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30 package s390x
31
32 import (
33 "cmd/internal/obj"
34 "cmd/internal/objabi"
35 "fmt"
36 "log"
37 "math"
38 "slices"
39 )
40
41
42
43
44 type ctxtz struct {
45 ctxt *obj.Link
46 newprog obj.ProgAlloc
47 cursym *obj.LSym
48 autosize int32
49 instoffset int64
50 pc int64
51 }
52
53
54 const (
55 funcAlign = 16
56 )
57
58 type Optab struct {
59 as obj.As
60 i uint8
61 a1 uint8
62 a2 uint8
63 a3 uint8
64 a4 uint8
65 a5 uint8
66 a6 uint8
67 }
68
69 var optab = []Optab{
70
71 {i: 0, as: obj.ATEXT, a1: C_ADDR, a6: C_TEXTSIZE},
72 {i: 0, as: obj.ATEXT, a1: C_ADDR, a3: C_LCON, a6: C_TEXTSIZE},
73 {i: 0, as: obj.APCDATA, a1: C_LCON, a6: C_LCON},
74 {i: 0, as: obj.AFUNCDATA, a1: C_SCON, a6: C_ADDR},
75 {i: 0, as: obj.ANOP},
76 {i: 0, as: obj.ANOP, a1: C_SAUTO},
77
78
79 {i: 1, as: AMOVD, a1: C_REG, a6: C_REG},
80 {i: 1, as: AMOVB, a1: C_REG, a6: C_REG},
81 {i: 1, as: AMOVBZ, a1: C_REG, a6: C_REG},
82 {i: 1, as: AMOVW, a1: C_REG, a6: C_REG},
83 {i: 1, as: AMOVWZ, a1: C_REG, a6: C_REG},
84 {i: 1, as: AFMOVD, a1: C_FREG, a6: C_FREG},
85 {i: 1, as: AMOVDBR, a1: C_REG, a6: C_REG},
86
87
88 {i: 26, as: AMOVD, a1: C_LACON, a6: C_REG},
89 {i: 26, as: AMOVW, a1: C_LACON, a6: C_REG},
90 {i: 26, as: AMOVWZ, a1: C_LACON, a6: C_REG},
91 {i: 3, as: AMOVD, a1: C_DCON, a6: C_REG},
92 {i: 3, as: AMOVW, a1: C_DCON, a6: C_REG},
93 {i: 3, as: AMOVWZ, a1: C_DCON, a6: C_REG},
94 {i: 3, as: AMOVB, a1: C_DCON, a6: C_REG},
95 {i: 3, as: AMOVBZ, a1: C_DCON, a6: C_REG},
96
97
98 {i: 72, as: AMOVD, a1: C_SCON, a6: C_LAUTO},
99 {i: 72, as: AMOVD, a1: C_ADDCON, a6: C_LAUTO},
100 {i: 72, as: AMOVW, a1: C_SCON, a6: C_LAUTO},
101 {i: 72, as: AMOVW, a1: C_ADDCON, a6: C_LAUTO},
102 {i: 72, as: AMOVWZ, a1: C_SCON, a6: C_LAUTO},
103 {i: 72, as: AMOVWZ, a1: C_ADDCON, a6: C_LAUTO},
104 {i: 72, as: AMOVB, a1: C_SCON, a6: C_LAUTO},
105 {i: 72, as: AMOVB, a1: C_ADDCON, a6: C_LAUTO},
106 {i: 72, as: AMOVBZ, a1: C_SCON, a6: C_LAUTO},
107 {i: 72, as: AMOVBZ, a1: C_ADDCON, a6: C_LAUTO},
108 {i: 72, as: AMOVD, a1: C_SCON, a6: C_LOREG},
109 {i: 72, as: AMOVD, a1: C_ADDCON, a6: C_LOREG},
110 {i: 72, as: AMOVW, a1: C_SCON, a6: C_LOREG},
111 {i: 72, as: AMOVW, a1: C_ADDCON, a6: C_LOREG},
112 {i: 72, as: AMOVWZ, a1: C_SCON, a6: C_LOREG},
113 {i: 72, as: AMOVWZ, a1: C_ADDCON, a6: C_LOREG},
114 {i: 72, as: AMOVB, a1: C_SCON, a6: C_LOREG},
115 {i: 72, as: AMOVB, a1: C_ADDCON, a6: C_LOREG},
116 {i: 72, as: AMOVBZ, a1: C_SCON, a6: C_LOREG},
117 {i: 72, as: AMOVBZ, a1: C_ADDCON, a6: C_LOREG},
118
119
120 {i: 35, as: AMOVD, a1: C_REG, a6: C_LAUTO},
121 {i: 35, as: AMOVW, a1: C_REG, a6: C_LAUTO},
122 {i: 35, as: AMOVWZ, a1: C_REG, a6: C_LAUTO},
123 {i: 35, as: AMOVBZ, a1: C_REG, a6: C_LAUTO},
124 {i: 35, as: AMOVB, a1: C_REG, a6: C_LAUTO},
125 {i: 35, as: AMOVDBR, a1: C_REG, a6: C_LAUTO},
126 {i: 35, as: AMOVHBR, a1: C_REG, a6: C_LAUTO},
127 {i: 35, as: AMOVD, a1: C_REG, a6: C_LOREG},
128 {i: 35, as: AMOVW, a1: C_REG, a6: C_LOREG},
129 {i: 35, as: AMOVWZ, a1: C_REG, a6: C_LOREG},
130 {i: 35, as: AMOVBZ, a1: C_REG, a6: C_LOREG},
131 {i: 35, as: AMOVB, a1: C_REG, a6: C_LOREG},
132 {i: 35, as: AMOVDBR, a1: C_REG, a6: C_LOREG},
133 {i: 35, as: AMOVHBR, a1: C_REG, a6: C_LOREG},
134 {i: 74, as: AMOVD, a1: C_REG, a6: C_ADDR},
135 {i: 74, as: AMOVW, a1: C_REG, a6: C_ADDR},
136 {i: 74, as: AMOVWZ, a1: C_REG, a6: C_ADDR},
137 {i: 74, as: AMOVBZ, a1: C_REG, a6: C_ADDR},
138 {i: 74, as: AMOVB, a1: C_REG, a6: C_ADDR},
139
140
141 {i: 36, as: AMOVD, a1: C_LAUTO, a6: C_REG},
142 {i: 36, as: AMOVW, a1: C_LAUTO, a6: C_REG},
143 {i: 36, as: AMOVWZ, a1: C_LAUTO, a6: C_REG},
144 {i: 36, as: AMOVBZ, a1: C_LAUTO, a6: C_REG},
145 {i: 36, as: AMOVB, a1: C_LAUTO, a6: C_REG},
146 {i: 36, as: AMOVDBR, a1: C_LAUTO, a6: C_REG},
147 {i: 36, as: AMOVHBR, a1: C_LAUTO, a6: C_REG},
148 {i: 36, as: AMOVD, a1: C_LOREG, a6: C_REG},
149 {i: 36, as: AMOVW, a1: C_LOREG, a6: C_REG},
150 {i: 36, as: AMOVWZ, a1: C_LOREG, a6: C_REG},
151 {i: 36, as: AMOVBZ, a1: C_LOREG, a6: C_REG},
152 {i: 36, as: AMOVB, a1: C_LOREG, a6: C_REG},
153 {i: 36, as: AMOVDBR, a1: C_LOREG, a6: C_REG},
154 {i: 36, as: AMOVHBR, a1: C_LOREG, a6: C_REG},
155 {i: 75, as: AMOVD, a1: C_ADDR, a6: C_REG},
156 {i: 75, as: AMOVW, a1: C_ADDR, a6: C_REG},
157 {i: 75, as: AMOVWZ, a1: C_ADDR, a6: C_REG},
158 {i: 75, as: AMOVBZ, a1: C_ADDR, a6: C_REG},
159 {i: 75, as: AMOVB, a1: C_ADDR, a6: C_REG},
160
161
162 {i: 99, as: ALAAG, a1: C_REG, a2: C_REG, a6: C_LOREG},
163
164
165 {i: 2, as: AADD, a1: C_REG, a2: C_REG, a6: C_REG},
166 {i: 2, as: AADD, a1: C_REG, a6: C_REG},
167 {i: 22, as: AADD, a1: C_LCON, a2: C_REG, a6: C_REG},
168 {i: 22, as: AADD, a1: C_LCON, a6: C_REG},
169 {i: 12, as: AADD, a1: C_LOREG, a6: C_REG},
170 {i: 12, as: AADD, a1: C_LAUTO, a6: C_REG},
171 {i: 21, as: ASUB, a1: C_LCON, a2: C_REG, a6: C_REG},
172 {i: 21, as: ASUB, a1: C_LCON, a6: C_REG},
173 {i: 12, as: ASUB, a1: C_LOREG, a6: C_REG},
174 {i: 12, as: ASUB, a1: C_LAUTO, a6: C_REG},
175 {i: 4, as: AMULHD, a1: C_REG, a6: C_REG},
176 {i: 4, as: AMULHD, a1: C_REG, a2: C_REG, a6: C_REG},
177 {i: 62, as: AMLGR, a1: C_REG, a6: C_REG},
178 {i: 2, as: ADIVW, a1: C_REG, a2: C_REG, a6: C_REG},
179 {i: 2, as: ADIVW, a1: C_REG, a6: C_REG},
180 {i: 10, as: ASUB, a1: C_REG, a2: C_REG, a6: C_REG},
181 {i: 10, as: ASUB, a1: C_REG, a6: C_REG},
182 {i: 47, as: ANEG, a1: C_REG, a6: C_REG},
183 {i: 47, as: ANEG, a6: C_REG},
184
185
186 {i: 6, as: AAND, a1: C_REG, a2: C_REG, a6: C_REG},
187 {i: 6, as: AAND, a1: C_REG, a6: C_REG},
188 {i: 23, as: AAND, a1: C_LCON, a6: C_REG},
189 {i: 12, as: AAND, a1: C_LOREG, a6: C_REG},
190 {i: 12, as: AAND, a1: C_LAUTO, a6: C_REG},
191 {i: 6, as: AANDW, a1: C_REG, a2: C_REG, a6: C_REG},
192 {i: 6, as: AANDW, a1: C_REG, a6: C_REG},
193 {i: 24, as: AANDW, a1: C_LCON, a6: C_REG},
194 {i: 12, as: AANDW, a1: C_LOREG, a6: C_REG},
195 {i: 12, as: AANDW, a1: C_LAUTO, a6: C_REG},
196 {i: 7, as: ASLD, a1: C_REG, a6: C_REG},
197 {i: 7, as: ASLD, a1: C_REG, a2: C_REG, a6: C_REG},
198 {i: 7, as: ASLD, a1: C_SCON, a2: C_REG, a6: C_REG},
199 {i: 7, as: ASLD, a1: C_SCON, a6: C_REG},
200 {i: 13, as: ARNSBG, a1: C_SCON, a3: C_SCON, a4: C_SCON, a5: C_REG, a6: C_REG},
201
202
203 {i: 79, as: ACSG, a1: C_REG, a2: C_REG, a6: C_SOREG},
204
205
206 {i: 32, as: AFADD, a1: C_FREG, a6: C_FREG},
207 {i: 33, as: AFABS, a1: C_FREG, a6: C_FREG},
208 {i: 33, as: AFABS, a6: C_FREG},
209 {i: 34, as: AFMADD, a1: C_FREG, a2: C_FREG, a6: C_FREG},
210 {i: 32, as: AFMUL, a1: C_FREG, a6: C_FREG},
211 {i: 36, as: AFMOVD, a1: C_LAUTO, a6: C_FREG},
212 {i: 36, as: AFMOVD, a1: C_LOREG, a6: C_FREG},
213 {i: 75, as: AFMOVD, a1: C_ADDR, a6: C_FREG},
214 {i: 35, as: AFMOVD, a1: C_FREG, a6: C_LAUTO},
215 {i: 35, as: AFMOVD, a1: C_FREG, a6: C_LOREG},
216 {i: 74, as: AFMOVD, a1: C_FREG, a6: C_ADDR},
217 {i: 67, as: AFMOVD, a1: C_ZCON, a6: C_FREG},
218 {i: 81, as: ALDGR, a1: C_REG, a6: C_FREG},
219 {i: 81, as: ALGDR, a1: C_FREG, a6: C_REG},
220 {i: 82, as: ACEFBRA, a1: C_REG, a6: C_FREG},
221 {i: 83, as: ACFEBRA, a1: C_FREG, a6: C_REG},
222 {i: 48, as: AFIEBR, a1: C_SCON, a2: C_FREG, a6: C_FREG},
223 {i: 49, as: ACPSDR, a1: C_FREG, a2: C_FREG, a6: C_FREG},
224 {i: 50, as: ALTDBR, a1: C_FREG, a6: C_FREG},
225 {i: 51, as: ATCDB, a1: C_FREG, a6: C_SCON},
226
227
228 {i: 19, as: AMOVD, a1: C_SYMADDR, a6: C_REG},
229 {i: 93, as: AMOVD, a1: C_GOTADDR, a6: C_REG},
230 {i: 94, as: AMOVD, a1: C_TLS_LE, a6: C_REG},
231 {i: 95, as: AMOVD, a1: C_TLS_IE, a6: C_REG},
232
233
234 {i: 5, as: ASYSCALL},
235 {i: 77, as: ASYSCALL, a1: C_SCON},
236
237
238 {i: 16, as: ABEQ, a6: C_SBRA},
239 {i: 16, as: ABRC, a1: C_SCON, a6: C_SBRA},
240 {i: 11, as: ABR, a6: C_LBRA},
241 {i: 16, as: ABC, a1: C_SCON, a2: C_REG, a6: C_LBRA},
242 {i: 18, as: ABR, a6: C_REG},
243 {i: 18, as: ABR, a1: C_REG, a6: C_REG},
244 {i: 15, as: ABR, a6: C_ZOREG},
245 {i: 15, as: ABC, a6: C_ZOREG},
246
247
248 {i: 89, as: ACGRJ, a1: C_SCON, a2: C_REG, a3: C_REG, a6: C_SBRA},
249 {i: 89, as: ACMPBEQ, a1: C_REG, a2: C_REG, a6: C_SBRA},
250 {i: 89, as: ACLGRJ, a1: C_SCON, a2: C_REG, a3: C_REG, a6: C_SBRA},
251 {i: 89, as: ACMPUBEQ, a1: C_REG, a2: C_REG, a6: C_SBRA},
252 {i: 90, as: ACGIJ, a1: C_SCON, a2: C_REG, a3: C_ADDCON, a6: C_SBRA},
253 {i: 90, as: ACGIJ, a1: C_SCON, a2: C_REG, a3: C_SCON, a6: C_SBRA},
254 {i: 90, as: ACMPBEQ, a1: C_REG, a3: C_ADDCON, a6: C_SBRA},
255 {i: 90, as: ACMPBEQ, a1: C_REG, a3: C_SCON, a6: C_SBRA},
256 {i: 90, as: ACLGIJ, a1: C_SCON, a2: C_REG, a3: C_ADDCON, a6: C_SBRA},
257 {i: 90, as: ACMPUBEQ, a1: C_REG, a3: C_ANDCON, a6: C_SBRA},
258
259
260 {i: 41, as: ABRCT, a1: C_REG, a6: C_SBRA},
261 {i: 41, as: ABRCTG, a1: C_REG, a6: C_SBRA},
262
263
264 {i: 17, as: AMOVDEQ, a1: C_REG, a6: C_REG},
265
266
267 {i: 25, as: ALOCGR, a1: C_SCON, a2: C_REG, a6: C_REG},
268
269
270 {i: 8, as: AFLOGR, a1: C_REG, a6: C_REG},
271
272
273 {i: 9, as: APOPCNT, a1: C_REG, a6: C_REG},
274
275
276 {i: 70, as: ACMP, a1: C_REG, a6: C_REG},
277 {i: 71, as: ACMP, a1: C_REG, a6: C_LCON},
278 {i: 70, as: ACMPU, a1: C_REG, a6: C_REG},
279 {i: 71, as: ACMPU, a1: C_REG, a6: C_LCON},
280 {i: 70, as: AFCMPO, a1: C_FREG, a6: C_FREG},
281 {i: 70, as: AFCMPO, a1: C_FREG, a2: C_REG, a6: C_FREG},
282
283
284 {i: 91, as: ATMHH, a1: C_REG, a6: C_ANDCON},
285
286
287 {i: 92, as: AIPM, a1: C_REG},
288
289
290 {i: 76, as: ASPM, a1: C_REG},
291
292
293 {i: 68, as: AMOVW, a1: C_AREG, a6: C_REG},
294 {i: 68, as: AMOVWZ, a1: C_AREG, a6: C_REG},
295 {i: 69, as: AMOVW, a1: C_REG, a6: C_AREG},
296 {i: 69, as: AMOVWZ, a1: C_REG, a6: C_AREG},
297
298
299 {i: 96, as: ACLEAR, a1: C_LCON, a6: C_LOREG},
300 {i: 96, as: ACLEAR, a1: C_LCON, a6: C_LAUTO},
301
302
303 {i: 97, as: ASTMG, a1: C_REG, a2: C_REG, a6: C_LOREG},
304 {i: 97, as: ASTMG, a1: C_REG, a2: C_REG, a6: C_LAUTO},
305 {i: 98, as: ALMG, a1: C_LOREG, a2: C_REG, a6: C_REG},
306 {i: 98, as: ALMG, a1: C_LAUTO, a2: C_REG, a6: C_REG},
307
308
309 {i: 40, as: ABYTE, a1: C_SCON},
310 {i: 40, as: AWORD, a1: C_LCON},
311 {i: 31, as: ADWORD, a1: C_LCON},
312 {i: 31, as: ADWORD, a1: C_DCON},
313
314
315 {i: 80, as: ASYNC},
316
317
318 {i: 88, as: ASTCK, a6: C_SAUTO},
319 {i: 88, as: ASTCK, a6: C_SOREG},
320
321
322 {i: 84, as: AMVC, a1: C_SCON, a3: C_LOREG, a6: C_LOREG},
323 {i: 84, as: AMVC, a1: C_SCON, a3: C_LOREG, a6: C_LAUTO},
324 {i: 84, as: AMVC, a1: C_SCON, a3: C_LAUTO, a6: C_LAUTO},
325
326
327 {i: 85, as: ALARL, a1: C_LCON, a6: C_REG},
328 {i: 85, as: ALARL, a1: C_SYMADDR, a6: C_REG},
329 {i: 86, as: ALA, a1: C_SOREG, a6: C_REG},
330 {i: 86, as: ALA, a1: C_SAUTO, a6: C_REG},
331 {i: 87, as: AEXRL, a1: C_SYMADDR, a6: C_REG},
332
333
334 {i: 78, as: obj.AUNDEF},
335
336
337 {i: 73, as: ABRRK},
338
339
340 {i: 66, as: ANOPH},
341
342
343
344
345 {i: 124, as: AKM, a1: C_REG, a6: C_REG},
346
347
348 {i: 125, as: AKDSA, a1: C_REG, a6: C_REG},
349
350
351 {i: 126, as: AKMA, a1: C_REG, a2: C_REG, a6: C_REG},
352
353
354
355
356 {i: 100, as: AVST, a1: C_VREG, a6: C_SOREG},
357 {i: 100, as: AVST, a1: C_VREG, a6: C_SAUTO},
358 {i: 100, as: AVSTEG, a1: C_SCON, a2: C_VREG, a6: C_SOREG},
359 {i: 100, as: AVSTEG, a1: C_SCON, a2: C_VREG, a6: C_SAUTO},
360
361
362 {i: 101, as: AVL, a1: C_SOREG, a6: C_VREG},
363 {i: 101, as: AVL, a1: C_SAUTO, a6: C_VREG},
364 {i: 101, as: AVLEG, a1: C_SCON, a3: C_SOREG, a6: C_VREG},
365 {i: 101, as: AVLEG, a1: C_SCON, a3: C_SAUTO, a6: C_VREG},
366
367
368 {i: 102, as: AVSCEG, a1: C_SCON, a2: C_VREG, a6: C_SOREG},
369 {i: 102, as: AVSCEG, a1: C_SCON, a2: C_VREG, a6: C_SAUTO},
370
371
372 {i: 103, as: AVGEG, a1: C_SCON, a3: C_SOREG, a6: C_VREG},
373 {i: 103, as: AVGEG, a1: C_SCON, a3: C_SAUTO, a6: C_VREG},
374
375
376 {i: 104, as: AVESLG, a1: C_SCON, a2: C_VREG, a6: C_VREG},
377 {i: 104, as: AVESLG, a1: C_REG, a2: C_VREG, a6: C_VREG},
378 {i: 104, as: AVESLG, a1: C_SCON, a6: C_VREG},
379 {i: 104, as: AVESLG, a1: C_REG, a6: C_VREG},
380 {i: 104, as: AVLGVG, a1: C_SCON, a2: C_VREG, a6: C_REG},
381 {i: 104, as: AVLGVG, a1: C_REG, a2: C_VREG, a6: C_REG},
382 {i: 104, as: AVLVGG, a1: C_SCON, a2: C_REG, a6: C_VREG},
383 {i: 104, as: AVLVGG, a1: C_REG, a2: C_REG, a6: C_VREG},
384
385
386 {i: 105, as: AVSTM, a1: C_VREG, a2: C_VREG, a6: C_SOREG},
387 {i: 105, as: AVSTM, a1: C_VREG, a2: C_VREG, a6: C_SAUTO},
388
389
390 {i: 106, as: AVLM, a1: C_SOREG, a2: C_VREG, a6: C_VREG},
391 {i: 106, as: AVLM, a1: C_SAUTO, a2: C_VREG, a6: C_VREG},
392
393
394 {i: 107, as: AVSTL, a1: C_REG, a2: C_VREG, a6: C_SOREG},
395 {i: 107, as: AVSTL, a1: C_REG, a2: C_VREG, a6: C_SAUTO},
396
397
398 {i: 108, as: AVLL, a1: C_REG, a3: C_SOREG, a6: C_VREG},
399 {i: 108, as: AVLL, a1: C_REG, a3: C_SAUTO, a6: C_VREG},
400
401
402 {i: 109, as: AVGBM, a1: C_ANDCON, a6: C_VREG},
403 {i: 109, as: AVZERO, a6: C_VREG},
404 {i: 109, as: AVREPIG, a1: C_ADDCON, a6: C_VREG},
405 {i: 109, as: AVREPIG, a1: C_SCON, a6: C_VREG},
406 {i: 109, as: AVLEIG, a1: C_SCON, a3: C_ADDCON, a6: C_VREG},
407 {i: 109, as: AVLEIG, a1: C_SCON, a3: C_SCON, a6: C_VREG},
408
409
410 {i: 110, as: AVGMG, a1: C_SCON, a3: C_SCON, a6: C_VREG},
411
412
413 {i: 111, as: AVREPG, a1: C_UCON, a2: C_VREG, a6: C_VREG},
414
415
416
417 {i: 112, as: AVERIMG, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG},
418 {i: 112, as: AVSLDB, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG},
419
420
421 {i: 113, as: AVFTCIDB, a1: C_SCON, a2: C_VREG, a6: C_VREG},
422
423
424 {i: 114, as: AVLR, a1: C_VREG, a6: C_VREG},
425
426
427 {i: 115, as: AVECG, a1: C_VREG, a6: C_VREG},
428
429
430 {i: 117, as: AVCEQG, a1: C_VREG, a2: C_VREG, a6: C_VREG},
431 {i: 117, as: AVFAEF, a1: C_VREG, a2: C_VREG, a6: C_VREG},
432 {i: 117, as: AVPKSG, a1: C_VREG, a2: C_VREG, a6: C_VREG},
433
434
435 {i: 118, as: AVAQ, a1: C_VREG, a2: C_VREG, a6: C_VREG},
436 {i: 118, as: AVAQ, a1: C_VREG, a6: C_VREG},
437 {i: 118, as: AVNOT, a1: C_VREG, a6: C_VREG},
438 {i: 123, as: AVPDI, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG},
439
440
441 {i: 119, as: AVERLLVG, a1: C_VREG, a2: C_VREG, a6: C_VREG},
442 {i: 119, as: AVERLLVG, a1: C_VREG, a6: C_VREG},
443
444
445 {i: 128, as: AVFMAXDB, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG},
446 {i: 128, as: AWFMAXDB, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG},
447 {i: 128, as: AWFMAXDB, a1: C_SCON, a2: C_FREG, a3: C_FREG, a6: C_FREG},
448
449
450 {i: 120, as: AVACQ, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG},
451
452
453 {i: 121, as: AVSEL, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG},
454
455
456 {i: 122, as: AVLVGP, a1: C_REG, a2: C_REG, a6: C_VREG},
457
458
459 {i: 127, as: AMVCLE, a1: C_LOREG, a2: C_REG, a6: C_REG},
460 {i: 127, as: AMVCLE, a1: C_SCON, a2: C_REG, a6: C_REG},
461 }
462
463 var oprange [ALAST & obj.AMask][]Optab
464
465 var xcmp [C_NCLASS][C_NCLASS]bool
466
467 func spanz(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) {
468 if ctxt.Retpoline {
469 ctxt.Diag("-spectre=ret not supported on s390x")
470 ctxt.Retpoline = false
471 }
472
473 p := cursym.Func().Text
474 if p == nil || p.Link == nil {
475 return
476 }
477
478 if oprange[AORW&obj.AMask] == nil {
479 ctxt.Diag("s390x ops not initialized, call s390x.buildop first")
480 }
481
482 c := ctxtz{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset)}
483
484 buffer := make([]byte, 0)
485 changed := true
486 loop := 0
487 nrelocs0 := len(c.cursym.R)
488 for changed {
489 if loop > 100 {
490 c.ctxt.Diag("stuck in spanz loop")
491 break
492 }
493 changed = false
494 buffer = buffer[:0]
495 for i := range c.cursym.R[nrelocs0:] {
496 c.cursym.R[nrelocs0+i] = obj.Reloc{}
497 }
498 c.cursym.R = c.cursym.R[:nrelocs0]
499 for p := c.cursym.Func().Text; p != nil; p = p.Link {
500 pc := int64(len(buffer))
501 if pc != p.Pc {
502 changed = true
503 }
504 p.Pc = pc
505 c.pc = p.Pc
506 c.asmout(p, &buffer)
507 if pc == int64(len(buffer)) {
508 switch p.As {
509 case obj.ANOP, obj.AFUNCDATA, obj.APCDATA, obj.ATEXT:
510
511 default:
512 c.ctxt.Diag("zero-width instruction\n%v", p)
513 }
514 }
515 }
516 loop++
517 }
518
519 c.cursym.Size = int64(len(buffer))
520 if c.cursym.Size%funcAlign != 0 {
521 c.cursym.Size += funcAlign - (c.cursym.Size % funcAlign)
522 }
523 c.cursym.Grow(c.cursym.Size)
524 copy(c.cursym.P, buffer)
525
526
527
528
529
530 obj.MarkUnsafePoints(c.ctxt, c.cursym.Func().Text, c.newprog, c.isUnsafePoint, nil)
531 }
532
533
534 func (c *ctxtz) isUnsafePoint(p *obj.Prog) bool {
535 if p.From.Reg == REGTMP || p.To.Reg == REGTMP || p.Reg == REGTMP {
536 return true
537 }
538 for _, a := range p.RestArgs {
539 if a.Reg == REGTMP {
540 return true
541 }
542 }
543 return p.Mark&USETMP != 0
544 }
545
546 func isint32(v int64) bool {
547 return int64(int32(v)) == v
548 }
549
550 func isuint32(v uint64) bool {
551 return uint64(uint32(v)) == v
552 }
553
554 func (c *ctxtz) aclass(a *obj.Addr) int {
555 switch a.Type {
556 case obj.TYPE_NONE:
557 return C_NONE
558
559 case obj.TYPE_REG:
560 if REG_R0 <= a.Reg && a.Reg <= REG_R15 {
561 return C_REG
562 }
563 if REG_F0 <= a.Reg && a.Reg <= REG_F15 {
564 return C_FREG
565 }
566 if REG_AR0 <= a.Reg && a.Reg <= REG_AR15 {
567 return C_AREG
568 }
569 if REG_V0 <= a.Reg && a.Reg <= REG_V31 {
570 return C_VREG
571 }
572 return C_GOK
573
574 case obj.TYPE_MEM:
575 switch a.Name {
576 case obj.NAME_EXTERN,
577 obj.NAME_STATIC:
578 if a.Sym == nil {
579
580 break
581 }
582 c.instoffset = a.Offset
583 if a.Sym.Type == objabi.STLSBSS {
584 if c.ctxt.Flag_shared {
585 return C_TLS_IE
586 }
587 return C_TLS_LE
588 }
589 return C_ADDR
590
591 case obj.NAME_GOTREF:
592 return C_GOTADDR
593
594 case obj.NAME_AUTO:
595 if a.Reg == REGSP {
596
597
598 a.Reg = obj.REG_NONE
599 }
600 c.instoffset = int64(c.autosize) + a.Offset
601 if c.instoffset >= -BIG && c.instoffset < BIG {
602 return C_SAUTO
603 }
604 return C_LAUTO
605
606 case obj.NAME_PARAM:
607 if a.Reg == REGSP {
608
609
610 a.Reg = obj.REG_NONE
611 }
612 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize
613 if c.instoffset >= -BIG && c.instoffset < BIG {
614 return C_SAUTO
615 }
616 return C_LAUTO
617
618 case obj.NAME_NONE:
619 c.instoffset = a.Offset
620 if c.instoffset == 0 {
621 return C_ZOREG
622 }
623 if c.instoffset >= -BIG && c.instoffset < BIG {
624 return C_SOREG
625 }
626 return C_LOREG
627 }
628
629 return C_GOK
630
631 case obj.TYPE_TEXTSIZE:
632 return C_TEXTSIZE
633
634 case obj.TYPE_FCONST:
635 if f64, ok := a.Val.(float64); ok && math.Float64bits(f64) == 0 {
636 return C_ZCON
637 }
638 c.ctxt.Diag("cannot handle the floating point constant %v", a.Val)
639
640 case obj.TYPE_CONST,
641 obj.TYPE_ADDR:
642 switch a.Name {
643 case obj.NAME_NONE:
644 c.instoffset = a.Offset
645 if a.Reg != 0 {
646 if -BIG <= c.instoffset && c.instoffset <= BIG {
647 return C_SACON
648 }
649 if isint32(c.instoffset) {
650 return C_LACON
651 }
652 return C_DACON
653 }
654
655 case obj.NAME_EXTERN,
656 obj.NAME_STATIC:
657 s := a.Sym
658 if s == nil {
659 return C_GOK
660 }
661 c.instoffset = a.Offset
662
663 return C_SYMADDR
664
665 case obj.NAME_AUTO:
666 if a.Reg == REGSP {
667
668
669 a.Reg = obj.REG_NONE
670 }
671 c.instoffset = int64(c.autosize) + a.Offset
672 if c.instoffset >= -BIG && c.instoffset < BIG {
673 return C_SACON
674 }
675 return C_LACON
676
677 case obj.NAME_PARAM:
678 if a.Reg == REGSP {
679
680
681 a.Reg = obj.REG_NONE
682 }
683 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize
684 if c.instoffset >= -BIG && c.instoffset < BIG {
685 return C_SACON
686 }
687 return C_LACON
688
689 default:
690 return C_GOK
691 }
692
693 if c.instoffset == 0 {
694 return C_ZCON
695 }
696 if c.instoffset >= 0 {
697 if c.instoffset <= 0x7fff {
698 return C_SCON
699 }
700 if c.instoffset <= 0xffff {
701 return C_ANDCON
702 }
703 if c.instoffset&0xffff == 0 && isuint32(uint64(c.instoffset)) {
704 return C_UCON
705 }
706 if isint32(c.instoffset) || isuint32(uint64(c.instoffset)) {
707 return C_LCON
708 }
709 return C_DCON
710 }
711
712 if c.instoffset >= -0x8000 {
713 return C_ADDCON
714 }
715 if c.instoffset&0xffff == 0 && isint32(c.instoffset) {
716 return C_UCON
717 }
718 if isint32(c.instoffset) {
719 return C_LCON
720 }
721 return C_DCON
722
723 case obj.TYPE_BRANCH:
724 return C_SBRA
725 }
726
727 return C_GOK
728 }
729
730 func (c *ctxtz) oplook(p *obj.Prog) *Optab {
731
732 if p.Optab != 0 {
733 return &optab[p.Optab-1]
734 }
735 if len(p.RestArgs) > 3 {
736 c.ctxt.Diag("too many RestArgs: got %v, maximum is 3\n", len(p.RestArgs))
737 return nil
738 }
739
740
741 p.From.Class = int8(c.aclass(&p.From) + 1)
742 p.To.Class = int8(c.aclass(&p.To) + 1)
743 for i := range p.RestArgs {
744 p.RestArgs[i].Addr.Class = int8(c.aclass(&p.RestArgs[i].Addr) + 1)
745 }
746
747
748 args := [...]int8{
749 p.From.Class - 1,
750 C_NONE,
751 C_NONE,
752 C_NONE,
753 C_NONE,
754 p.To.Class - 1,
755 }
756
757 switch {
758 case REG_R0 <= p.Reg && p.Reg <= REG_R15:
759 args[1] = C_REG
760 case REG_V0 <= p.Reg && p.Reg <= REG_V31:
761 args[1] = C_VREG
762 case REG_F0 <= p.Reg && p.Reg <= REG_F15:
763 args[1] = C_FREG
764 case REG_AR0 <= p.Reg && p.Reg <= REG_AR15:
765 args[1] = C_AREG
766 }
767
768 for i, a := range p.RestArgs {
769 args[2+i] = a.Class - 1
770 }
771
772
773 ops := oprange[p.As&obj.AMask]
774 cmp := [len(args)]*[C_NCLASS]bool{}
775 for i := range cmp {
776 cmp[i] = &xcmp[args[i]]
777 }
778 for i := range ops {
779 op := &ops[i]
780 if cmp[0][op.a1] && cmp[1][op.a2] &&
781 cmp[2][op.a3] && cmp[3][op.a4] &&
782 cmp[4][op.a5] && cmp[5][op.a6] {
783 p.Optab = uint16(cap(optab) - cap(ops) + i + 1)
784 return op
785 }
786 }
787
788
789 s := ""
790 for _, a := range args {
791 s += fmt.Sprintf(" %v", DRconv(int(a)))
792 }
793 c.ctxt.Diag("illegal combination %v%v\n", p.As, s)
794 c.ctxt.Diag("prog: %v\n", p)
795 return nil
796 }
797
798 func cmp(a int, b int) bool {
799 if a == b {
800 return true
801 }
802 switch a {
803 case C_DCON:
804 if b == C_LCON {
805 return true
806 }
807 fallthrough
808 case C_LCON:
809 if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON {
810 return true
811 }
812
813 case C_ADDCON:
814 if b == C_ZCON || b == C_SCON {
815 return true
816 }
817
818 case C_ANDCON:
819 if b == C_ZCON || b == C_SCON {
820 return true
821 }
822
823 case C_UCON:
824 if b == C_ZCON || b == C_SCON {
825 return true
826 }
827
828 case C_SCON:
829 if b == C_ZCON {
830 return true
831 }
832
833 case C_LACON:
834 if b == C_SACON {
835 return true
836 }
837
838 case C_LBRA:
839 if b == C_SBRA {
840 return true
841 }
842
843 case C_LAUTO:
844 if b == C_SAUTO {
845 return true
846 }
847
848 case C_LOREG:
849 if b == C_ZOREG || b == C_SOREG {
850 return true
851 }
852
853 case C_SOREG:
854 if b == C_ZOREG {
855 return true
856 }
857
858 case C_ANY:
859 return true
860 }
861
862 return false
863 }
864
865 func ocmp(p1, p2 Optab) int {
866 if p1.as != p2.as {
867 return int(p1.as) - int(p2.as)
868 }
869 if p1.a1 != p2.a1 {
870 return int(p1.a1) - int(p2.a1)
871 }
872 if p1.a2 != p2.a2 {
873 return int(p1.a2) - int(p2.a2)
874 }
875 if p1.a3 != p2.a3 {
876 return int(p1.a3) - int(p2.a3)
877 }
878 if p1.a4 != p2.a4 {
879 return int(p1.a4) - int(p2.a4)
880 }
881 return 0
882 }
883 func opset(a, b obj.As) {
884 oprange[a&obj.AMask] = oprange[b&obj.AMask]
885 }
886
887 func buildop(ctxt *obj.Link) {
888 if oprange[AORW&obj.AMask] != nil {
889
890
891
892 return
893 }
894
895 for i := 0; i < C_NCLASS; i++ {
896 for n := 0; n < C_NCLASS; n++ {
897 if cmp(n, i) {
898 xcmp[i][n] = true
899 }
900 }
901 }
902 slices.SortFunc(optab, ocmp)
903 for i := 0; i < len(optab); i++ {
904 r := optab[i].as
905 start := i
906 for ; i+1 < len(optab); i++ {
907 if optab[i+1].as != r {
908 break
909 }
910 }
911 oprange[r&obj.AMask] = optab[start : i+1]
912
913
914
915 switch r {
916 case AADD:
917 opset(AADDC, r)
918 opset(AADDW, r)
919 opset(AADDE, r)
920 opset(AMULLD, r)
921 opset(AMULLW, r)
922 case ADIVW:
923 opset(ADIVD, r)
924 opset(ADIVDU, r)
925 opset(ADIVWU, r)
926 opset(AMODD, r)
927 opset(AMODDU, r)
928 opset(AMODW, r)
929 opset(AMODWU, r)
930 case AMULHD:
931 opset(AMULHDU, r)
932 case AMOVBZ:
933 opset(AMOVH, r)
934 opset(AMOVHZ, r)
935 case ALA:
936 opset(ALAY, r)
937 case AMVC:
938 opset(AMVCIN, r)
939 opset(ACLC, r)
940 opset(AXC, r)
941 opset(AOC, r)
942 opset(ANC, r)
943 case ASTCK:
944 opset(ASTCKC, r)
945 opset(ASTCKE, r)
946 opset(ASTCKF, r)
947 case ALAAG:
948 opset(ALAA, r)
949 opset(ALAAL, r)
950 opset(ALAALG, r)
951 opset(ALAN, r)
952 opset(ALANG, r)
953 opset(ALAX, r)
954 opset(ALAXG, r)
955 opset(ALAO, r)
956 opset(ALAOG, r)
957 case ASTMG:
958 opset(ASTMY, r)
959 case ALMG:
960 opset(ALMY, r)
961 case ABEQ:
962 opset(ABGE, r)
963 opset(ABGT, r)
964 opset(ABLE, r)
965 opset(ABLT, r)
966 opset(ABNE, r)
967 opset(ABVC, r)
968 opset(ABVS, r)
969 opset(ABLEU, r)
970 opset(ABLTU, r)
971 case ABR:
972 opset(ABL, r)
973 case ABC:
974 opset(ABCL, r)
975 case AFABS:
976 opset(AFNABS, r)
977 opset(ALPDFR, r)
978 opset(ALNDFR, r)
979 opset(AFNEG, r)
980 opset(AFNEGS, r)
981 opset(ALCDBR, r)
982 opset(ALEDBR, r)
983 opset(ALDEBR, r)
984 opset(AFSQRT, r)
985 opset(AFSQRTS, r)
986 case AFADD:
987 opset(AFADDS, r)
988 opset(AFDIV, r)
989 opset(AFDIVS, r)
990 opset(AFSUB, r)
991 opset(AFSUBS, r)
992 case AFMADD:
993 opset(AFMADDS, r)
994 opset(AFMSUB, r)
995 opset(AFMSUBS, r)
996 case AFMUL:
997 opset(AFMULS, r)
998 case AFCMPO:
999 opset(AFCMPU, r)
1000 opset(ACEBR, r)
1001 case AAND:
1002 opset(AOR, r)
1003 opset(AXOR, r)
1004 case AANDW:
1005 opset(AORW, r)
1006 opset(AXORW, r)
1007 case ASLD:
1008 opset(ASRD, r)
1009 opset(ASLW, r)
1010 opset(ASRW, r)
1011 opset(ASRAD, r)
1012 opset(ASRAW, r)
1013 opset(ARLL, r)
1014 opset(ARLLG, r)
1015 case ARNSBG:
1016 opset(ARXSBG, r)
1017 opset(AROSBG, r)
1018 opset(ARNSBGT, r)
1019 opset(ARXSBGT, r)
1020 opset(AROSBGT, r)
1021 opset(ARISBG, r)
1022 opset(ARISBGN, r)
1023 opset(ARISBGZ, r)
1024 opset(ARISBGNZ, r)
1025 opset(ARISBHG, r)
1026 opset(ARISBLG, r)
1027 opset(ARISBHGZ, r)
1028 opset(ARISBLGZ, r)
1029 case ACSG:
1030 opset(ACS, r)
1031 case ASUB:
1032 opset(ASUBC, r)
1033 opset(ASUBE, r)
1034 opset(ASUBW, r)
1035 case ANEG:
1036 opset(ANEGW, r)
1037 case AFMOVD:
1038 opset(AFMOVS, r)
1039 case AMOVDBR:
1040 opset(AMOVWBR, r)
1041 case ACMP:
1042 opset(ACMPW, r)
1043 case ACMPU:
1044 opset(ACMPWU, r)
1045 case ATMHH:
1046 opset(ATMHL, r)
1047 opset(ATMLH, r)
1048 opset(ATMLL, r)
1049 case ACEFBRA:
1050 opset(ACDFBRA, r)
1051 opset(ACEGBRA, r)
1052 opset(ACDGBRA, r)
1053 opset(ACELFBR, r)
1054 opset(ACDLFBR, r)
1055 opset(ACELGBR, r)
1056 opset(ACDLGBR, r)
1057 case ACFEBRA:
1058 opset(ACFDBRA, r)
1059 opset(ACGEBRA, r)
1060 opset(ACGDBRA, r)
1061 opset(ACLFEBR, r)
1062 opset(ACLFDBR, r)
1063 opset(ACLGEBR, r)
1064 opset(ACLGDBR, r)
1065 case AFIEBR:
1066 opset(AFIDBR, r)
1067 case ACMPBEQ:
1068 opset(ACMPBGE, r)
1069 opset(ACMPBGT, r)
1070 opset(ACMPBLE, r)
1071 opset(ACMPBLT, r)
1072 opset(ACMPBNE, r)
1073 case ACMPUBEQ:
1074 opset(ACMPUBGE, r)
1075 opset(ACMPUBGT, r)
1076 opset(ACMPUBLE, r)
1077 opset(ACMPUBLT, r)
1078 opset(ACMPUBNE, r)
1079 case ACGRJ:
1080 opset(ACRJ, r)
1081 case ACLGRJ:
1082 opset(ACLRJ, r)
1083 case ACGIJ:
1084 opset(ACIJ, r)
1085 case ACLGIJ:
1086 opset(ACLIJ, r)
1087 case AMOVDEQ:
1088 opset(AMOVDGE, r)
1089 opset(AMOVDGT, r)
1090 opset(AMOVDLE, r)
1091 opset(AMOVDLT, r)
1092 opset(AMOVDNE, r)
1093 case ALOCGR:
1094 opset(ALOCR, r)
1095 case ALTDBR:
1096 opset(ALTEBR, r)
1097 case ATCDB:
1098 opset(ATCEB, r)
1099 case AVL:
1100 opset(AVLLEZB, r)
1101 opset(AVLLEZH, r)
1102 opset(AVLLEZF, r)
1103 opset(AVLLEZG, r)
1104 opset(AVLREPB, r)
1105 opset(AVLREPH, r)
1106 opset(AVLREPF, r)
1107 opset(AVLREPG, r)
1108 case AVLEG:
1109 opset(AVLBB, r)
1110 opset(AVLEB, r)
1111 opset(AVLEH, r)
1112 opset(AVLEF, r)
1113 opset(AVLEG, r)
1114 opset(AVLREP, r)
1115 case AVSTEG:
1116 opset(AVSTEB, r)
1117 opset(AVSTEH, r)
1118 opset(AVSTEF, r)
1119 case AVSCEG:
1120 opset(AVSCEF, r)
1121 case AVGEG:
1122 opset(AVGEF, r)
1123 case AVESLG:
1124 opset(AVESLB, r)
1125 opset(AVESLH, r)
1126 opset(AVESLF, r)
1127 opset(AVERLLB, r)
1128 opset(AVERLLH, r)
1129 opset(AVERLLF, r)
1130 opset(AVERLLG, r)
1131 opset(AVESRAB, r)
1132 opset(AVESRAH, r)
1133 opset(AVESRAF, r)
1134 opset(AVESRAG, r)
1135 opset(AVESRLB, r)
1136 opset(AVESRLH, r)
1137 opset(AVESRLF, r)
1138 opset(AVESRLG, r)
1139 case AVLGVG:
1140 opset(AVLGVB, r)
1141 opset(AVLGVH, r)
1142 opset(AVLGVF, r)
1143 case AVLVGG:
1144 opset(AVLVGB, r)
1145 opset(AVLVGH, r)
1146 opset(AVLVGF, r)
1147 case AVZERO:
1148 opset(AVONE, r)
1149 case AVREPIG:
1150 opset(AVREPIB, r)
1151 opset(AVREPIH, r)
1152 opset(AVREPIF, r)
1153 case AVLEIG:
1154 opset(AVLEIB, r)
1155 opset(AVLEIH, r)
1156 opset(AVLEIF, r)
1157 case AVGMG:
1158 opset(AVGMB, r)
1159 opset(AVGMH, r)
1160 opset(AVGMF, r)
1161 case AVREPG:
1162 opset(AVREPB, r)
1163 opset(AVREPH, r)
1164 opset(AVREPF, r)
1165 case AVERIMG:
1166 opset(AVERIMB, r)
1167 opset(AVERIMH, r)
1168 opset(AVERIMF, r)
1169 case AVFTCIDB:
1170 opset(AWFTCIDB, r)
1171 case AVLR:
1172 opset(AVUPHB, r)
1173 opset(AVUPHH, r)
1174 opset(AVUPHF, r)
1175 opset(AVUPLHB, r)
1176 opset(AVUPLHH, r)
1177 opset(AVUPLHF, r)
1178 opset(AVUPLB, r)
1179 opset(AVUPLHW, r)
1180 opset(AVUPLF, r)
1181 opset(AVUPLLB, r)
1182 opset(AVUPLLH, r)
1183 opset(AVUPLLF, r)
1184 opset(AVCLZB, r)
1185 opset(AVCLZH, r)
1186 opset(AVCLZF, r)
1187 opset(AVCLZG, r)
1188 opset(AVCTZB, r)
1189 opset(AVCTZH, r)
1190 opset(AVCTZF, r)
1191 opset(AVCTZG, r)
1192 opset(AVLDEB, r)
1193 opset(AWLDEB, r)
1194 opset(AVFLCDB, r)
1195 opset(AWFLCDB, r)
1196 opset(AVFLNDB, r)
1197 opset(AWFLNDB, r)
1198 opset(AVFLPDB, r)
1199 opset(AWFLPDB, r)
1200 opset(AVFSQDB, r)
1201 opset(AWFSQDB, r)
1202 opset(AVISTRB, r)
1203 opset(AVISTRH, r)
1204 opset(AVISTRF, r)
1205 opset(AVISTRBS, r)
1206 opset(AVISTRHS, r)
1207 opset(AVISTRFS, r)
1208 opset(AVLCB, r)
1209 opset(AVLCH, r)
1210 opset(AVLCF, r)
1211 opset(AVLCG, r)
1212 opset(AVLPB, r)
1213 opset(AVLPH, r)
1214 opset(AVLPF, r)
1215 opset(AVLPG, r)
1216 opset(AVPOPCT, r)
1217 opset(AVSEGB, r)
1218 opset(AVSEGH, r)
1219 opset(AVSEGF, r)
1220 case AVECG:
1221 opset(AVECB, r)
1222 opset(AVECH, r)
1223 opset(AVECF, r)
1224 opset(AVECLB, r)
1225 opset(AVECLH, r)
1226 opset(AVECLF, r)
1227 opset(AVECLG, r)
1228 opset(AWFCDB, r)
1229 opset(AWFKDB, r)
1230 case AVCEQG:
1231 opset(AVCEQB, r)
1232 opset(AVCEQH, r)
1233 opset(AVCEQF, r)
1234 opset(AVCEQBS, r)
1235 opset(AVCEQHS, r)
1236 opset(AVCEQFS, r)
1237 opset(AVCEQGS, r)
1238 opset(AVCHB, r)
1239 opset(AVCHH, r)
1240 opset(AVCHF, r)
1241 opset(AVCHG, r)
1242 opset(AVCHBS, r)
1243 opset(AVCHHS, r)
1244 opset(AVCHFS, r)
1245 opset(AVCHGS, r)
1246 opset(AVCHLB, r)
1247 opset(AVCHLH, r)
1248 opset(AVCHLF, r)
1249 opset(AVCHLG, r)
1250 opset(AVCHLBS, r)
1251 opset(AVCHLHS, r)
1252 opset(AVCHLFS, r)
1253 opset(AVCHLGS, r)
1254 case AVFAEF:
1255 opset(AVFAEB, r)
1256 opset(AVFAEH, r)
1257 opset(AVFAEBS, r)
1258 opset(AVFAEHS, r)
1259 opset(AVFAEFS, r)
1260 opset(AVFAEZB, r)
1261 opset(AVFAEZH, r)
1262 opset(AVFAEZF, r)
1263 opset(AVFAEZBS, r)
1264 opset(AVFAEZHS, r)
1265 opset(AVFAEZFS, r)
1266 opset(AVFEEB, r)
1267 opset(AVFEEH, r)
1268 opset(AVFEEF, r)
1269 opset(AVFEEBS, r)
1270 opset(AVFEEHS, r)
1271 opset(AVFEEFS, r)
1272 opset(AVFEEZB, r)
1273 opset(AVFEEZH, r)
1274 opset(AVFEEZF, r)
1275 opset(AVFEEZBS, r)
1276 opset(AVFEEZHS, r)
1277 opset(AVFEEZFS, r)
1278 opset(AVFENEB, r)
1279 opset(AVFENEH, r)
1280 opset(AVFENEF, r)
1281 opset(AVFENEBS, r)
1282 opset(AVFENEHS, r)
1283 opset(AVFENEFS, r)
1284 opset(AVFENEZB, r)
1285 opset(AVFENEZH, r)
1286 opset(AVFENEZF, r)
1287 opset(AVFENEZBS, r)
1288 opset(AVFENEZHS, r)
1289 opset(AVFENEZFS, r)
1290 case AVPKSG:
1291 opset(AVPKSH, r)
1292 opset(AVPKSF, r)
1293 opset(AVPKSHS, r)
1294 opset(AVPKSFS, r)
1295 opset(AVPKSGS, r)
1296 opset(AVPKLSH, r)
1297 opset(AVPKLSF, r)
1298 opset(AVPKLSG, r)
1299 opset(AVPKLSHS, r)
1300 opset(AVPKLSFS, r)
1301 opset(AVPKLSGS, r)
1302 case AVAQ:
1303 opset(AVAB, r)
1304 opset(AVAH, r)
1305 opset(AVAF, r)
1306 opset(AVAG, r)
1307 opset(AVACCB, r)
1308 opset(AVACCH, r)
1309 opset(AVACCF, r)
1310 opset(AVACCG, r)
1311 opset(AVACCQ, r)
1312 opset(AVN, r)
1313 opset(AVNC, r)
1314 opset(AVAVGB, r)
1315 opset(AVAVGH, r)
1316 opset(AVAVGF, r)
1317 opset(AVAVGG, r)
1318 opset(AVAVGLB, r)
1319 opset(AVAVGLH, r)
1320 opset(AVAVGLF, r)
1321 opset(AVAVGLG, r)
1322 opset(AVCKSM, r)
1323 opset(AVX, r)
1324 opset(AVFADB, r)
1325 opset(AWFADB, r)
1326 opset(AVFCEDB, r)
1327 opset(AVFCEDBS, r)
1328 opset(AWFCEDB, r)
1329 opset(AWFCEDBS, r)
1330 opset(AVFCHDB, r)
1331 opset(AVFCHDBS, r)
1332 opset(AWFCHDB, r)
1333 opset(AWFCHDBS, r)
1334 opset(AVFCHEDB, r)
1335 opset(AVFCHEDBS, r)
1336 opset(AWFCHEDB, r)
1337 opset(AWFCHEDBS, r)
1338 opset(AVFMDB, r)
1339 opset(AWFMDB, r)
1340 opset(AVGFMB, r)
1341 opset(AVGFMH, r)
1342 opset(AVGFMF, r)
1343 opset(AVGFMG, r)
1344 opset(AVMXB, r)
1345 opset(AVMXH, r)
1346 opset(AVMXF, r)
1347 opset(AVMXG, r)
1348 opset(AVMXLB, r)
1349 opset(AVMXLH, r)
1350 opset(AVMXLF, r)
1351 opset(AVMXLG, r)
1352 opset(AVMNB, r)
1353 opset(AVMNH, r)
1354 opset(AVMNF, r)
1355 opset(AVMNG, r)
1356 opset(AVMNLB, r)
1357 opset(AVMNLH, r)
1358 opset(AVMNLF, r)
1359 opset(AVMNLG, r)
1360 opset(AVMRHB, r)
1361 opset(AVMRHH, r)
1362 opset(AVMRHF, r)
1363 opset(AVMRHG, r)
1364 opset(AVMRLB, r)
1365 opset(AVMRLH, r)
1366 opset(AVMRLF, r)
1367 opset(AVMRLG, r)
1368 opset(AVMEB, r)
1369 opset(AVMEH, r)
1370 opset(AVMEF, r)
1371 opset(AVMLEB, r)
1372 opset(AVMLEH, r)
1373 opset(AVMLEF, r)
1374 opset(AVMOB, r)
1375 opset(AVMOH, r)
1376 opset(AVMOF, r)
1377 opset(AVMLOB, r)
1378 opset(AVMLOH, r)
1379 opset(AVMLOF, r)
1380 opset(AVMHB, r)
1381 opset(AVMHH, r)
1382 opset(AVMHF, r)
1383 opset(AVMLHB, r)
1384 opset(AVMLHH, r)
1385 opset(AVMLHF, r)
1386 opset(AVMLH, r)
1387 opset(AVMLHW, r)
1388 opset(AVMLF, r)
1389 opset(AVNO, r)
1390 opset(AVO, r)
1391 opset(AVPKH, r)
1392 opset(AVPKF, r)
1393 opset(AVPKG, r)
1394 opset(AVSUMGH, r)
1395 opset(AVSUMGF, r)
1396 opset(AVSUMQF, r)
1397 opset(AVSUMQG, r)
1398 opset(AVSUMB, r)
1399 opset(AVSUMH, r)
1400 case AVERLLVG:
1401 opset(AVERLLVB, r)
1402 opset(AVERLLVH, r)
1403 opset(AVERLLVF, r)
1404 opset(AVESLVB, r)
1405 opset(AVESLVH, r)
1406 opset(AVESLVF, r)
1407 opset(AVESLVG, r)
1408 opset(AVESRAVB, r)
1409 opset(AVESRAVH, r)
1410 opset(AVESRAVF, r)
1411 opset(AVESRAVG, r)
1412 opset(AVESRLVB, r)
1413 opset(AVESRLVH, r)
1414 opset(AVESRLVF, r)
1415 opset(AVESRLVG, r)
1416 opset(AVFDDB, r)
1417 opset(AWFDDB, r)
1418 opset(AVFSDB, r)
1419 opset(AWFSDB, r)
1420 opset(AVSL, r)
1421 opset(AVSLB, r)
1422 opset(AVSRA, r)
1423 opset(AVSRAB, r)
1424 opset(AVSRL, r)
1425 opset(AVSRLB, r)
1426 opset(AVSB, r)
1427 opset(AVSH, r)
1428 opset(AVSF, r)
1429 opset(AVSG, r)
1430 opset(AVSQ, r)
1431 opset(AVSCBIB, r)
1432 opset(AVSCBIH, r)
1433 opset(AVSCBIF, r)
1434 opset(AVSCBIG, r)
1435 opset(AVSCBIQ, r)
1436 case AVACQ:
1437 opset(AVACCCQ, r)
1438 opset(AVGFMAB, r)
1439 opset(AVGFMAH, r)
1440 opset(AVGFMAF, r)
1441 opset(AVGFMAG, r)
1442 opset(AVMALB, r)
1443 opset(AVMALHW, r)
1444 opset(AVMALF, r)
1445 opset(AVMAHB, r)
1446 opset(AVMAHH, r)
1447 opset(AVMAHF, r)
1448 opset(AVMALHB, r)
1449 opset(AVMALHH, r)
1450 opset(AVMALHF, r)
1451 opset(AVMAEB, r)
1452 opset(AVMAEH, r)
1453 opset(AVMAEF, r)
1454 opset(AVMALEB, r)
1455 opset(AVMALEH, r)
1456 opset(AVMALEF, r)
1457 opset(AVMAOB, r)
1458 opset(AVMAOH, r)
1459 opset(AVMAOF, r)
1460 opset(AVMALOB, r)
1461 opset(AVMALOH, r)
1462 opset(AVMALOF, r)
1463 opset(AVSTRC, r)
1464 opset(AVSTRCB, r)
1465 opset(AVSTRCH, r)
1466 opset(AVSTRCF, r)
1467 opset(AVSTRCBS, r)
1468 opset(AVSTRCHS, r)
1469 opset(AVSTRCFS, r)
1470 opset(AVSTRCZB, r)
1471 opset(AVSTRCZH, r)
1472 opset(AVSTRCZF, r)
1473 opset(AVSTRCZBS, r)
1474 opset(AVSTRCZHS, r)
1475 opset(AVSTRCZFS, r)
1476 opset(AVSBCBIQ, r)
1477 opset(AVSBIQ, r)
1478 opset(AVMSLG, r)
1479 opset(AVMSLEG, r)
1480 opset(AVMSLOG, r)
1481 opset(AVMSLEOG, r)
1482 case AVSEL:
1483 opset(AVFMADB, r)
1484 opset(AWFMADB, r)
1485 opset(AVFMSDB, r)
1486 opset(AWFMSDB, r)
1487 opset(AVPERM, r)
1488 case AVFMAXDB:
1489 opset(AVFMAXSB, r)
1490 opset(AVFMINDB, r)
1491 opset(AVFMINSB, r)
1492 case AWFMAXDB:
1493 opset(AWFMAXSB, r)
1494 opset(AWFMINDB, r)
1495 opset(AWFMINSB, r)
1496 case AKM:
1497 opset(AKMC, r)
1498 opset(AKLMD, r)
1499 opset(AKIMD, r)
1500 case AKMA:
1501 opset(AKMCTR, r)
1502 }
1503 }
1504 }
1505
1506 const (
1507 op_A uint32 = 0x5A00
1508 op_AD uint32 = 0x6A00
1509 op_ADB uint32 = 0xED1A
1510 op_ADBR uint32 = 0xB31A
1511 op_ADR uint32 = 0x2A00
1512 op_ADTR uint32 = 0xB3D2
1513 op_ADTRA uint32 = 0xB3D2
1514 op_AE uint32 = 0x7A00
1515 op_AEB uint32 = 0xED0A
1516 op_AEBR uint32 = 0xB30A
1517 op_AER uint32 = 0x3A00
1518 op_AFI uint32 = 0xC209
1519 op_AG uint32 = 0xE308
1520 op_AGF uint32 = 0xE318
1521 op_AGFI uint32 = 0xC208
1522 op_AGFR uint32 = 0xB918
1523 op_AGHI uint32 = 0xA70B
1524 op_AGHIK uint32 = 0xECD9
1525 op_AGR uint32 = 0xB908
1526 op_AGRK uint32 = 0xB9E8
1527 op_AGSI uint32 = 0xEB7A
1528 op_AH uint32 = 0x4A00
1529 op_AHHHR uint32 = 0xB9C8
1530 op_AHHLR uint32 = 0xB9D8
1531 op_AHI uint32 = 0xA70A
1532 op_AHIK uint32 = 0xECD8
1533 op_AHY uint32 = 0xE37A
1534 op_AIH uint32 = 0xCC08
1535 op_AL uint32 = 0x5E00
1536 op_ALC uint32 = 0xE398
1537 op_ALCG uint32 = 0xE388
1538 op_ALCGR uint32 = 0xB988
1539 op_ALCR uint32 = 0xB998
1540 op_ALFI uint32 = 0xC20B
1541 op_ALG uint32 = 0xE30A
1542 op_ALGF uint32 = 0xE31A
1543 op_ALGFI uint32 = 0xC20A
1544 op_ALGFR uint32 = 0xB91A
1545 op_ALGHSIK uint32 = 0xECDB
1546 op_ALGR uint32 = 0xB90A
1547 op_ALGRK uint32 = 0xB9EA
1548 op_ALGSI uint32 = 0xEB7E
1549 op_ALHHHR uint32 = 0xB9CA
1550 op_ALHHLR uint32 = 0xB9DA
1551 op_ALHSIK uint32 = 0xECDA
1552 op_ALR uint32 = 0x1E00
1553 op_ALRK uint32 = 0xB9FA
1554 op_ALSI uint32 = 0xEB6E
1555 op_ALSIH uint32 = 0xCC0A
1556 op_ALSIHN uint32 = 0xCC0B
1557 op_ALY uint32 = 0xE35E
1558 op_AP uint32 = 0xFA00
1559 op_AR uint32 = 0x1A00
1560 op_ARK uint32 = 0xB9F8
1561 op_ASI uint32 = 0xEB6A
1562 op_AU uint32 = 0x7E00
1563 op_AUR uint32 = 0x3E00
1564 op_AW uint32 = 0x6E00
1565 op_AWR uint32 = 0x2E00
1566 op_AXBR uint32 = 0xB34A
1567 op_AXR uint32 = 0x3600
1568 op_AXTR uint32 = 0xB3DA
1569 op_AXTRA uint32 = 0xB3DA
1570 op_AY uint32 = 0xE35A
1571 op_BAKR uint32 = 0xB240
1572 op_BAL uint32 = 0x4500
1573 op_BALR uint32 = 0x0500
1574 op_BAS uint32 = 0x4D00
1575 op_BASR uint32 = 0x0D00
1576 op_BASSM uint32 = 0x0C00
1577 op_BC uint32 = 0x4700
1578 op_BCR uint32 = 0x0700
1579 op_BCT uint32 = 0x4600
1580 op_BCTG uint32 = 0xE346
1581 op_BCTGR uint32 = 0xB946
1582 op_BCTR uint32 = 0x0600
1583 op_BPP uint32 = 0xC700
1584 op_BPRP uint32 = 0xC500
1585 op_BRAS uint32 = 0xA705
1586 op_BRASL uint32 = 0xC005
1587 op_BRC uint32 = 0xA704
1588 op_BRCL uint32 = 0xC004
1589 op_BRCT uint32 = 0xA706
1590 op_BRCTG uint32 = 0xA707
1591 op_BRCTH uint32 = 0xCC06
1592 op_BRXH uint32 = 0x8400
1593 op_BRXHG uint32 = 0xEC44
1594 op_BRXLE uint32 = 0x8500
1595 op_BRXLG uint32 = 0xEC45
1596 op_BSA uint32 = 0xB25A
1597 op_BSG uint32 = 0xB258
1598 op_BSM uint32 = 0x0B00
1599 op_BXH uint32 = 0x8600
1600 op_BXHG uint32 = 0xEB44
1601 op_BXLE uint32 = 0x8700
1602 op_BXLEG uint32 = 0xEB45
1603 op_C uint32 = 0x5900
1604 op_CD uint32 = 0x6900
1605 op_CDB uint32 = 0xED19
1606 op_CDBR uint32 = 0xB319
1607 op_CDFBR uint32 = 0xB395
1608 op_CDFBRA uint32 = 0xB395
1609 op_CDFR uint32 = 0xB3B5
1610 op_CDFTR uint32 = 0xB951
1611 op_CDGBR uint32 = 0xB3A5
1612 op_CDGBRA uint32 = 0xB3A5
1613 op_CDGR uint32 = 0xB3C5
1614 op_CDGTR uint32 = 0xB3F1
1615 op_CDGTRA uint32 = 0xB3F1
1616 op_CDLFBR uint32 = 0xB391
1617 op_CDLFTR uint32 = 0xB953
1618 op_CDLGBR uint32 = 0xB3A1
1619 op_CDLGTR uint32 = 0xB952
1620 op_CDR uint32 = 0x2900
1621 op_CDS uint32 = 0xBB00
1622 op_CDSG uint32 = 0xEB3E
1623 op_CDSTR uint32 = 0xB3F3
1624 op_CDSY uint32 = 0xEB31
1625 op_CDTR uint32 = 0xB3E4
1626 op_CDUTR uint32 = 0xB3F2
1627 op_CDZT uint32 = 0xEDAA
1628 op_CE uint32 = 0x7900
1629 op_CEB uint32 = 0xED09
1630 op_CEBR uint32 = 0xB309
1631 op_CEDTR uint32 = 0xB3F4
1632 op_CEFBR uint32 = 0xB394
1633 op_CEFBRA uint32 = 0xB394
1634 op_CEFR uint32 = 0xB3B4
1635 op_CEGBR uint32 = 0xB3A4
1636 op_CEGBRA uint32 = 0xB3A4
1637 op_CEGR uint32 = 0xB3C4
1638 op_CELFBR uint32 = 0xB390
1639 op_CELGBR uint32 = 0xB3A0
1640 op_CER uint32 = 0x3900
1641 op_CEXTR uint32 = 0xB3FC
1642 op_CFC uint32 = 0xB21A
1643 op_CFDBR uint32 = 0xB399
1644 op_CFDBRA uint32 = 0xB399
1645 op_CFDR uint32 = 0xB3B9
1646 op_CFDTR uint32 = 0xB941
1647 op_CFEBR uint32 = 0xB398
1648 op_CFEBRA uint32 = 0xB398
1649 op_CFER uint32 = 0xB3B8
1650 op_CFI uint32 = 0xC20D
1651 op_CFXBR uint32 = 0xB39A
1652 op_CFXBRA uint32 = 0xB39A
1653 op_CFXR uint32 = 0xB3BA
1654 op_CFXTR uint32 = 0xB949
1655 op_CG uint32 = 0xE320
1656 op_CGDBR uint32 = 0xB3A9
1657 op_CGDBRA uint32 = 0xB3A9
1658 op_CGDR uint32 = 0xB3C9
1659 op_CGDTR uint32 = 0xB3E1
1660 op_CGDTRA uint32 = 0xB3E1
1661 op_CGEBR uint32 = 0xB3A8
1662 op_CGEBRA uint32 = 0xB3A8
1663 op_CGER uint32 = 0xB3C8
1664 op_CGF uint32 = 0xE330
1665 op_CGFI uint32 = 0xC20C
1666 op_CGFR uint32 = 0xB930
1667 op_CGFRL uint32 = 0xC60C
1668 op_CGH uint32 = 0xE334
1669 op_CGHI uint32 = 0xA70F
1670 op_CGHRL uint32 = 0xC604
1671 op_CGHSI uint32 = 0xE558
1672 op_CGIB uint32 = 0xECFC
1673 op_CGIJ uint32 = 0xEC7C
1674 op_CGIT uint32 = 0xEC70
1675 op_CGR uint32 = 0xB920
1676 op_CGRB uint32 = 0xECE4
1677 op_CGRJ uint32 = 0xEC64
1678 op_CGRL uint32 = 0xC608
1679 op_CGRT uint32 = 0xB960
1680 op_CGXBR uint32 = 0xB3AA
1681 op_CGXBRA uint32 = 0xB3AA
1682 op_CGXR uint32 = 0xB3CA
1683 op_CGXTR uint32 = 0xB3E9
1684 op_CGXTRA uint32 = 0xB3E9
1685 op_CH uint32 = 0x4900
1686 op_CHF uint32 = 0xE3CD
1687 op_CHHR uint32 = 0xB9CD
1688 op_CHHSI uint32 = 0xE554
1689 op_CHI uint32 = 0xA70E
1690 op_CHLR uint32 = 0xB9DD
1691 op_CHRL uint32 = 0xC605
1692 op_CHSI uint32 = 0xE55C
1693 op_CHY uint32 = 0xE379
1694 op_CIB uint32 = 0xECFE
1695 op_CIH uint32 = 0xCC0D
1696 op_CIJ uint32 = 0xEC7E
1697 op_CIT uint32 = 0xEC72
1698 op_CKSM uint32 = 0xB241
1699 op_CL uint32 = 0x5500
1700 op_CLC uint32 = 0xD500
1701 op_CLCL uint32 = 0x0F00
1702 op_CLCLE uint32 = 0xA900
1703 op_CLCLU uint32 = 0xEB8F
1704 op_CLFDBR uint32 = 0xB39D
1705 op_CLFDTR uint32 = 0xB943
1706 op_CLFEBR uint32 = 0xB39C
1707 op_CLFHSI uint32 = 0xE55D
1708 op_CLFI uint32 = 0xC20F
1709 op_CLFIT uint32 = 0xEC73
1710 op_CLFXBR uint32 = 0xB39E
1711 op_CLFXTR uint32 = 0xB94B
1712 op_CLG uint32 = 0xE321
1713 op_CLGDBR uint32 = 0xB3AD
1714 op_CLGDTR uint32 = 0xB942
1715 op_CLGEBR uint32 = 0xB3AC
1716 op_CLGF uint32 = 0xE331
1717 op_CLGFI uint32 = 0xC20E
1718 op_CLGFR uint32 = 0xB931
1719 op_CLGFRL uint32 = 0xC60E
1720 op_CLGHRL uint32 = 0xC606
1721 op_CLGHSI uint32 = 0xE559
1722 op_CLGIB uint32 = 0xECFD
1723 op_CLGIJ uint32 = 0xEC7D
1724 op_CLGIT uint32 = 0xEC71
1725 op_CLGR uint32 = 0xB921
1726 op_CLGRB uint32 = 0xECE5
1727 op_CLGRJ uint32 = 0xEC65
1728 op_CLGRL uint32 = 0xC60A
1729 op_CLGRT uint32 = 0xB961
1730 op_CLGT uint32 = 0xEB2B
1731 op_CLGXBR uint32 = 0xB3AE
1732 op_CLGXTR uint32 = 0xB94A
1733 op_CLHF uint32 = 0xE3CF
1734 op_CLHHR uint32 = 0xB9CF
1735 op_CLHHSI uint32 = 0xE555
1736 op_CLHLR uint32 = 0xB9DF
1737 op_CLHRL uint32 = 0xC607
1738 op_CLI uint32 = 0x9500
1739 op_CLIB uint32 = 0xECFF
1740 op_CLIH uint32 = 0xCC0F
1741 op_CLIJ uint32 = 0xEC7F
1742 op_CLIY uint32 = 0xEB55
1743 op_CLM uint32 = 0xBD00
1744 op_CLMH uint32 = 0xEB20
1745 op_CLMY uint32 = 0xEB21
1746 op_CLR uint32 = 0x1500
1747 op_CLRB uint32 = 0xECF7
1748 op_CLRJ uint32 = 0xEC77
1749 op_CLRL uint32 = 0xC60F
1750 op_CLRT uint32 = 0xB973
1751 op_CLST uint32 = 0xB25D
1752 op_CLT uint32 = 0xEB23
1753 op_CLY uint32 = 0xE355
1754 op_CMPSC uint32 = 0xB263
1755 op_CP uint32 = 0xF900
1756 op_CPSDR uint32 = 0xB372
1757 op_CPYA uint32 = 0xB24D
1758 op_CR uint32 = 0x1900
1759 op_CRB uint32 = 0xECF6
1760 op_CRDTE uint32 = 0xB98F
1761 op_CRJ uint32 = 0xEC76
1762 op_CRL uint32 = 0xC60D
1763 op_CRT uint32 = 0xB972
1764 op_CS uint32 = 0xBA00
1765 op_CSCH uint32 = 0xB230
1766 op_CSDTR uint32 = 0xB3E3
1767 op_CSG uint32 = 0xEB30
1768 op_CSP uint32 = 0xB250
1769 op_CSPG uint32 = 0xB98A
1770 op_CSST uint32 = 0xC802
1771 op_CSXTR uint32 = 0xB3EB
1772 op_CSY uint32 = 0xEB14
1773 op_CU12 uint32 = 0xB2A7
1774 op_CU14 uint32 = 0xB9B0
1775 op_CU21 uint32 = 0xB2A6
1776 op_CU24 uint32 = 0xB9B1
1777 op_CU41 uint32 = 0xB9B2
1778 op_CU42 uint32 = 0xB9B3
1779 op_CUDTR uint32 = 0xB3E2
1780 op_CUSE uint32 = 0xB257
1781 op_CUTFU uint32 = 0xB2A7
1782 op_CUUTF uint32 = 0xB2A6
1783 op_CUXTR uint32 = 0xB3EA
1784 op_CVB uint32 = 0x4F00
1785 op_CVBG uint32 = 0xE30E
1786 op_CVBY uint32 = 0xE306
1787 op_CVD uint32 = 0x4E00
1788 op_CVDG uint32 = 0xE32E
1789 op_CVDY uint32 = 0xE326
1790 op_CXBR uint32 = 0xB349
1791 op_CXFBR uint32 = 0xB396
1792 op_CXFBRA uint32 = 0xB396
1793 op_CXFR uint32 = 0xB3B6
1794 op_CXFTR uint32 = 0xB959
1795 op_CXGBR uint32 = 0xB3A6
1796 op_CXGBRA uint32 = 0xB3A6
1797 op_CXGR uint32 = 0xB3C6
1798 op_CXGTR uint32 = 0xB3F9
1799 op_CXGTRA uint32 = 0xB3F9
1800 op_CXLFBR uint32 = 0xB392
1801 op_CXLFTR uint32 = 0xB95B
1802 op_CXLGBR uint32 = 0xB3A2
1803 op_CXLGTR uint32 = 0xB95A
1804 op_CXR uint32 = 0xB369
1805 op_CXSTR uint32 = 0xB3FB
1806 op_CXTR uint32 = 0xB3EC
1807 op_CXUTR uint32 = 0xB3FA
1808 op_CXZT uint32 = 0xEDAB
1809 op_CY uint32 = 0xE359
1810 op_CZDT uint32 = 0xEDA8
1811 op_CZXT uint32 = 0xEDA9
1812 op_D uint32 = 0x5D00
1813 op_DD uint32 = 0x6D00
1814 op_DDB uint32 = 0xED1D
1815 op_DDBR uint32 = 0xB31D
1816 op_DDR uint32 = 0x2D00
1817 op_DDTR uint32 = 0xB3D1
1818 op_DDTRA uint32 = 0xB3D1
1819 op_DE uint32 = 0x7D00
1820 op_DEB uint32 = 0xED0D
1821 op_DEBR uint32 = 0xB30D
1822 op_DER uint32 = 0x3D00
1823 op_DIDBR uint32 = 0xB35B
1824 op_DIEBR uint32 = 0xB353
1825 op_DL uint32 = 0xE397
1826 op_DLG uint32 = 0xE387
1827 op_DLGR uint32 = 0xB987
1828 op_DLR uint32 = 0xB997
1829 op_DP uint32 = 0xFD00
1830 op_DR uint32 = 0x1D00
1831 op_DSG uint32 = 0xE30D
1832 op_DSGF uint32 = 0xE31D
1833 op_DSGFR uint32 = 0xB91D
1834 op_DSGR uint32 = 0xB90D
1835 op_DXBR uint32 = 0xB34D
1836 op_DXR uint32 = 0xB22D
1837 op_DXTR uint32 = 0xB3D9
1838 op_DXTRA uint32 = 0xB3D9
1839 op_EAR uint32 = 0xB24F
1840 op_ECAG uint32 = 0xEB4C
1841 op_ECTG uint32 = 0xC801
1842 op_ED uint32 = 0xDE00
1843 op_EDMK uint32 = 0xDF00
1844 op_EEDTR uint32 = 0xB3E5
1845 op_EEXTR uint32 = 0xB3ED
1846 op_EFPC uint32 = 0xB38C
1847 op_EPAIR uint32 = 0xB99A
1848 op_EPAR uint32 = 0xB226
1849 op_EPSW uint32 = 0xB98D
1850 op_EREG uint32 = 0xB249
1851 op_EREGG uint32 = 0xB90E
1852 op_ESAIR uint32 = 0xB99B
1853 op_ESAR uint32 = 0xB227
1854 op_ESDTR uint32 = 0xB3E7
1855 op_ESEA uint32 = 0xB99D
1856 op_ESTA uint32 = 0xB24A
1857 op_ESXTR uint32 = 0xB3EF
1858 op_ETND uint32 = 0xB2EC
1859 op_EX uint32 = 0x4400
1860 op_EXRL uint32 = 0xC600
1861 op_FIDBR uint32 = 0xB35F
1862 op_FIDBRA uint32 = 0xB35F
1863 op_FIDR uint32 = 0xB37F
1864 op_FIDTR uint32 = 0xB3D7
1865 op_FIEBR uint32 = 0xB357
1866 op_FIEBRA uint32 = 0xB357
1867 op_FIER uint32 = 0xB377
1868 op_FIXBR uint32 = 0xB347
1869 op_FIXBRA uint32 = 0xB347
1870 op_FIXR uint32 = 0xB367
1871 op_FIXTR uint32 = 0xB3DF
1872 op_FLOGR uint32 = 0xB983
1873 op_HDR uint32 = 0x2400
1874 op_HER uint32 = 0x3400
1875 op_HSCH uint32 = 0xB231
1876 op_IAC uint32 = 0xB224
1877 op_IC uint32 = 0x4300
1878 op_ICM uint32 = 0xBF00
1879 op_ICMH uint32 = 0xEB80
1880 op_ICMY uint32 = 0xEB81
1881 op_ICY uint32 = 0xE373
1882 op_IDTE uint32 = 0xB98E
1883 op_IEDTR uint32 = 0xB3F6
1884 op_IEXTR uint32 = 0xB3FE
1885 op_IIHF uint32 = 0xC008
1886 op_IIHH uint32 = 0xA500
1887 op_IIHL uint32 = 0xA501
1888 op_IILF uint32 = 0xC009
1889 op_IILH uint32 = 0xA502
1890 op_IILL uint32 = 0xA503
1891 op_IPK uint32 = 0xB20B
1892 op_IPM uint32 = 0xB222
1893 op_IPTE uint32 = 0xB221
1894 op_ISKE uint32 = 0xB229
1895 op_IVSK uint32 = 0xB223
1896 op_KDB uint32 = 0xED18
1897 op_KDBR uint32 = 0xB318
1898 op_KDTR uint32 = 0xB3E0
1899 op_KEB uint32 = 0xED08
1900 op_KEBR uint32 = 0xB308
1901 op_KIMD uint32 = 0xB93E
1902 op_KLMD uint32 = 0xB93F
1903 op_KM uint32 = 0xB92E
1904 op_KMAC uint32 = 0xB91E
1905 op_KMC uint32 = 0xB92F
1906 op_KMA uint32 = 0xB929
1907 op_KMCTR uint32 = 0xB92D
1908 op_KMF uint32 = 0xB92A
1909 op_KMO uint32 = 0xB92B
1910 op_KXBR uint32 = 0xB348
1911 op_KXTR uint32 = 0xB3E8
1912 op_L uint32 = 0x5800
1913 op_LA uint32 = 0x4100
1914 op_LAA uint32 = 0xEBF8
1915 op_LAAG uint32 = 0xEBE8
1916 op_LAAL uint32 = 0xEBFA
1917 op_LAALG uint32 = 0xEBEA
1918 op_LAE uint32 = 0x5100
1919 op_LAEY uint32 = 0xE375
1920 op_LAM uint32 = 0x9A00
1921 op_LAMY uint32 = 0xEB9A
1922 op_LAN uint32 = 0xEBF4
1923 op_LANG uint32 = 0xEBE4
1924 op_LAO uint32 = 0xEBF6
1925 op_LAOG uint32 = 0xEBE6
1926 op_LARL uint32 = 0xC000
1927 op_LASP uint32 = 0xE500
1928 op_LAT uint32 = 0xE39F
1929 op_LAX uint32 = 0xEBF7
1930 op_LAXG uint32 = 0xEBE7
1931 op_LAY uint32 = 0xE371
1932 op_LB uint32 = 0xE376
1933 op_LBH uint32 = 0xE3C0
1934 op_LBR uint32 = 0xB926
1935 op_LCDBR uint32 = 0xB313
1936 op_LCDFR uint32 = 0xB373
1937 op_LCDR uint32 = 0x2300
1938 op_LCEBR uint32 = 0xB303
1939 op_LCER uint32 = 0x3300
1940 op_LCGFR uint32 = 0xB913
1941 op_LCGR uint32 = 0xB903
1942 op_LCR uint32 = 0x1300
1943 op_LCTL uint32 = 0xB700
1944 op_LCTLG uint32 = 0xEB2F
1945 op_LCXBR uint32 = 0xB343
1946 op_LCXR uint32 = 0xB363
1947 op_LD uint32 = 0x6800
1948 op_LDE uint32 = 0xED24
1949 op_LDEB uint32 = 0xED04
1950 op_LDEBR uint32 = 0xB304
1951 op_LDER uint32 = 0xB324
1952 op_LDETR uint32 = 0xB3D4
1953 op_LDGR uint32 = 0xB3C1
1954 op_LDR uint32 = 0x2800
1955 op_LDXBR uint32 = 0xB345
1956 op_LDXBRA uint32 = 0xB345
1957 op_LDXR uint32 = 0x2500
1958 op_LDXTR uint32 = 0xB3DD
1959 op_LDY uint32 = 0xED65
1960 op_LE uint32 = 0x7800
1961 op_LEDBR uint32 = 0xB344
1962 op_LEDBRA uint32 = 0xB344
1963 op_LEDR uint32 = 0x3500
1964 op_LEDTR uint32 = 0xB3D5
1965 op_LER uint32 = 0x3800
1966 op_LEXBR uint32 = 0xB346
1967 op_LEXBRA uint32 = 0xB346
1968 op_LEXR uint32 = 0xB366
1969 op_LEY uint32 = 0xED64
1970 op_LFAS uint32 = 0xB2BD
1971 op_LFH uint32 = 0xE3CA
1972 op_LFHAT uint32 = 0xE3C8
1973 op_LFPC uint32 = 0xB29D
1974 op_LG uint32 = 0xE304
1975 op_LGAT uint32 = 0xE385
1976 op_LGB uint32 = 0xE377
1977 op_LGBR uint32 = 0xB906
1978 op_LGDR uint32 = 0xB3CD
1979 op_LGF uint32 = 0xE314
1980 op_LGFI uint32 = 0xC001
1981 op_LGFR uint32 = 0xB914
1982 op_LGFRL uint32 = 0xC40C
1983 op_LGH uint32 = 0xE315
1984 op_LGHI uint32 = 0xA709
1985 op_LGHR uint32 = 0xB907
1986 op_LGHRL uint32 = 0xC404
1987 op_LGR uint32 = 0xB904
1988 op_LGRL uint32 = 0xC408
1989 op_LH uint32 = 0x4800
1990 op_LHH uint32 = 0xE3C4
1991 op_LHI uint32 = 0xA708
1992 op_LHR uint32 = 0xB927
1993 op_LHRL uint32 = 0xC405
1994 op_LHY uint32 = 0xE378
1995 op_LLC uint32 = 0xE394
1996 op_LLCH uint32 = 0xE3C2
1997 op_LLCR uint32 = 0xB994
1998 op_LLGC uint32 = 0xE390
1999 op_LLGCR uint32 = 0xB984
2000 op_LLGF uint32 = 0xE316
2001 op_LLGFAT uint32 = 0xE39D
2002 op_LLGFR uint32 = 0xB916
2003 op_LLGFRL uint32 = 0xC40E
2004 op_LLGH uint32 = 0xE391
2005 op_LLGHR uint32 = 0xB985
2006 op_LLGHRL uint32 = 0xC406
2007 op_LLGT uint32 = 0xE317
2008 op_LLGTAT uint32 = 0xE39C
2009 op_LLGTR uint32 = 0xB917
2010 op_LLH uint32 = 0xE395
2011 op_LLHH uint32 = 0xE3C6
2012 op_LLHR uint32 = 0xB995
2013 op_LLHRL uint32 = 0xC402
2014 op_LLIHF uint32 = 0xC00E
2015 op_LLIHH uint32 = 0xA50C
2016 op_LLIHL uint32 = 0xA50D
2017 op_LLILF uint32 = 0xC00F
2018 op_LLILH uint32 = 0xA50E
2019 op_LLILL uint32 = 0xA50F
2020 op_LM uint32 = 0x9800
2021 op_LMD uint32 = 0xEF00
2022 op_LMG uint32 = 0xEB04
2023 op_LMH uint32 = 0xEB96
2024 op_LMY uint32 = 0xEB98
2025 op_LNDBR uint32 = 0xB311
2026 op_LNDFR uint32 = 0xB371
2027 op_LNDR uint32 = 0x2100
2028 op_LNEBR uint32 = 0xB301
2029 op_LNER uint32 = 0x3100
2030 op_LNGFR uint32 = 0xB911
2031 op_LNGR uint32 = 0xB901
2032 op_LNR uint32 = 0x1100
2033 op_LNXBR uint32 = 0xB341
2034 op_LNXR uint32 = 0xB361
2035 op_LOC uint32 = 0xEBF2
2036 op_LOCG uint32 = 0xEBE2
2037 op_LOCGR uint32 = 0xB9E2
2038 op_LOCR uint32 = 0xB9F2
2039 op_LPD uint32 = 0xC804
2040 op_LPDBR uint32 = 0xB310
2041 op_LPDFR uint32 = 0xB370
2042 op_LPDG uint32 = 0xC805
2043 op_LPDR uint32 = 0x2000
2044 op_LPEBR uint32 = 0xB300
2045 op_LPER uint32 = 0x3000
2046 op_LPGFR uint32 = 0xB910
2047 op_LPGR uint32 = 0xB900
2048 op_LPQ uint32 = 0xE38F
2049 op_LPR uint32 = 0x1000
2050 op_LPSW uint32 = 0x8200
2051 op_LPSWE uint32 = 0xB2B2
2052 op_LPTEA uint32 = 0xB9AA
2053 op_LPXBR uint32 = 0xB340
2054 op_LPXR uint32 = 0xB360
2055 op_LR uint32 = 0x1800
2056 op_LRA uint32 = 0xB100
2057 op_LRAG uint32 = 0xE303
2058 op_LRAY uint32 = 0xE313
2059 op_LRDR uint32 = 0x2500
2060 op_LRER uint32 = 0x3500
2061 op_LRL uint32 = 0xC40D
2062 op_LRV uint32 = 0xE31E
2063 op_LRVG uint32 = 0xE30F
2064 op_LRVGR uint32 = 0xB90F
2065 op_LRVH uint32 = 0xE31F
2066 op_LRVR uint32 = 0xB91F
2067 op_LT uint32 = 0xE312
2068 op_LTDBR uint32 = 0xB312
2069 op_LTDR uint32 = 0x2200
2070 op_LTDTR uint32 = 0xB3D6
2071 op_LTEBR uint32 = 0xB302
2072 op_LTER uint32 = 0x3200
2073 op_LTG uint32 = 0xE302
2074 op_LTGF uint32 = 0xE332
2075 op_LTGFR uint32 = 0xB912
2076 op_LTGR uint32 = 0xB902
2077 op_LTR uint32 = 0x1200
2078 op_LTXBR uint32 = 0xB342
2079 op_LTXR uint32 = 0xB362
2080 op_LTXTR uint32 = 0xB3DE
2081 op_LURA uint32 = 0xB24B
2082 op_LURAG uint32 = 0xB905
2083 op_LXD uint32 = 0xED25
2084 op_LXDB uint32 = 0xED05
2085 op_LXDBR uint32 = 0xB305
2086 op_LXDR uint32 = 0xB325
2087 op_LXDTR uint32 = 0xB3DC
2088 op_LXE uint32 = 0xED26
2089 op_LXEB uint32 = 0xED06
2090 op_LXEBR uint32 = 0xB306
2091 op_LXER uint32 = 0xB326
2092 op_LXR uint32 = 0xB365
2093 op_LY uint32 = 0xE358
2094 op_LZDR uint32 = 0xB375
2095 op_LZER uint32 = 0xB374
2096 op_LZXR uint32 = 0xB376
2097 op_M uint32 = 0x5C00
2098 op_MAD uint32 = 0xED3E
2099 op_MADB uint32 = 0xED1E
2100 op_MADBR uint32 = 0xB31E
2101 op_MADR uint32 = 0xB33E
2102 op_MAE uint32 = 0xED2E
2103 op_MAEB uint32 = 0xED0E
2104 op_MAEBR uint32 = 0xB30E
2105 op_MAER uint32 = 0xB32E
2106 op_MAY uint32 = 0xED3A
2107 op_MAYH uint32 = 0xED3C
2108 op_MAYHR uint32 = 0xB33C
2109 op_MAYL uint32 = 0xED38
2110 op_MAYLR uint32 = 0xB338
2111 op_MAYR uint32 = 0xB33A
2112 op_MC uint32 = 0xAF00
2113 op_MD uint32 = 0x6C00
2114 op_MDB uint32 = 0xED1C
2115 op_MDBR uint32 = 0xB31C
2116 op_MDE uint32 = 0x7C00
2117 op_MDEB uint32 = 0xED0C
2118 op_MDEBR uint32 = 0xB30C
2119 op_MDER uint32 = 0x3C00
2120 op_MDR uint32 = 0x2C00
2121 op_MDTR uint32 = 0xB3D0
2122 op_MDTRA uint32 = 0xB3D0
2123 op_ME uint32 = 0x7C00
2124 op_MEE uint32 = 0xED37
2125 op_MEEB uint32 = 0xED17
2126 op_MEEBR uint32 = 0xB317
2127 op_MEER uint32 = 0xB337
2128 op_MER uint32 = 0x3C00
2129 op_MFY uint32 = 0xE35C
2130 op_MGHI uint32 = 0xA70D
2131 op_MH uint32 = 0x4C00
2132 op_MHI uint32 = 0xA70C
2133 op_MHY uint32 = 0xE37C
2134 op_ML uint32 = 0xE396
2135 op_MLG uint32 = 0xE386
2136 op_MLGR uint32 = 0xB986
2137 op_MLR uint32 = 0xB996
2138 op_MP uint32 = 0xFC00
2139 op_MR uint32 = 0x1C00
2140 op_MS uint32 = 0x7100
2141 op_MSCH uint32 = 0xB232
2142 op_MSD uint32 = 0xED3F
2143 op_MSDB uint32 = 0xED1F
2144 op_MSDBR uint32 = 0xB31F
2145 op_MSDR uint32 = 0xB33F
2146 op_MSE uint32 = 0xED2F
2147 op_MSEB uint32 = 0xED0F
2148 op_MSEBR uint32 = 0xB30F
2149 op_MSER uint32 = 0xB32F
2150 op_MSFI uint32 = 0xC201
2151 op_MSG uint32 = 0xE30C
2152 op_MSGF uint32 = 0xE31C
2153 op_MSGFI uint32 = 0xC200
2154 op_MSGFR uint32 = 0xB91C
2155 op_MSGR uint32 = 0xB90C
2156 op_MSR uint32 = 0xB252
2157 op_MSTA uint32 = 0xB247
2158 op_MSY uint32 = 0xE351
2159 op_MVC uint32 = 0xD200
2160 op_MVCDK uint32 = 0xE50F
2161 op_MVCIN uint32 = 0xE800
2162 op_MVCK uint32 = 0xD900
2163 op_MVCL uint32 = 0x0E00
2164 op_MVCLE uint32 = 0xA800
2165 op_MVCLU uint32 = 0xEB8E
2166 op_MVCOS uint32 = 0xC800
2167 op_MVCP uint32 = 0xDA00
2168 op_MVCS uint32 = 0xDB00
2169 op_MVCSK uint32 = 0xE50E
2170 op_MVGHI uint32 = 0xE548
2171 op_MVHHI uint32 = 0xE544
2172 op_MVHI uint32 = 0xE54C
2173 op_MVI uint32 = 0x9200
2174 op_MVIY uint32 = 0xEB52
2175 op_MVN uint32 = 0xD100
2176 op_MVO uint32 = 0xF100
2177 op_MVPG uint32 = 0xB254
2178 op_MVST uint32 = 0xB255
2179 op_MVZ uint32 = 0xD300
2180 op_MXBR uint32 = 0xB34C
2181 op_MXD uint32 = 0x6700
2182 op_MXDB uint32 = 0xED07
2183 op_MXDBR uint32 = 0xB307
2184 op_MXDR uint32 = 0x2700
2185 op_MXR uint32 = 0x2600
2186 op_MXTR uint32 = 0xB3D8
2187 op_MXTRA uint32 = 0xB3D8
2188 op_MY uint32 = 0xED3B
2189 op_MYH uint32 = 0xED3D
2190 op_MYHR uint32 = 0xB33D
2191 op_MYL uint32 = 0xED39
2192 op_MYLR uint32 = 0xB339
2193 op_MYR uint32 = 0xB33B
2194 op_N uint32 = 0x5400
2195 op_NC uint32 = 0xD400
2196 op_NG uint32 = 0xE380
2197 op_NGR uint32 = 0xB980
2198 op_NGRK uint32 = 0xB9E4
2199 op_NI uint32 = 0x9400
2200 op_NIAI uint32 = 0xB2FA
2201 op_NIHF uint32 = 0xC00A
2202 op_NIHH uint32 = 0xA504
2203 op_NIHL uint32 = 0xA505
2204 op_NILF uint32 = 0xC00B
2205 op_NILH uint32 = 0xA506
2206 op_NILL uint32 = 0xA507
2207 op_NIY uint32 = 0xEB54
2208 op_NR uint32 = 0x1400
2209 op_NRK uint32 = 0xB9F4
2210 op_NTSTG uint32 = 0xE325
2211 op_NY uint32 = 0xE354
2212 op_O uint32 = 0x5600
2213 op_OC uint32 = 0xD600
2214 op_OG uint32 = 0xE381
2215 op_OGR uint32 = 0xB981
2216 op_OGRK uint32 = 0xB9E6
2217 op_OI uint32 = 0x9600
2218 op_OIHF uint32 = 0xC00C
2219 op_OIHH uint32 = 0xA508
2220 op_OIHL uint32 = 0xA509
2221 op_OILF uint32 = 0xC00D
2222 op_OILH uint32 = 0xA50A
2223 op_OILL uint32 = 0xA50B
2224 op_OIY uint32 = 0xEB56
2225 op_OR uint32 = 0x1600
2226 op_ORK uint32 = 0xB9F6
2227 op_OY uint32 = 0xE356
2228 op_PACK uint32 = 0xF200
2229 op_PALB uint32 = 0xB248
2230 op_PC uint32 = 0xB218
2231 op_PCC uint32 = 0xB92C
2232 op_PCKMO uint32 = 0xB928
2233 op_PFD uint32 = 0xE336
2234 op_PFDRL uint32 = 0xC602
2235 op_PFMF uint32 = 0xB9AF
2236 op_PFPO uint32 = 0x010A
2237 op_PGIN uint32 = 0xB22E
2238 op_PGOUT uint32 = 0xB22F
2239 op_PKA uint32 = 0xE900
2240 op_PKU uint32 = 0xE100
2241 op_PLO uint32 = 0xEE00
2242 op_POPCNT uint32 = 0xB9E1
2243 op_PPA uint32 = 0xB2E8
2244 op_PR uint32 = 0x0101
2245 op_PT uint32 = 0xB228
2246 op_PTF uint32 = 0xB9A2
2247 op_PTFF uint32 = 0x0104
2248 op_PTI uint32 = 0xB99E
2249 op_PTLB uint32 = 0xB20D
2250 op_QADTR uint32 = 0xB3F5
2251 op_QAXTR uint32 = 0xB3FD
2252 op_RCHP uint32 = 0xB23B
2253 op_RISBG uint32 = 0xEC55
2254 op_RISBGN uint32 = 0xEC59
2255 op_RISBHG uint32 = 0xEC5D
2256 op_RISBLG uint32 = 0xEC51
2257 op_RLL uint32 = 0xEB1D
2258 op_RLLG uint32 = 0xEB1C
2259 op_RNSBG uint32 = 0xEC54
2260 op_ROSBG uint32 = 0xEC56
2261 op_RP uint32 = 0xB277
2262 op_RRBE uint32 = 0xB22A
2263 op_RRBM uint32 = 0xB9AE
2264 op_RRDTR uint32 = 0xB3F7
2265 op_RRXTR uint32 = 0xB3FF
2266 op_RSCH uint32 = 0xB238
2267 op_RXSBG uint32 = 0xEC57
2268 op_S uint32 = 0x5B00
2269 op_SAC uint32 = 0xB219
2270 op_SACF uint32 = 0xB279
2271 op_SAL uint32 = 0xB237
2272 op_SAM24 uint32 = 0x010C
2273 op_SAM31 uint32 = 0x010D
2274 op_SAM64 uint32 = 0x010E
2275 op_SAR uint32 = 0xB24E
2276 op_SCHM uint32 = 0xB23C
2277 op_SCK uint32 = 0xB204
2278 op_SCKC uint32 = 0xB206
2279 op_SCKPF uint32 = 0x0107
2280 op_SD uint32 = 0x6B00
2281 op_SDB uint32 = 0xED1B
2282 op_SDBR uint32 = 0xB31B
2283 op_SDR uint32 = 0x2B00
2284 op_SDTR uint32 = 0xB3D3
2285 op_SDTRA uint32 = 0xB3D3
2286 op_SE uint32 = 0x7B00
2287 op_SEB uint32 = 0xED0B
2288 op_SEBR uint32 = 0xB30B
2289 op_SER uint32 = 0x3B00
2290 op_SFASR uint32 = 0xB385
2291 op_SFPC uint32 = 0xB384
2292 op_SG uint32 = 0xE309
2293 op_SGF uint32 = 0xE319
2294 op_SGFR uint32 = 0xB919
2295 op_SGR uint32 = 0xB909
2296 op_SGRK uint32 = 0xB9E9
2297 op_SH uint32 = 0x4B00
2298 op_SHHHR uint32 = 0xB9C9
2299 op_SHHLR uint32 = 0xB9D9
2300 op_SHY uint32 = 0xE37B
2301 op_SIGP uint32 = 0xAE00
2302 op_SL uint32 = 0x5F00
2303 op_SLA uint32 = 0x8B00
2304 op_SLAG uint32 = 0xEB0B
2305 op_SLAK uint32 = 0xEBDD
2306 op_SLB uint32 = 0xE399
2307 op_SLBG uint32 = 0xE389
2308 op_SLBGR uint32 = 0xB989
2309 op_SLBR uint32 = 0xB999
2310 op_SLDA uint32 = 0x8F00
2311 op_SLDL uint32 = 0x8D00
2312 op_SLDT uint32 = 0xED40
2313 op_SLFI uint32 = 0xC205
2314 op_SLG uint32 = 0xE30B
2315 op_SLGF uint32 = 0xE31B
2316 op_SLGFI uint32 = 0xC204
2317 op_SLGFR uint32 = 0xB91B
2318 op_SLGR uint32 = 0xB90B
2319 op_SLGRK uint32 = 0xB9EB
2320 op_SLHHHR uint32 = 0xB9CB
2321 op_SLHHLR uint32 = 0xB9DB
2322 op_SLL uint32 = 0x8900
2323 op_SLLG uint32 = 0xEB0D
2324 op_SLLK uint32 = 0xEBDF
2325 op_SLR uint32 = 0x1F00
2326 op_SLRK uint32 = 0xB9FB
2327 op_SLXT uint32 = 0xED48
2328 op_SLY uint32 = 0xE35F
2329 op_SP uint32 = 0xFB00
2330 op_SPKA uint32 = 0xB20A
2331 op_SPM uint32 = 0x0400
2332 op_SPT uint32 = 0xB208
2333 op_SPX uint32 = 0xB210
2334 op_SQD uint32 = 0xED35
2335 op_SQDB uint32 = 0xED15
2336 op_SQDBR uint32 = 0xB315
2337 op_SQDR uint32 = 0xB244
2338 op_SQE uint32 = 0xED34
2339 op_SQEB uint32 = 0xED14
2340 op_SQEBR uint32 = 0xB314
2341 op_SQER uint32 = 0xB245
2342 op_SQXBR uint32 = 0xB316
2343 op_SQXR uint32 = 0xB336
2344 op_SR uint32 = 0x1B00
2345 op_SRA uint32 = 0x8A00
2346 op_SRAG uint32 = 0xEB0A
2347 op_SRAK uint32 = 0xEBDC
2348 op_SRDA uint32 = 0x8E00
2349 op_SRDL uint32 = 0x8C00
2350 op_SRDT uint32 = 0xED41
2351 op_SRK uint32 = 0xB9F9
2352 op_SRL uint32 = 0x8800
2353 op_SRLG uint32 = 0xEB0C
2354 op_SRLK uint32 = 0xEBDE
2355 op_SRNM uint32 = 0xB299
2356 op_SRNMB uint32 = 0xB2B8
2357 op_SRNMT uint32 = 0xB2B9
2358 op_SRP uint32 = 0xF000
2359 op_SRST uint32 = 0xB25E
2360 op_SRSTU uint32 = 0xB9BE
2361 op_SRXT uint32 = 0xED49
2362 op_SSAIR uint32 = 0xB99F
2363 op_SSAR uint32 = 0xB225
2364 op_SSCH uint32 = 0xB233
2365 op_SSKE uint32 = 0xB22B
2366 op_SSM uint32 = 0x8000
2367 op_ST uint32 = 0x5000
2368 op_STAM uint32 = 0x9B00
2369 op_STAMY uint32 = 0xEB9B
2370 op_STAP uint32 = 0xB212
2371 op_STC uint32 = 0x4200
2372 op_STCH uint32 = 0xE3C3
2373 op_STCK uint32 = 0xB205
2374 op_STCKC uint32 = 0xB207
2375 op_STCKE uint32 = 0xB278
2376 op_STCKF uint32 = 0xB27C
2377 op_STCM uint32 = 0xBE00
2378 op_STCMH uint32 = 0xEB2C
2379 op_STCMY uint32 = 0xEB2D
2380 op_STCPS uint32 = 0xB23A
2381 op_STCRW uint32 = 0xB239
2382 op_STCTG uint32 = 0xEB25
2383 op_STCTL uint32 = 0xB600
2384 op_STCY uint32 = 0xE372
2385 op_STD uint32 = 0x6000
2386 op_STDY uint32 = 0xED67
2387 op_STE uint32 = 0x7000
2388 op_STEY uint32 = 0xED66
2389 op_STFH uint32 = 0xE3CB
2390 op_STFL uint32 = 0xB2B1
2391 op_STFLE uint32 = 0xB2B0
2392 op_STFPC uint32 = 0xB29C
2393 op_STG uint32 = 0xE324
2394 op_STGRL uint32 = 0xC40B
2395 op_STH uint32 = 0x4000
2396 op_STHH uint32 = 0xE3C7
2397 op_STHRL uint32 = 0xC407
2398 op_STHY uint32 = 0xE370
2399 op_STIDP uint32 = 0xB202
2400 op_STM uint32 = 0x9000
2401 op_STMG uint32 = 0xEB24
2402 op_STMH uint32 = 0xEB26
2403 op_STMY uint32 = 0xEB90
2404 op_STNSM uint32 = 0xAC00
2405 op_STOC uint32 = 0xEBF3
2406 op_STOCG uint32 = 0xEBE3
2407 op_STOSM uint32 = 0xAD00
2408 op_STPQ uint32 = 0xE38E
2409 op_STPT uint32 = 0xB209
2410 op_STPX uint32 = 0xB211
2411 op_STRAG uint32 = 0xE502
2412 op_STRL uint32 = 0xC40F
2413 op_STRV uint32 = 0xE33E
2414 op_STRVG uint32 = 0xE32F
2415 op_STRVH uint32 = 0xE33F
2416 op_STSCH uint32 = 0xB234
2417 op_STSI uint32 = 0xB27D
2418 op_STURA uint32 = 0xB246
2419 op_STURG uint32 = 0xB925
2420 op_STY uint32 = 0xE350
2421 op_SU uint32 = 0x7F00
2422 op_SUR uint32 = 0x3F00
2423 op_SVC uint32 = 0x0A00
2424 op_SW uint32 = 0x6F00
2425 op_SWR uint32 = 0x2F00
2426 op_SXBR uint32 = 0xB34B
2427 op_SXR uint32 = 0x3700
2428 op_SXTR uint32 = 0xB3DB
2429 op_SXTRA uint32 = 0xB3DB
2430 op_SY uint32 = 0xE35B
2431 op_TABORT uint32 = 0xB2FC
2432 op_TAM uint32 = 0x010B
2433 op_TAR uint32 = 0xB24C
2434 op_TB uint32 = 0xB22C
2435 op_TBDR uint32 = 0xB351
2436 op_TBEDR uint32 = 0xB350
2437 op_TBEGIN uint32 = 0xE560
2438 op_TBEGINC uint32 = 0xE561
2439 op_TCDB uint32 = 0xED11
2440 op_TCEB uint32 = 0xED10
2441 op_TCXB uint32 = 0xED12
2442 op_TDCDT uint32 = 0xED54
2443 op_TDCET uint32 = 0xED50
2444 op_TDCXT uint32 = 0xED58
2445 op_TDGDT uint32 = 0xED55
2446 op_TDGET uint32 = 0xED51
2447 op_TDGXT uint32 = 0xED59
2448 op_TEND uint32 = 0xB2F8
2449 op_THDER uint32 = 0xB358
2450 op_THDR uint32 = 0xB359
2451 op_TM uint32 = 0x9100
2452 op_TMH uint32 = 0xA700
2453 op_TMHH uint32 = 0xA702
2454 op_TMHL uint32 = 0xA703
2455 op_TML uint32 = 0xA701
2456 op_TMLH uint32 = 0xA700
2457 op_TMLL uint32 = 0xA701
2458 op_TMY uint32 = 0xEB51
2459 op_TP uint32 = 0xEBC0
2460 op_TPI uint32 = 0xB236
2461 op_TPROT uint32 = 0xE501
2462 op_TR uint32 = 0xDC00
2463 op_TRACE uint32 = 0x9900
2464 op_TRACG uint32 = 0xEB0F
2465 op_TRAP2 uint32 = 0x01FF
2466 op_TRAP4 uint32 = 0xB2FF
2467 op_TRE uint32 = 0xB2A5
2468 op_TROO uint32 = 0xB993
2469 op_TROT uint32 = 0xB992
2470 op_TRT uint32 = 0xDD00
2471 op_TRTE uint32 = 0xB9BF
2472 op_TRTO uint32 = 0xB991
2473 op_TRTR uint32 = 0xD000
2474 op_TRTRE uint32 = 0xB9BD
2475 op_TRTT uint32 = 0xB990
2476 op_TS uint32 = 0x9300
2477 op_TSCH uint32 = 0xB235
2478 op_UNPK uint32 = 0xF300
2479 op_UNPKA uint32 = 0xEA00
2480 op_UNPKU uint32 = 0xE200
2481 op_UPT uint32 = 0x0102
2482 op_X uint32 = 0x5700
2483 op_XC uint32 = 0xD700
2484 op_XG uint32 = 0xE382
2485 op_XGR uint32 = 0xB982
2486 op_XGRK uint32 = 0xB9E7
2487 op_XI uint32 = 0x9700
2488 op_XIHF uint32 = 0xC006
2489 op_XILF uint32 = 0xC007
2490 op_XIY uint32 = 0xEB57
2491 op_XR uint32 = 0x1700
2492 op_XRK uint32 = 0xB9F7
2493 op_XSCH uint32 = 0xB276
2494 op_XY uint32 = 0xE357
2495 op_ZAP uint32 = 0xF800
2496 op_BRRK uint32 = 0x0001
2497
2498
2499 op_CXPT uint32 = 0xEDAF
2500 op_CDPT uint32 = 0xEDAE
2501 op_CPXT uint32 = 0xEDAD
2502 op_CPDT uint32 = 0xEDAC
2503 op_LZRF uint32 = 0xE33B
2504 op_LZRG uint32 = 0xE32A
2505 op_LCCB uint32 = 0xE727
2506 op_LOCHHI uint32 = 0xEC4E
2507 op_LOCHI uint32 = 0xEC42
2508 op_LOCGHI uint32 = 0xEC46
2509 op_LOCFH uint32 = 0xEBE0
2510 op_LOCFHR uint32 = 0xB9E0
2511 op_LLZRGF uint32 = 0xE33A
2512 op_STOCFH uint32 = 0xEBE1
2513 op_VA uint32 = 0xE7F3
2514 op_VACC uint32 = 0xE7F1
2515 op_VAC uint32 = 0xE7BB
2516 op_VACCC uint32 = 0xE7B9
2517 op_VN uint32 = 0xE768
2518 op_VNC uint32 = 0xE769
2519 op_VAVG uint32 = 0xE7F2
2520 op_VAVGL uint32 = 0xE7F0
2521 op_VCKSM uint32 = 0xE766
2522 op_VCEQ uint32 = 0xE7F8
2523 op_VCH uint32 = 0xE7FB
2524 op_VCHL uint32 = 0xE7F9
2525 op_VCLZ uint32 = 0xE753
2526 op_VCTZ uint32 = 0xE752
2527 op_VEC uint32 = 0xE7DB
2528 op_VECL uint32 = 0xE7D9
2529 op_VERIM uint32 = 0xE772
2530 op_VERLL uint32 = 0xE733
2531 op_VERLLV uint32 = 0xE773
2532 op_VESLV uint32 = 0xE770
2533 op_VESL uint32 = 0xE730
2534 op_VESRA uint32 = 0xE73A
2535 op_VESRAV uint32 = 0xE77A
2536 op_VESRL uint32 = 0xE738
2537 op_VESRLV uint32 = 0xE778
2538 op_VX uint32 = 0xE76D
2539 op_VFAE uint32 = 0xE782
2540 op_VFEE uint32 = 0xE780
2541 op_VFENE uint32 = 0xE781
2542 op_VFA uint32 = 0xE7E3
2543 op_WFK uint32 = 0xE7CA
2544 op_VFCE uint32 = 0xE7E8
2545 op_VFCH uint32 = 0xE7EB
2546 op_VFCHE uint32 = 0xE7EA
2547 op_WFC uint32 = 0xE7CB
2548 op_VCDG uint32 = 0xE7C3
2549 op_VCDLG uint32 = 0xE7C1
2550 op_VCGD uint32 = 0xE7C2
2551 op_VCLGD uint32 = 0xE7C0
2552 op_VFD uint32 = 0xE7E5
2553 op_VLDE uint32 = 0xE7C4
2554 op_VLED uint32 = 0xE7C5
2555 op_VFM uint32 = 0xE7E7
2556 op_VFMA uint32 = 0xE78F
2557 op_VFMS uint32 = 0xE78E
2558 op_VFPSO uint32 = 0xE7CC
2559 op_VFSQ uint32 = 0xE7CE
2560 op_VFS uint32 = 0xE7E2
2561 op_VFTCI uint32 = 0xE74A
2562 op_VGFM uint32 = 0xE7B4
2563 op_VGFMA uint32 = 0xE7BC
2564 op_VGEF uint32 = 0xE713
2565 op_VGEG uint32 = 0xE712
2566 op_VGBM uint32 = 0xE744
2567 op_VGM uint32 = 0xE746
2568 op_VISTR uint32 = 0xE75C
2569 op_VL uint32 = 0xE706
2570 op_VLR uint32 = 0xE756
2571 op_VLREP uint32 = 0xE705
2572 op_VLC uint32 = 0xE7DE
2573 op_VLEH uint32 = 0xE701
2574 op_VLEF uint32 = 0xE703
2575 op_VLEG uint32 = 0xE702
2576 op_VLEB uint32 = 0xE700
2577 op_VLEIH uint32 = 0xE741
2578 op_VLEIF uint32 = 0xE743
2579 op_VLEIG uint32 = 0xE742
2580 op_VLEIB uint32 = 0xE740
2581 op_VFI uint32 = 0xE7C7
2582 op_VLGV uint32 = 0xE721
2583 op_VLLEZ uint32 = 0xE704
2584 op_VLM uint32 = 0xE736
2585 op_VLP uint32 = 0xE7DF
2586 op_VLBB uint32 = 0xE707
2587 op_VLVG uint32 = 0xE722
2588 op_VLVGP uint32 = 0xE762
2589 op_VLL uint32 = 0xE737
2590 op_VMX uint32 = 0xE7FF
2591 op_VMXL uint32 = 0xE7FD
2592 op_VMRH uint32 = 0xE761
2593 op_VMRL uint32 = 0xE760
2594 op_VMN uint32 = 0xE7FE
2595 op_VMNL uint32 = 0xE7FC
2596 op_VMAE uint32 = 0xE7AE
2597 op_VMAH uint32 = 0xE7AB
2598 op_VMALE uint32 = 0xE7AC
2599 op_VMALH uint32 = 0xE7A9
2600 op_VMALO uint32 = 0xE7AD
2601 op_VMAL uint32 = 0xE7AA
2602 op_VMAO uint32 = 0xE7AF
2603 op_VME uint32 = 0xE7A6
2604 op_VMH uint32 = 0xE7A3
2605 op_VMLE uint32 = 0xE7A4
2606 op_VMLH uint32 = 0xE7A1
2607 op_VMLO uint32 = 0xE7A5
2608 op_VML uint32 = 0xE7A2
2609 op_VMO uint32 = 0xE7A7
2610 op_VNO uint32 = 0xE76B
2611 op_VO uint32 = 0xE76A
2612 op_VPK uint32 = 0xE794
2613 op_VPKLS uint32 = 0xE795
2614 op_VPKS uint32 = 0xE797
2615 op_VPERM uint32 = 0xE78C
2616 op_VPDI uint32 = 0xE784
2617 op_VPOPCT uint32 = 0xE750
2618 op_VREP uint32 = 0xE74D
2619 op_VREPI uint32 = 0xE745
2620 op_VSCEF uint32 = 0xE71B
2621 op_VSCEG uint32 = 0xE71A
2622 op_VSEL uint32 = 0xE78D
2623 op_VSL uint32 = 0xE774
2624 op_VSLB uint32 = 0xE775
2625 op_VSLDB uint32 = 0xE777
2626 op_VSRA uint32 = 0xE77E
2627 op_VSRAB uint32 = 0xE77F
2628 op_VSRL uint32 = 0xE77C
2629 op_VSRLB uint32 = 0xE77D
2630 op_VSEG uint32 = 0xE75F
2631 op_VST uint32 = 0xE70E
2632 op_VSTEH uint32 = 0xE709
2633 op_VSTEF uint32 = 0xE70B
2634 op_VSTEG uint32 = 0xE70A
2635 op_VSTEB uint32 = 0xE708
2636 op_VSTM uint32 = 0xE73E
2637 op_VSTL uint32 = 0xE73F
2638 op_VSTRC uint32 = 0xE78A
2639 op_VS uint32 = 0xE7F7
2640 op_VSCBI uint32 = 0xE7F5
2641 op_VSBCBI uint32 = 0xE7BD
2642 op_VSBI uint32 = 0xE7BF
2643 op_VSUMG uint32 = 0xE765
2644 op_VSUMQ uint32 = 0xE767
2645 op_VSUM uint32 = 0xE764
2646 op_VTM uint32 = 0xE7D8
2647 op_VUPH uint32 = 0xE7D7
2648 op_VUPLH uint32 = 0xE7D5
2649 op_VUPLL uint32 = 0xE7D4
2650 op_VUPL uint32 = 0xE7D6
2651 op_VMSL uint32 = 0xE7B8
2652 op_VFMAX uint32 = 0xE7EF
2653 op_VFMIN uint32 = 0xE7EE
2654
2655
2656 op_KDSA uint32 = 0xB93A
2657
2658 )
2659
2660 func oclass(a *obj.Addr) int {
2661 return int(a.Class) - 1
2662 }
2663
2664
2665
2666 func (c *ctxtz) addrilreloc(sym *obj.LSym, add int64) {
2667 if sym == nil {
2668 c.ctxt.Diag("require symbol to apply relocation")
2669 }
2670 offset := int64(2)
2671 c.cursym.AddRel(c.ctxt, obj.Reloc{
2672 Type: objabi.R_PCRELDBL,
2673 Off: int32(c.pc + offset),
2674 Siz: 4,
2675 Sym: sym,
2676 Add: add + offset + 4,
2677 })
2678 }
2679
2680
2681
2682 func (c *ctxtz) addcallreloc(sym *obj.LSym, add int64) {
2683 if sym == nil {
2684 c.ctxt.Diag("require symbol to apply relocation")
2685 }
2686 offset := int64(2)
2687 c.cursym.AddRel(c.ctxt, obj.Reloc{
2688 Type: objabi.R_CALL,
2689 Off: int32(c.pc + offset),
2690 Siz: 4,
2691 Sym: sym,
2692 Add: add + offset + int64(4),
2693 })
2694 }
2695
2696 func (c *ctxtz) branchMask(p *obj.Prog) CCMask {
2697 switch p.As {
2698 case ABRC, ALOCR, ALOCGR,
2699 ACRJ, ACGRJ, ACIJ, ACGIJ,
2700 ACLRJ, ACLGRJ, ACLIJ, ACLGIJ:
2701 return CCMask(p.From.Offset)
2702 case ABEQ, ACMPBEQ, ACMPUBEQ, AMOVDEQ:
2703 return Equal
2704 case ABGE, ACMPBGE, ACMPUBGE, AMOVDGE:
2705 return GreaterOrEqual
2706 case ABGT, ACMPBGT, ACMPUBGT, AMOVDGT:
2707 return Greater
2708 case ABLE, ACMPBLE, ACMPUBLE, AMOVDLE:
2709 return LessOrEqual
2710 case ABLT, ACMPBLT, ACMPUBLT, AMOVDLT:
2711 return Less
2712 case ABNE, ACMPBNE, ACMPUBNE, AMOVDNE:
2713 return NotEqual
2714 case ABLEU:
2715 return NotGreater
2716 case ABLTU:
2717 return LessOrUnordered
2718 case ABVC:
2719 return Never
2720 case ABVS:
2721 return Unordered
2722 }
2723 c.ctxt.Diag("unknown conditional branch %v", p.As)
2724 return Always
2725 }
2726
2727 func regtmp(p *obj.Prog) uint32 {
2728 p.Mark |= USETMP
2729 return REGTMP
2730 }
2731
2732 func (c *ctxtz) asmout(p *obj.Prog, asm *[]byte) {
2733 o := c.oplook(p)
2734
2735 if o == nil {
2736 return
2737 }
2738
2739
2740
2741
2742 switch o.i {
2743 default:
2744 c.ctxt.Diag("unknown index %d", o.i)
2745
2746 case 0:
2747 break
2748
2749 case 1:
2750 switch p.As {
2751 default:
2752 c.ctxt.Diag("unhandled operation: %v", p.As)
2753 case AMOVD:
2754 zRRE(op_LGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2755
2756 case AMOVW:
2757 zRRE(op_LGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2758 case AMOVH:
2759 zRRE(op_LGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2760 case AMOVB:
2761 zRRE(op_LGBR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2762
2763 case AMOVWZ:
2764 zRRE(op_LLGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2765 case AMOVHZ:
2766 zRRE(op_LLGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2767 case AMOVBZ:
2768 zRRE(op_LLGCR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2769
2770 case AMOVDBR:
2771 zRRE(op_LRVGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2772 case AMOVWBR:
2773 zRRE(op_LRVR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2774
2775 case AFMOVD, AFMOVS:
2776 zRR(op_LDR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2777 }
2778
2779 case 2:
2780 r := p.Reg
2781 if r == 0 {
2782 r = p.To.Reg
2783 }
2784
2785 var opcode uint32
2786
2787 switch p.As {
2788 default:
2789 c.ctxt.Diag("invalid opcode")
2790 case AADD:
2791 opcode = op_AGRK
2792 case AADDC:
2793 opcode = op_ALGRK
2794 case AADDE:
2795 opcode = op_ALCGR
2796 case AADDW:
2797 opcode = op_ARK
2798 case AMULLW:
2799 opcode = op_MSGFR
2800 case AMULLD:
2801 opcode = op_MSGR
2802 case ADIVW, AMODW:
2803 opcode = op_DSGFR
2804 case ADIVWU, AMODWU:
2805 opcode = op_DLR
2806 case ADIVD, AMODD:
2807 opcode = op_DSGR
2808 case ADIVDU, AMODDU:
2809 opcode = op_DLGR
2810 }
2811
2812 switch p.As {
2813 default:
2814
2815 case AADD, AADDC, AADDW:
2816 if p.As == AADDW && r == p.To.Reg {
2817 zRR(op_AR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2818 } else {
2819 zRRF(opcode, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm)
2820 }
2821
2822 case AADDE, AMULLW, AMULLD:
2823 if r == p.To.Reg {
2824 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2825 } else if p.From.Reg == p.To.Reg {
2826 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm)
2827 } else {
2828 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
2829 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2830 }
2831
2832 case ADIVW, ADIVWU, ADIVD, ADIVDU:
2833 if p.As == ADIVWU || p.As == ADIVDU {
2834 zRI(op_LGHI, regtmp(p), 0, asm)
2835 }
2836 zRRE(op_LGR, REGTMP2, uint32(r), asm)
2837 zRRE(opcode, regtmp(p), uint32(p.From.Reg), asm)
2838 zRRE(op_LGR, uint32(p.To.Reg), REGTMP2, asm)
2839
2840 case AMODW, AMODWU, AMODD, AMODDU:
2841 if p.As == AMODWU || p.As == AMODDU {
2842 zRI(op_LGHI, regtmp(p), 0, asm)
2843 }
2844 zRRE(op_LGR, REGTMP2, uint32(r), asm)
2845 zRRE(opcode, regtmp(p), uint32(p.From.Reg), asm)
2846 zRRE(op_LGR, uint32(p.To.Reg), regtmp(p), asm)
2847
2848 }
2849
2850 case 3:
2851 v := c.vregoff(&p.From)
2852 switch p.As {
2853 case AMOVBZ:
2854 v = int64(uint8(v))
2855 case AMOVHZ:
2856 v = int64(uint16(v))
2857 case AMOVWZ:
2858 v = int64(uint32(v))
2859 case AMOVB:
2860 v = int64(int8(v))
2861 case AMOVH:
2862 v = int64(int16(v))
2863 case AMOVW:
2864 v = int64(int32(v))
2865 }
2866 if int64(int16(v)) == v {
2867 zRI(op_LGHI, uint32(p.To.Reg), uint32(v), asm)
2868 } else if v&0xffff0000 == v {
2869 zRI(op_LLILH, uint32(p.To.Reg), uint32(v>>16), asm)
2870 } else if v&0xffff00000000 == v {
2871 zRI(op_LLIHL, uint32(p.To.Reg), uint32(v>>32), asm)
2872 } else if uint64(v)&0xffff000000000000 == uint64(v) {
2873 zRI(op_LLIHH, uint32(p.To.Reg), uint32(v>>48), asm)
2874 } else if int64(int32(v)) == v {
2875 zRIL(_a, op_LGFI, uint32(p.To.Reg), uint32(v), asm)
2876 } else if int64(uint32(v)) == v {
2877 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm)
2878 } else if uint64(v)&0xffffffff00000000 == uint64(v) {
2879 zRIL(_a, op_LLIHF, uint32(p.To.Reg), uint32(v>>32), asm)
2880 } else {
2881 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm)
2882 zRIL(_a, op_IIHF, uint32(p.To.Reg), uint32(v>>32), asm)
2883 }
2884
2885 case 4:
2886 r := p.Reg
2887 if r == 0 {
2888 r = p.To.Reg
2889 }
2890 zRRE(op_LGR, REGTMP2, uint32(r), asm)
2891 zRRE(op_MLGR, regtmp(p), uint32(p.From.Reg), asm)
2892 switch p.As {
2893 case AMULHDU:
2894
2895 zRRE(op_LGR, uint32(p.To.Reg), regtmp(p), asm)
2896 case AMULHD:
2897
2898
2899 zRSY(op_SRAG, REGTMP2, uint32(p.From.Reg), 0, 63, asm)
2900 zRRE(op_NGR, REGTMP2, uint32(r), asm)
2901 zRRE(op_SGR, regtmp(p), REGTMP2, asm)
2902 zRSY(op_SRAG, REGTMP2, uint32(r), 0, 63, asm)
2903 zRRE(op_NGR, REGTMP2, uint32(p.From.Reg), asm)
2904 zRRF(op_SGRK, REGTMP2, 0, uint32(p.To.Reg), regtmp(p), asm)
2905 }
2906
2907 case 5:
2908 zI(op_SVC, 0, asm)
2909
2910 case 6:
2911 var oprr, oprre, oprrf uint32
2912 switch p.As {
2913 case AAND:
2914 oprre = op_NGR
2915 oprrf = op_NGRK
2916 case AANDW:
2917 oprr = op_NR
2918 oprrf = op_NRK
2919 case AOR:
2920 oprre = op_OGR
2921 oprrf = op_OGRK
2922 case AORW:
2923 oprr = op_OR
2924 oprrf = op_ORK
2925 case AXOR:
2926 oprre = op_XGR
2927 oprrf = op_XGRK
2928 case AXORW:
2929 oprr = op_XR
2930 oprrf = op_XRK
2931 }
2932 if p.Reg == 0 {
2933 if oprr != 0 {
2934 zRR(oprr, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2935 } else {
2936 zRRE(oprre, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2937 }
2938 } else {
2939 zRRF(oprrf, uint32(p.Reg), 0, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2940 }
2941
2942 case 7:
2943 d2 := c.vregoff(&p.From)
2944 b2 := p.From.Reg
2945 r3 := p.Reg
2946 if r3 == 0 {
2947 r3 = p.To.Reg
2948 }
2949 r1 := p.To.Reg
2950 var opcode uint32
2951 switch p.As {
2952 default:
2953 case ASLD:
2954 opcode = op_SLLG
2955 case ASRD:
2956 opcode = op_SRLG
2957 case ASLW:
2958 opcode = op_SLLK
2959 case ASRW:
2960 opcode = op_SRLK
2961 case ARLL:
2962 opcode = op_RLL
2963 case ARLLG:
2964 opcode = op_RLLG
2965 case ASRAW:
2966 opcode = op_SRAK
2967 case ASRAD:
2968 opcode = op_SRAG
2969 }
2970 zRSY(opcode, uint32(r1), uint32(r3), uint32(b2), uint32(d2), asm)
2971
2972 case 8:
2973 if p.To.Reg&1 != 0 {
2974 c.ctxt.Diag("target must be an even-numbered register")
2975 }
2976
2977 zRRE(op_FLOGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2978
2979 case 9:
2980 zRRE(op_POPCNT, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2981
2982 case 10:
2983 r := int(p.Reg)
2984
2985 switch p.As {
2986 default:
2987 case ASUB:
2988 if r == 0 {
2989 zRRE(op_SGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2990 } else {
2991 zRRF(op_SGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm)
2992 }
2993 case ASUBC:
2994 if r == 0 {
2995 zRRE(op_SLGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2996 } else {
2997 zRRF(op_SLGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm)
2998 }
2999 case ASUBE:
3000 if r == 0 {
3001 r = int(p.To.Reg)
3002 }
3003 if r == int(p.To.Reg) {
3004 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3005 } else if p.From.Reg == p.To.Reg {
3006 zRRE(op_LGR, regtmp(p), uint32(p.From.Reg), asm)
3007 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
3008 zRRE(op_SLBGR, uint32(p.To.Reg), regtmp(p), asm)
3009 } else {
3010 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
3011 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3012 }
3013 case ASUBW:
3014 if r == 0 {
3015 zRR(op_SR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3016 } else {
3017 zRRF(op_SRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm)
3018 }
3019 }
3020
3021 case 11:
3022 v := int32(0)
3023
3024 if p.To.Target() != nil {
3025 v = int32((p.To.Target().Pc - p.Pc) >> 1)
3026 }
3027
3028 if p.As == ABR && p.To.Sym == nil && int32(int16(v)) == v {
3029 zRI(op_BRC, 0xF, uint32(v), asm)
3030 } else {
3031 if p.As == ABL {
3032 zRIL(_b, op_BRASL, uint32(REG_LR), uint32(v), asm)
3033 } else {
3034 zRIL(_c, op_BRCL, 0xF, uint32(v), asm)
3035 }
3036 if p.To.Sym != nil {
3037 c.addcallreloc(p.To.Sym, p.To.Offset)
3038 }
3039 }
3040
3041 case 12:
3042 r1 := p.To.Reg
3043 d2 := c.vregoff(&p.From)
3044 b2 := p.From.Reg
3045 if b2 == 0 {
3046 b2 = REGSP
3047 }
3048 x2 := p.From.Index
3049 if -DISP20/2 > d2 || d2 >= DISP20/2 {
3050 zRIL(_a, op_LGFI, regtmp(p), uint32(d2), asm)
3051 if x2 != 0 {
3052 zRX(op_LA, regtmp(p), regtmp(p), uint32(x2), 0, asm)
3053 }
3054 x2 = int16(regtmp(p))
3055 d2 = 0
3056 }
3057 var opx, opxy uint32
3058 switch p.As {
3059 case AADD:
3060 opxy = op_AG
3061 case AADDC:
3062 opxy = op_ALG
3063 case AADDE:
3064 opxy = op_ALCG
3065 case AADDW:
3066 opx = op_A
3067 opxy = op_AY
3068 case AMULLW:
3069 opx = op_MS
3070 opxy = op_MSY
3071 case AMULLD:
3072 opxy = op_MSG
3073 case ASUB:
3074 opxy = op_SG
3075 case ASUBC:
3076 opxy = op_SLG
3077 case ASUBE:
3078 opxy = op_SLBG
3079 case ASUBW:
3080 opx = op_S
3081 opxy = op_SY
3082 case AAND:
3083 opxy = op_NG
3084 case AANDW:
3085 opx = op_N
3086 opxy = op_NY
3087 case AOR:
3088 opxy = op_OG
3089 case AORW:
3090 opx = op_O
3091 opxy = op_OY
3092 case AXOR:
3093 opxy = op_XG
3094 case AXORW:
3095 opx = op_X
3096 opxy = op_XY
3097 }
3098 if opx != 0 && 0 <= d2 && d2 < DISP12 {
3099 zRX(opx, uint32(r1), uint32(x2), uint32(b2), uint32(d2), asm)
3100 } else {
3101 zRXY(opxy, uint32(r1), uint32(x2), uint32(b2), uint32(d2), asm)
3102 }
3103
3104 case 13:
3105 r1 := p.To.Reg
3106 r2 := p.RestArgs[2].Reg
3107 i3 := uint8(p.From.Offset)
3108 i4 := uint8(p.RestArgs[0].Offset)
3109 i5 := uint8(p.RestArgs[1].Offset)
3110 switch p.As {
3111 case ARNSBGT, ARXSBGT, AROSBGT:
3112 i3 |= 0x80
3113 case ARISBGZ, ARISBGNZ, ARISBHGZ, ARISBLGZ:
3114 i4 |= 0x80
3115 }
3116 var opcode uint32
3117 switch p.As {
3118 case ARNSBG, ARNSBGT:
3119 opcode = op_RNSBG
3120 case ARXSBG, ARXSBGT:
3121 opcode = op_RXSBG
3122 case AROSBG, AROSBGT:
3123 opcode = op_ROSBG
3124 case ARISBG, ARISBGZ:
3125 opcode = op_RISBG
3126 case ARISBGN, ARISBGNZ:
3127 opcode = op_RISBGN
3128 case ARISBHG, ARISBHGZ:
3129 opcode = op_RISBHG
3130 case ARISBLG, ARISBLGZ:
3131 opcode = op_RISBLG
3132 }
3133 zRIE(_f, uint32(opcode), uint32(r1), uint32(r2), 0, uint32(i3), uint32(i4), 0, uint32(i5), asm)
3134
3135 case 15:
3136 r := p.To.Reg
3137 if p.As == ABCL || p.As == ABL {
3138 zRR(op_BASR, uint32(REG_LR), uint32(r), asm)
3139 } else {
3140 zRR(op_BCR, uint32(Always), uint32(r), asm)
3141 }
3142
3143 case 16:
3144 v := int32(0)
3145 if p.To.Target() != nil {
3146 v = int32((p.To.Target().Pc - p.Pc) >> 1)
3147 }
3148 mask := uint32(c.branchMask(p))
3149 if p.To.Sym == nil && int32(int16(v)) == v {
3150 zRI(op_BRC, mask, uint32(v), asm)
3151 } else {
3152 zRIL(_c, op_BRCL, mask, uint32(v), asm)
3153 }
3154 if p.To.Sym != nil {
3155 c.addrilreloc(p.To.Sym, p.To.Offset)
3156 }
3157
3158 case 17:
3159 m3 := uint32(c.branchMask(p))
3160 zRRF(op_LOCGR, m3, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3161
3162 case 18:
3163 if p.As == ABL {
3164 zRR(op_BASR, uint32(REG_LR), uint32(p.To.Reg), asm)
3165 } else {
3166 zRR(op_BCR, uint32(Always), uint32(p.To.Reg), asm)
3167 }
3168
3169 case 19:
3170 d := c.vregoff(&p.From)
3171 zRIL(_b, op_LARL, uint32(p.To.Reg), 0, asm)
3172 if d&1 != 0 {
3173 zRX(op_LA, uint32(p.To.Reg), uint32(p.To.Reg), 0, 1, asm)
3174 d -= 1
3175 }
3176 c.addrilreloc(p.From.Sym, d)
3177
3178 case 21:
3179 v := c.vregoff(&p.From)
3180 r := p.Reg
3181 if r == 0 {
3182 r = p.To.Reg
3183 }
3184 switch p.As {
3185 case ASUB:
3186 zRIL(_a, op_LGFI, uint32(regtmp(p)), uint32(v), asm)
3187 zRRF(op_SLGRK, uint32(regtmp(p)), 0, uint32(p.To.Reg), uint32(r), asm)
3188 case ASUBC:
3189 if r != p.To.Reg {
3190 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
3191 }
3192 zRIL(_a, op_SLGFI, uint32(p.To.Reg), uint32(v), asm)
3193 case ASUBW:
3194 if r != p.To.Reg {
3195 zRR(op_LR, uint32(p.To.Reg), uint32(r), asm)
3196 }
3197 zRIL(_a, op_SLFI, uint32(p.To.Reg), uint32(v), asm)
3198 }
3199
3200 case 22:
3201 v := c.vregoff(&p.From)
3202 r := p.Reg
3203 if r == 0 {
3204 r = p.To.Reg
3205 }
3206 var opri, opril, oprie uint32
3207 switch p.As {
3208 case AADD:
3209 opri = op_AGHI
3210 opril = op_AGFI
3211 oprie = op_AGHIK
3212 case AADDC:
3213 opril = op_ALGFI
3214 oprie = op_ALGHSIK
3215 case AADDW:
3216 opri = op_AHI
3217 opril = op_AFI
3218 oprie = op_AHIK
3219 case AMULLW:
3220 opri = op_MHI
3221 opril = op_MSFI
3222 case AMULLD:
3223 opri = op_MGHI
3224 opril = op_MSGFI
3225 }
3226 if r != p.To.Reg && (oprie == 0 || int64(int16(v)) != v) {
3227 switch p.As {
3228 case AADD, AADDC, AMULLD:
3229 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
3230 case AADDW, AMULLW:
3231 zRR(op_LR, uint32(p.To.Reg), uint32(r), asm)
3232 }
3233 r = p.To.Reg
3234 }
3235 if opri != 0 && r == p.To.Reg && int64(int16(v)) == v {
3236 zRI(opri, uint32(p.To.Reg), uint32(v), asm)
3237 } else if oprie != 0 && int64(int16(v)) == v {
3238 zRIE(_d, oprie, uint32(p.To.Reg), uint32(r), uint32(v), 0, 0, 0, 0, asm)
3239 } else {
3240 zRIL(_a, opril, uint32(p.To.Reg), uint32(v), asm)
3241 }
3242
3243 case 23:
3244
3245 v := c.vregoff(&p.From)
3246 switch p.As {
3247 default:
3248 c.ctxt.Diag("%v is not supported", p)
3249 case AAND:
3250 if v >= 0 {
3251 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm)
3252 zRRE(op_NGR, uint32(p.To.Reg), regtmp(p), asm)
3253 } else if int64(int16(v)) == v {
3254 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm)
3255 } else {
3256 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm)
3257 }
3258 case AOR:
3259 if int64(uint32(v)) != v {
3260 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm)
3261 zRRE(op_OGR, uint32(p.To.Reg), regtmp(p), asm)
3262 } else if int64(uint16(v)) == v {
3263 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm)
3264 } else {
3265 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm)
3266 }
3267 case AXOR:
3268 if int64(uint32(v)) != v {
3269 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm)
3270 zRRE(op_XGR, uint32(p.To.Reg), regtmp(p), asm)
3271 } else {
3272 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm)
3273 }
3274 }
3275
3276 case 24:
3277 v := c.vregoff(&p.From)
3278 switch p.As {
3279 case AANDW:
3280 if uint32(v&0xffff0000) == 0xffff0000 {
3281 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm)
3282 } else if uint32(v&0x0000ffff) == 0x0000ffff {
3283 zRI(op_NILH, uint32(p.To.Reg), uint32(v)>>16, asm)
3284 } else {
3285 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm)
3286 }
3287 case AORW:
3288 if uint32(v&0xffff0000) == 0 {
3289 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm)
3290 } else if uint32(v&0x0000ffff) == 0 {
3291 zRI(op_OILH, uint32(p.To.Reg), uint32(v)>>16, asm)
3292 } else {
3293 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm)
3294 }
3295 case AXORW:
3296 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm)
3297 }
3298
3299 case 25:
3300 m3 := uint32(c.branchMask(p))
3301 var opcode uint32
3302 switch p.As {
3303 case ALOCR:
3304 opcode = op_LOCR
3305 case ALOCGR:
3306 opcode = op_LOCGR
3307 }
3308 zRRF(opcode, m3, 0, uint32(p.To.Reg), uint32(p.Reg), asm)
3309
3310 case 26:
3311 v := c.regoff(&p.From)
3312 r := p.From.Reg
3313 if r == 0 {
3314 r = REGSP
3315 }
3316 i := p.From.Index
3317 if v >= 0 && v < DISP12 {
3318 zRX(op_LA, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm)
3319 } else if v >= -DISP20/2 && v < DISP20/2 {
3320 zRXY(op_LAY, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm)
3321 } else {
3322 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm)
3323 zRX(op_LA, uint32(p.To.Reg), uint32(r), regtmp(p), uint32(i), asm)
3324 }
3325
3326 case 31:
3327 wd := uint64(c.vregoff(&p.From))
3328 *asm = append(*asm,
3329 uint8(wd>>56),
3330 uint8(wd>>48),
3331 uint8(wd>>40),
3332 uint8(wd>>32),
3333 uint8(wd>>24),
3334 uint8(wd>>16),
3335 uint8(wd>>8),
3336 uint8(wd))
3337
3338 case 32:
3339 var opcode uint32
3340 switch p.As {
3341 default:
3342 c.ctxt.Diag("invalid opcode")
3343 case AFADD:
3344 opcode = op_ADBR
3345 case AFADDS:
3346 opcode = op_AEBR
3347 case AFDIV:
3348 opcode = op_DDBR
3349 case AFDIVS:
3350 opcode = op_DEBR
3351 case AFMUL:
3352 opcode = op_MDBR
3353 case AFMULS:
3354 opcode = op_MEEBR
3355 case AFSUB:
3356 opcode = op_SDBR
3357 case AFSUBS:
3358 opcode = op_SEBR
3359 }
3360 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3361
3362 case 33:
3363 r := p.From.Reg
3364 if oclass(&p.From) == C_NONE {
3365 r = p.To.Reg
3366 }
3367 var opcode uint32
3368 switch p.As {
3369 default:
3370 case AFABS:
3371 opcode = op_LPDBR
3372 case AFNABS:
3373 opcode = op_LNDBR
3374 case ALPDFR:
3375 opcode = op_LPDFR
3376 case ALNDFR:
3377 opcode = op_LNDFR
3378 case AFNEG:
3379 opcode = op_LCDFR
3380 case AFNEGS:
3381 opcode = op_LCEBR
3382 case ALCDBR:
3383 opcode = op_LCDBR
3384 case ALEDBR:
3385 opcode = op_LEDBR
3386 case ALDEBR:
3387 opcode = op_LDEBR
3388 case AFSQRT:
3389 opcode = op_SQDBR
3390 case AFSQRTS:
3391 opcode = op_SQEBR
3392 }
3393 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm)
3394
3395 case 34:
3396 var opcode uint32
3397 switch p.As {
3398 default:
3399 c.ctxt.Diag("invalid opcode")
3400 case AFMADD:
3401 opcode = op_MADBR
3402 case AFMADDS:
3403 opcode = op_MAEBR
3404 case AFMSUB:
3405 opcode = op_MSDBR
3406 case AFMSUBS:
3407 opcode = op_MSEBR
3408 }
3409 zRRD(opcode, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm)
3410
3411 case 35:
3412 d2 := c.regoff(&p.To)
3413 b2 := p.To.Reg
3414 if b2 == 0 {
3415 b2 = REGSP
3416 }
3417 x2 := p.To.Index
3418 if d2 < -DISP20/2 || d2 >= DISP20/2 {
3419 zRIL(_a, op_LGFI, regtmp(p), uint32(d2), asm)
3420 if x2 != 0 {
3421 zRX(op_LA, regtmp(p), regtmp(p), uint32(x2), 0, asm)
3422 }
3423 x2 = int16(regtmp(p))
3424 d2 = 0
3425 }
3426
3427 if op, ok := c.zopstore12(p.As); ok && isU12(d2) {
3428 zRX(op, uint32(p.From.Reg), uint32(x2), uint32(b2), uint32(d2), asm)
3429 } else {
3430 zRXY(c.zopstore(p.As), uint32(p.From.Reg), uint32(x2), uint32(b2), uint32(d2), asm)
3431 }
3432
3433 case 36:
3434 d2 := c.regoff(&p.From)
3435 b2 := p.From.Reg
3436 if b2 == 0 {
3437 b2 = REGSP
3438 }
3439 x2 := p.From.Index
3440 if d2 < -DISP20/2 || d2 >= DISP20/2 {
3441 zRIL(_a, op_LGFI, regtmp(p), uint32(d2), asm)
3442 if x2 != 0 {
3443 zRX(op_LA, regtmp(p), regtmp(p), uint32(x2), 0, asm)
3444 }
3445 x2 = int16(regtmp(p))
3446 d2 = 0
3447 }
3448
3449 if op, ok := c.zopload12(p.As); ok && isU12(d2) {
3450 zRX(op, uint32(p.To.Reg), uint32(x2), uint32(b2), uint32(d2), asm)
3451 } else {
3452 zRXY(c.zopload(p.As), uint32(p.To.Reg), uint32(x2), uint32(b2), uint32(d2), asm)
3453 }
3454
3455 case 40:
3456 wd := uint32(c.regoff(&p.From))
3457 if p.As == AWORD {
3458 *asm = append(*asm, uint8(wd>>24), uint8(wd>>16), uint8(wd>>8), uint8(wd))
3459 } else {
3460 *asm = append(*asm, uint8(wd))
3461 }
3462
3463 case 41:
3464 r1 := p.From.Reg
3465 ri2 := (p.To.Target().Pc - p.Pc) >> 1
3466 if int64(int16(ri2)) != ri2 {
3467 c.ctxt.Diag("branch target too far away")
3468 }
3469 var opcode uint32
3470 switch p.As {
3471 case ABRCT:
3472 opcode = op_BRCT
3473 case ABRCTG:
3474 opcode = op_BRCTG
3475 }
3476 zRI(opcode, uint32(r1), uint32(ri2), asm)
3477
3478 case 47:
3479 r := p.From.Reg
3480 if r == 0 {
3481 r = p.To.Reg
3482 }
3483 switch p.As {
3484 case ANEG:
3485 zRRE(op_LCGR, uint32(p.To.Reg), uint32(r), asm)
3486 case ANEGW:
3487 zRRE(op_LCGFR, uint32(p.To.Reg), uint32(r), asm)
3488 }
3489
3490 case 48:
3491 m3 := c.vregoff(&p.From)
3492 if 0 > m3 || m3 > 7 {
3493 c.ctxt.Diag("mask (%v) must be in the range [0, 7]", m3)
3494 }
3495 var opcode uint32
3496 switch p.As {
3497 case AFIEBR:
3498 opcode = op_FIEBR
3499 case AFIDBR:
3500 opcode = op_FIDBR
3501 }
3502 zRRF(opcode, uint32(m3), 0, uint32(p.To.Reg), uint32(p.Reg), asm)
3503
3504 case 49:
3505 zRRF(op_CPSDR, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(p.Reg), asm)
3506
3507 case 50:
3508 var opcode uint32
3509 switch p.As {
3510 case ALTEBR:
3511 opcode = op_LTEBR
3512 case ALTDBR:
3513 opcode = op_LTDBR
3514 }
3515 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3516
3517 case 51:
3518 var opcode uint32
3519 switch p.As {
3520 case ATCEB:
3521 opcode = op_TCEB
3522 case ATCDB:
3523 opcode = op_TCDB
3524 }
3525 d2 := c.regoff(&p.To)
3526 zRXE(opcode, uint32(p.From.Reg), 0, 0, uint32(d2), 0, asm)
3527
3528 case 62:
3529 zRRE(op_MLGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3530
3531 case 66:
3532 zRR(op_BCR, uint32(Never), 0, asm)
3533
3534 case 67:
3535 var opcode uint32
3536 switch p.As {
3537 case AFMOVS:
3538 opcode = op_LZER
3539 case AFMOVD:
3540 opcode = op_LZDR
3541 }
3542 zRRE(opcode, uint32(p.To.Reg), 0, asm)
3543
3544 case 68:
3545 zRRE(op_EAR, uint32(p.To.Reg), uint32(p.From.Reg-REG_AR0), asm)
3546
3547 case 69:
3548 zRRE(op_SAR, uint32(p.To.Reg-REG_AR0), uint32(p.From.Reg), asm)
3549
3550 case 70:
3551 if p.As == ACMPW || p.As == ACMPWU {
3552 zRR(c.zoprr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm)
3553 } else {
3554 zRRE(c.zoprre(p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm)
3555 }
3556
3557 case 71:
3558 v := c.vregoff(&p.To)
3559 switch p.As {
3560 case ACMP, ACMPW:
3561 if int64(int32(v)) != v {
3562 c.ctxt.Diag("%v overflows an int32", v)
3563 }
3564 case ACMPU, ACMPWU:
3565 if int64(uint32(v)) != v {
3566 c.ctxt.Diag("%v overflows a uint32", v)
3567 }
3568 }
3569 if p.As == ACMP && int64(int16(v)) == v {
3570 zRI(op_CGHI, uint32(p.From.Reg), uint32(v), asm)
3571 } else if p.As == ACMPW && int64(int16(v)) == v {
3572 zRI(op_CHI, uint32(p.From.Reg), uint32(v), asm)
3573 } else {
3574 zRIL(_a, c.zopril(p.As), uint32(p.From.Reg), uint32(v), asm)
3575 }
3576
3577 case 72:
3578 v := c.regoff(&p.From)
3579 d := c.regoff(&p.To)
3580 r := p.To.Reg
3581 if p.To.Index != 0 {
3582 c.ctxt.Diag("cannot use index register")
3583 }
3584 if r == 0 {
3585 r = REGSP
3586 }
3587 var opcode uint32
3588 switch p.As {
3589 case AMOVD:
3590 opcode = op_MVGHI
3591 case AMOVW, AMOVWZ:
3592 opcode = op_MVHI
3593 case AMOVH, AMOVHZ:
3594 opcode = op_MVHHI
3595 case AMOVB, AMOVBZ:
3596 opcode = op_MVI
3597 }
3598 if d < 0 || d >= DISP12 {
3599 if r == int16(regtmp(p)) {
3600 c.ctxt.Diag("displacement must be in range [0, 4096) to use %v", r)
3601 }
3602 if d >= -DISP20/2 && d < DISP20/2 {
3603 if opcode == op_MVI {
3604 opcode = op_MVIY
3605 } else {
3606 zRXY(op_LAY, uint32(regtmp(p)), 0, uint32(r), uint32(d), asm)
3607 r = int16(regtmp(p))
3608 d = 0
3609 }
3610 } else {
3611 zRIL(_a, op_LGFI, regtmp(p), uint32(d), asm)
3612 zRX(op_LA, regtmp(p), regtmp(p), uint32(r), 0, asm)
3613 r = int16(regtmp(p))
3614 d = 0
3615 }
3616 }
3617 switch opcode {
3618 case op_MVI:
3619 zSI(opcode, uint32(v), uint32(r), uint32(d), asm)
3620 case op_MVIY:
3621 zSIY(opcode, uint32(v), uint32(r), uint32(d), asm)
3622 default:
3623 zSIL(opcode, uint32(r), uint32(d), uint32(v), asm)
3624 }
3625
3626 case 73:
3627 zE(op_BRRK, asm)
3628
3629 case 74:
3630 i2 := c.regoff(&p.To)
3631 switch p.As {
3632 case AMOVD:
3633 zRIL(_b, op_STGRL, uint32(p.From.Reg), 0, asm)
3634 case AMOVW, AMOVWZ:
3635 zRIL(_b, op_STRL, uint32(p.From.Reg), 0, asm)
3636 case AMOVH, AMOVHZ:
3637 zRIL(_b, op_STHRL, uint32(p.From.Reg), 0, asm)
3638 case AMOVB, AMOVBZ:
3639 zRIL(_b, op_LARL, regtmp(p), 0, asm)
3640 adj := uint32(0)
3641 if i2&1 != 0 {
3642 i2 -= 1
3643 adj = 1
3644 }
3645 zRX(op_STC, uint32(p.From.Reg), 0, regtmp(p), adj, asm)
3646 case AFMOVD:
3647 zRIL(_b, op_LARL, regtmp(p), 0, asm)
3648 zRX(op_STD, uint32(p.From.Reg), 0, regtmp(p), 0, asm)
3649 case AFMOVS:
3650 zRIL(_b, op_LARL, regtmp(p), 0, asm)
3651 zRX(op_STE, uint32(p.From.Reg), 0, regtmp(p), 0, asm)
3652 }
3653 c.addrilreloc(p.To.Sym, int64(i2))
3654
3655 case 75:
3656 i2 := c.regoff(&p.From)
3657 switch p.As {
3658 case AMOVD:
3659 if i2&1 != 0 {
3660 zRIL(_b, op_LARL, regtmp(p), 0, asm)
3661 zRXY(op_LG, uint32(p.To.Reg), regtmp(p), 0, 1, asm)
3662 i2 -= 1
3663 } else {
3664 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm)
3665 }
3666 case AMOVW:
3667 zRIL(_b, op_LGFRL, uint32(p.To.Reg), 0, asm)
3668 case AMOVWZ:
3669 zRIL(_b, op_LLGFRL, uint32(p.To.Reg), 0, asm)
3670 case AMOVH:
3671 zRIL(_b, op_LGHRL, uint32(p.To.Reg), 0, asm)
3672 case AMOVHZ:
3673 zRIL(_b, op_LLGHRL, uint32(p.To.Reg), 0, asm)
3674 case AMOVB, AMOVBZ:
3675 zRIL(_b, op_LARL, regtmp(p), 0, asm)
3676 adj := uint32(0)
3677 if i2&1 != 0 {
3678 i2 -= 1
3679 adj = 1
3680 }
3681 switch p.As {
3682 case AMOVB:
3683 zRXY(op_LGB, uint32(p.To.Reg), 0, regtmp(p), adj, asm)
3684 case AMOVBZ:
3685 zRXY(op_LLGC, uint32(p.To.Reg), 0, regtmp(p), adj, asm)
3686 }
3687 case AFMOVD:
3688 zRIL(_a, op_LARL, regtmp(p), 0, asm)
3689 zRX(op_LD, uint32(p.To.Reg), 0, regtmp(p), 0, asm)
3690 case AFMOVS:
3691 zRIL(_a, op_LARL, regtmp(p), 0, asm)
3692 zRX(op_LE, uint32(p.To.Reg), 0, regtmp(p), 0, asm)
3693 }
3694 c.addrilreloc(p.From.Sym, int64(i2))
3695
3696 case 76:
3697 zRR(op_SPM, uint32(p.From.Reg), 0, asm)
3698
3699 case 77:
3700 if p.From.Offset > 255 || p.From.Offset < 1 {
3701 c.ctxt.Diag("illegal system call; system call number out of range: %v", p)
3702 zE(op_TRAP2, asm)
3703 } else {
3704 zI(op_SVC, uint32(p.From.Offset), asm)
3705 }
3706
3707 case 78:
3708
3709
3710 *asm = append(*asm, 0, 0, 0, 0)
3711
3712 case 79:
3713 v := c.regoff(&p.To)
3714 if v < 0 {
3715 v = 0
3716 }
3717 if p.As == ACS {
3718 zRS(op_CS, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm)
3719 } else if p.As == ACSG {
3720 zRSY(op_CSG, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm)
3721 }
3722
3723 case 80:
3724 zRR(op_BCR, 14, 0, asm)
3725
3726 case 81:
3727 switch p.As {
3728 case ALDGR:
3729 zRRE(op_LDGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3730 case ALGDR:
3731 zRRE(op_LGDR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3732 }
3733
3734 case 82:
3735 var opcode uint32
3736 switch p.As {
3737 default:
3738 log.Fatalf("unexpected opcode %v", p.As)
3739 case ACEFBRA:
3740 opcode = op_CEFBRA
3741 case ACDFBRA:
3742 opcode = op_CDFBRA
3743 case ACEGBRA:
3744 opcode = op_CEGBRA
3745 case ACDGBRA:
3746 opcode = op_CDGBRA
3747 case ACELFBR:
3748 opcode = op_CELFBR
3749 case ACDLFBR:
3750 opcode = op_CDLFBR
3751 case ACELGBR:
3752 opcode = op_CELGBR
3753 case ACDLGBR:
3754 opcode = op_CDLGBR
3755 }
3756
3757
3758
3759
3760 zRRF(opcode, 0, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3761
3762 case 83:
3763 var opcode uint32
3764 switch p.As {
3765 default:
3766 log.Fatalf("unexpected opcode %v", p.As)
3767 case ACFEBRA:
3768 opcode = op_CFEBRA
3769 case ACFDBRA:
3770 opcode = op_CFDBRA
3771 case ACGEBRA:
3772 opcode = op_CGEBRA
3773 case ACGDBRA:
3774 opcode = op_CGDBRA
3775 case ACLFEBR:
3776 opcode = op_CLFEBR
3777 case ACLFDBR:
3778 opcode = op_CLFDBR
3779 case ACLGEBR:
3780 opcode = op_CLGEBR
3781 case ACLGDBR:
3782 opcode = op_CLGDBR
3783 }
3784
3785
3786 zRRF(opcode, 5, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3787
3788 case 84:
3789 l := c.regoff(&p.From)
3790 if l < 1 || l > 256 {
3791 c.ctxt.Diag("number of bytes (%v) not in range [1,256]", l)
3792 }
3793 if p.GetFrom3().Index != 0 || p.To.Index != 0 {
3794 c.ctxt.Diag("cannot use index reg")
3795 }
3796 b1 := p.To.Reg
3797 b2 := p.GetFrom3().Reg
3798 if b1 == 0 {
3799 b1 = REGSP
3800 }
3801 if b2 == 0 {
3802 b2 = REGSP
3803 }
3804 d1 := c.regoff(&p.To)
3805 d2 := c.regoff(p.GetFrom3())
3806 if d1 < 0 || d1 >= DISP12 {
3807 if b2 == int16(regtmp(p)) {
3808 c.ctxt.Diag("regtmp(p) conflict")
3809 }
3810 if b1 != int16(regtmp(p)) {
3811 zRRE(op_LGR, regtmp(p), uint32(b1), asm)
3812 }
3813 zRIL(_a, op_AGFI, regtmp(p), uint32(d1), asm)
3814 if d1 == d2 && b1 == b2 {
3815 d2 = 0
3816 b2 = int16(regtmp(p))
3817 }
3818 d1 = 0
3819 b1 = int16(regtmp(p))
3820 }
3821 if d2 < 0 || d2 >= DISP12 {
3822 if b1 == REGTMP2 {
3823 c.ctxt.Diag("REGTMP2 conflict")
3824 }
3825 if b2 != REGTMP2 {
3826 zRRE(op_LGR, REGTMP2, uint32(b2), asm)
3827 }
3828 zRIL(_a, op_AGFI, REGTMP2, uint32(d2), asm)
3829 d2 = 0
3830 b2 = REGTMP2
3831 }
3832 var opcode uint32
3833 switch p.As {
3834 default:
3835 c.ctxt.Diag("unexpected opcode %v", p.As)
3836 case AMVC:
3837 opcode = op_MVC
3838 case AMVCIN:
3839 opcode = op_MVCIN
3840 case ACLC:
3841 opcode = op_CLC
3842
3843 b1, b2 = b2, b1
3844 d1, d2 = d2, d1
3845 case AXC:
3846 opcode = op_XC
3847 case AOC:
3848 opcode = op_OC
3849 case ANC:
3850 opcode = op_NC
3851 }
3852 zSS(_a, opcode, uint32(l-1), 0, uint32(b1), uint32(d1), uint32(b2), uint32(d2), asm)
3853
3854 case 85:
3855 v := c.regoff(&p.From)
3856 if p.From.Sym == nil {
3857 if (v & 1) != 0 {
3858 c.ctxt.Diag("cannot use LARL with odd offset: %v", v)
3859 }
3860 } else {
3861 c.addrilreloc(p.From.Sym, int64(v))
3862 v = 0
3863 }
3864 zRIL(_b, op_LARL, uint32(p.To.Reg), uint32(v>>1), asm)
3865
3866 case 86:
3867 d := c.vregoff(&p.From)
3868 x := p.From.Index
3869 b := p.From.Reg
3870 if b == 0 {
3871 b = REGSP
3872 }
3873 switch p.As {
3874 case ALA:
3875 zRX(op_LA, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm)
3876 case ALAY:
3877 zRXY(op_LAY, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm)
3878 }
3879
3880 case 87:
3881 v := c.vregoff(&p.From)
3882 if p.From.Sym == nil {
3883 if v&1 != 0 {
3884 c.ctxt.Diag("cannot use EXRL with odd offset: %v", v)
3885 }
3886 } else {
3887 c.addrilreloc(p.From.Sym, v)
3888 v = 0
3889 }
3890 zRIL(_b, op_EXRL, uint32(p.To.Reg), uint32(v>>1), asm)
3891
3892 case 88:
3893 var opcode uint32
3894 switch p.As {
3895 case ASTCK:
3896 opcode = op_STCK
3897 case ASTCKC:
3898 opcode = op_STCKC
3899 case ASTCKE:
3900 opcode = op_STCKE
3901 case ASTCKF:
3902 opcode = op_STCKF
3903 }
3904 v := c.vregoff(&p.To)
3905 r := p.To.Reg
3906 if r == 0 {
3907 r = REGSP
3908 }
3909 zS(opcode, uint32(r), uint32(v), asm)
3910
3911 case 89:
3912 var v int32
3913 if p.To.Target() != nil {
3914 v = int32((p.To.Target().Pc - p.Pc) >> 1)
3915 }
3916
3917
3918 r1, r2 := p.From.Reg, p.Reg
3919 if p.From.Type == obj.TYPE_CONST {
3920 r1, r2 = p.Reg, p.RestArgs[0].Reg
3921 }
3922 m3 := uint32(c.branchMask(p))
3923
3924 var opcode uint32
3925 switch p.As {
3926 case ACRJ:
3927
3928 opcode = op_CRJ
3929 case ACGRJ, ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE:
3930
3931 opcode = op_CGRJ
3932 case ACLRJ:
3933
3934 opcode = op_CLRJ
3935 case ACLGRJ, ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE:
3936
3937 opcode = op_CLGRJ
3938 }
3939
3940 if int32(int16(v)) != v {
3941
3942
3943
3944
3945
3946
3947
3948
3949 m3 ^= 0xe
3950 zRIE(_b, opcode, uint32(r1), uint32(r2), uint32(sizeRIE+sizeRIL)/2, 0, 0, m3, 0, asm)
3951 zRIL(_c, op_BRCL, uint32(Always), uint32(v-sizeRIE/2), asm)
3952 } else {
3953 zRIE(_b, opcode, uint32(r1), uint32(r2), uint32(v), 0, 0, m3, 0, asm)
3954 }
3955
3956 case 90:
3957 var v int32
3958 if p.To.Target() != nil {
3959 v = int32((p.To.Target().Pc - p.Pc) >> 1)
3960 }
3961
3962
3963 r1, i2 := p.From.Reg, p.RestArgs[0].Offset
3964 if p.From.Type == obj.TYPE_CONST {
3965 r1 = p.Reg
3966 }
3967 m3 := uint32(c.branchMask(p))
3968
3969 var opcode uint32
3970 switch p.As {
3971 case ACIJ:
3972 opcode = op_CIJ
3973 case ACGIJ, ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE:
3974 opcode = op_CGIJ
3975 case ACLIJ:
3976 opcode = op_CLIJ
3977 case ACLGIJ, ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE:
3978 opcode = op_CLGIJ
3979 }
3980 if int32(int16(v)) != v {
3981
3982
3983
3984
3985
3986
3987
3988
3989 m3 ^= 0xe
3990 zRIE(_c, opcode, uint32(r1), m3, uint32(sizeRIE+sizeRIL)/2, 0, 0, 0, uint32(i2), asm)
3991 zRIL(_c, op_BRCL, uint32(Always), uint32(v-sizeRIE/2), asm)
3992 } else {
3993 zRIE(_c, opcode, uint32(r1), m3, uint32(v), 0, 0, 0, uint32(i2), asm)
3994 }
3995
3996 case 91:
3997 var opcode uint32
3998 switch p.As {
3999 case ATMHH:
4000 opcode = op_TMHH
4001 case ATMHL:
4002 opcode = op_TMHL
4003 case ATMLH:
4004 opcode = op_TMLH
4005 case ATMLL:
4006 opcode = op_TMLL
4007 }
4008 zRI(opcode, uint32(p.From.Reg), uint32(c.vregoff(&p.To)), asm)
4009
4010 case 92:
4011 zRRE(op_IPM, uint32(p.From.Reg), 0, asm)
4012
4013 case 93:
4014 v := c.vregoff(&p.To)
4015 if v != 0 {
4016 c.ctxt.Diag("invalid offset against GOT slot %v", p)
4017 }
4018 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm)
4019 c.cursym.AddRel(c.ctxt, obj.Reloc{
4020 Type: objabi.R_GOTPCREL,
4021 Off: int32(c.pc + 2),
4022 Siz: 4,
4023 Sym: p.From.Sym,
4024 Add: 2 + 4,
4025 })
4026
4027 case 94:
4028 zRIL(_b, op_LARL, regtmp(p), (sizeRIL+sizeRXY+sizeRI)>>1, asm)
4029 zRXY(op_LG, uint32(p.To.Reg), regtmp(p), 0, 0, asm)
4030 zRI(op_BRC, 0xF, (sizeRI+8)>>1, asm)
4031 *asm = append(*asm, 0, 0, 0, 0, 0, 0, 0, 0)
4032 c.cursym.AddRel(c.ctxt, obj.Reloc{
4033 Type: objabi.R_TLS_LE,
4034 Off: int32(c.pc + sizeRIL + sizeRXY + sizeRI),
4035 Siz: 8,
4036 Sym: p.From.Sym,
4037 })
4038
4039 case 95:
4040
4041
4042
4043
4044
4045
4046
4047
4048
4049
4050
4051 zRIL(_b, op_LARL, regtmp(p), 0, asm)
4052 c.cursym.AddRel(c.ctxt, obj.Reloc{
4053 Type: objabi.R_TLS_IE,
4054 Off: int32(c.pc + 2),
4055 Siz: 4,
4056 Sym: p.From.Sym,
4057 Add: 2 + 4,
4058 })
4059
4060
4061 zRXY(op_LGF, uint32(p.To.Reg), regtmp(p), 0, 0, asm)
4062
4063
4064
4065 case 96:
4066 length := c.vregoff(&p.From)
4067 offset := c.vregoff(&p.To)
4068 reg := p.To.Reg
4069 if reg == 0 {
4070 reg = REGSP
4071 }
4072 if length <= 0 {
4073 c.ctxt.Diag("cannot CLEAR %d bytes, must be greater than 0", length)
4074 }
4075 for length > 0 {
4076 if offset < 0 || offset >= DISP12 {
4077 if offset >= -DISP20/2 && offset < DISP20/2 {
4078 zRXY(op_LAY, regtmp(p), uint32(reg), 0, uint32(offset), asm)
4079 } else {
4080 if reg != int16(regtmp(p)) {
4081 zRRE(op_LGR, regtmp(p), uint32(reg), asm)
4082 }
4083 zRIL(_a, op_AGFI, regtmp(p), uint32(offset), asm)
4084 }
4085 reg = int16(regtmp(p))
4086 offset = 0
4087 }
4088 size := length
4089 if size > 256 {
4090 size = 256
4091 }
4092
4093 switch size {
4094 case 1:
4095 zSI(op_MVI, 0, uint32(reg), uint32(offset), asm)
4096 case 2:
4097 zSIL(op_MVHHI, uint32(reg), uint32(offset), 0, asm)
4098 case 4:
4099 zSIL(op_MVHI, uint32(reg), uint32(offset), 0, asm)
4100 case 8:
4101 zSIL(op_MVGHI, uint32(reg), uint32(offset), 0, asm)
4102 default:
4103 zSS(_a, op_XC, uint32(size-1), 0, uint32(reg), uint32(offset), uint32(reg), uint32(offset), asm)
4104 }
4105
4106 length -= size
4107 offset += size
4108 }
4109
4110 case 97:
4111 rstart := p.From.Reg
4112 rend := p.Reg
4113 offset := c.regoff(&p.To)
4114 reg := p.To.Reg
4115 if reg == 0 {
4116 reg = REGSP
4117 }
4118 if offset < -DISP20/2 || offset >= DISP20/2 {
4119 if reg != int16(regtmp(p)) {
4120 zRRE(op_LGR, regtmp(p), uint32(reg), asm)
4121 }
4122 zRIL(_a, op_AGFI, regtmp(p), uint32(offset), asm)
4123 reg = int16(regtmp(p))
4124 offset = 0
4125 }
4126 switch p.As {
4127 case ASTMY:
4128 if offset >= 0 && offset < DISP12 {
4129 zRS(op_STM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
4130 } else {
4131 zRSY(op_STMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
4132 }
4133 case ASTMG:
4134 zRSY(op_STMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
4135 }
4136
4137 case 98:
4138 rstart := p.Reg
4139 rend := p.To.Reg
4140 offset := c.regoff(&p.From)
4141 reg := p.From.Reg
4142 if reg == 0 {
4143 reg = REGSP
4144 }
4145 if offset < -DISP20/2 || offset >= DISP20/2 {
4146 if reg != int16(regtmp(p)) {
4147 zRRE(op_LGR, regtmp(p), uint32(reg), asm)
4148 }
4149 zRIL(_a, op_AGFI, regtmp(p), uint32(offset), asm)
4150 reg = int16(regtmp(p))
4151 offset = 0
4152 }
4153 switch p.As {
4154 case ALMY:
4155 if offset >= 0 && offset < DISP12 {
4156 zRS(op_LM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
4157 } else {
4158 zRSY(op_LMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
4159 }
4160 case ALMG:
4161 zRSY(op_LMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
4162 }
4163
4164 case 99:
4165 if p.To.Index != 0 {
4166 c.ctxt.Diag("cannot use indexed address")
4167 }
4168 offset := c.regoff(&p.To)
4169 if offset < -DISP20/2 || offset >= DISP20/2 {
4170 c.ctxt.Diag("%v does not fit into 20-bit signed integer", offset)
4171 }
4172 var opcode uint32
4173 switch p.As {
4174 case ALAA:
4175 opcode = op_LAA
4176 case ALAAG:
4177 opcode = op_LAAG
4178 case ALAAL:
4179 opcode = op_LAAL
4180 case ALAALG:
4181 opcode = op_LAALG
4182 case ALAN:
4183 opcode = op_LAN
4184 case ALANG:
4185 opcode = op_LANG
4186 case ALAX:
4187 opcode = op_LAX
4188 case ALAXG:
4189 opcode = op_LAXG
4190 case ALAO:
4191 opcode = op_LAO
4192 case ALAOG:
4193 opcode = op_LAOG
4194 }
4195 zRSY(opcode, uint32(p.Reg), uint32(p.From.Reg), uint32(p.To.Reg), uint32(offset), asm)
4196
4197 case 100:
4198 op, m3, _ := vop(p.As)
4199 v1 := p.From.Reg
4200 if p.Reg != 0 {
4201 m3 = uint32(c.vregoff(&p.From))
4202 v1 = p.Reg
4203 }
4204 b2 := p.To.Reg
4205 if b2 == 0 {
4206 b2 = REGSP
4207 }
4208 d2 := uint32(c.vregoff(&p.To))
4209 zVRX(op, uint32(v1), uint32(p.To.Index), uint32(b2), d2, m3, asm)
4210
4211 case 101:
4212 op, m3, _ := vop(p.As)
4213 src := &p.From
4214 if p.GetFrom3() != nil {
4215 m3 = uint32(c.vregoff(&p.From))
4216 src = p.GetFrom3()
4217 }
4218 b2 := src.Reg
4219 if b2 == 0 {
4220 b2 = REGSP
4221 }
4222 d2 := uint32(c.vregoff(src))
4223 zVRX(op, uint32(p.To.Reg), uint32(src.Index), uint32(b2), d2, m3, asm)
4224
4225 case 102:
4226 op, _, _ := vop(p.As)
4227 m3 := uint32(c.vregoff(&p.From))
4228 b2 := p.To.Reg
4229 if b2 == 0 {
4230 b2 = REGSP
4231 }
4232 d2 := uint32(c.vregoff(&p.To))
4233 zVRV(op, uint32(p.Reg), uint32(p.To.Index), uint32(b2), d2, m3, asm)
4234
4235 case 103:
4236 op, _, _ := vop(p.As)
4237 m3 := uint32(c.vregoff(&p.From))
4238 b2 := p.GetFrom3().Reg
4239 if b2 == 0 {
4240 b2 = REGSP
4241 }
4242 d2 := uint32(c.vregoff(p.GetFrom3()))
4243 zVRV(op, uint32(p.To.Reg), uint32(p.GetFrom3().Index), uint32(b2), d2, m3, asm)
4244
4245 case 104:
4246 op, m4, _ := vop(p.As)
4247 fr := p.Reg
4248 if fr == 0 {
4249 fr = p.To.Reg
4250 }
4251 bits := uint32(c.vregoff(&p.From))
4252 zVRS(op, uint32(p.To.Reg), uint32(fr), uint32(p.From.Reg), bits, m4, asm)
4253
4254 case 105:
4255 op, _, _ := vop(p.As)
4256 offset := uint32(c.vregoff(&p.To))
4257 reg := p.To.Reg
4258 if reg == 0 {
4259 reg = REGSP
4260 }
4261 zVRS(op, uint32(p.From.Reg), uint32(p.Reg), uint32(reg), offset, 0, asm)
4262
4263 case 106:
4264 op, _, _ := vop(p.As)
4265 offset := uint32(c.vregoff(&p.From))
4266 reg := p.From.Reg
4267 if reg == 0 {
4268 reg = REGSP
4269 }
4270 zVRS(op, uint32(p.Reg), uint32(p.To.Reg), uint32(reg), offset, 0, asm)
4271
4272 case 107:
4273 op, _, _ := vop(p.As)
4274 offset := uint32(c.vregoff(&p.To))
4275 reg := p.To.Reg
4276 if reg == 0 {
4277 reg = REGSP
4278 }
4279 zVRS(op, uint32(p.Reg), uint32(p.From.Reg), uint32(reg), offset, 0, asm)
4280
4281 case 108:
4282 op, _, _ := vop(p.As)
4283 offset := uint32(c.vregoff(p.GetFrom3()))
4284 reg := p.GetFrom3().Reg
4285 if reg == 0 {
4286 reg = REGSP
4287 }
4288 zVRS(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(reg), offset, 0, asm)
4289
4290 case 109:
4291 op, m3, _ := vop(p.As)
4292 i2 := uint32(c.vregoff(&p.From))
4293 if p.GetFrom3() != nil {
4294 m3 = uint32(c.vregoff(&p.From))
4295 i2 = uint32(c.vregoff(p.GetFrom3()))
4296 }
4297 switch p.As {
4298 case AVZERO:
4299 i2 = 0
4300 case AVONE:
4301 i2 = 0xffff
4302 }
4303 zVRIa(op, uint32(p.To.Reg), i2, m3, asm)
4304
4305 case 110:
4306 op, m4, _ := vop(p.As)
4307 i2 := uint32(c.vregoff(&p.From))
4308 i3 := uint32(c.vregoff(p.GetFrom3()))
4309 zVRIb(op, uint32(p.To.Reg), i2, i3, m4, asm)
4310
4311 case 111:
4312 op, m4, _ := vop(p.As)
4313 i2 := uint32(c.vregoff(&p.From))
4314 zVRIc(op, uint32(p.To.Reg), uint32(p.Reg), i2, m4, asm)
4315
4316 case 112:
4317 op, m5, _ := vop(p.As)
4318 i4 := uint32(c.vregoff(&p.From))
4319 zVRId(op, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), i4, m5, asm)
4320
4321 case 113:
4322 op, m4, _ := vop(p.As)
4323 m5 := singleElementMask(p.As)
4324 i3 := uint32(c.vregoff(&p.From))
4325 zVRIe(op, uint32(p.To.Reg), uint32(p.Reg), i3, m5, m4, asm)
4326
4327 case 114:
4328 op, m3, m5 := vop(p.As)
4329 m4 := singleElementMask(p.As)
4330 zVRRa(op, uint32(p.To.Reg), uint32(p.From.Reg), m5, m4, m3, asm)
4331
4332 case 115:
4333 op, m3, m5 := vop(p.As)
4334 m4 := singleElementMask(p.As)
4335 zVRRa(op, uint32(p.From.Reg), uint32(p.To.Reg), m5, m4, m3, asm)
4336
4337 case 117:
4338 op, m4, m5 := vop(p.As)
4339 zVRRb(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), m5, m4, asm)
4340
4341 case 118:
4342 op, m4, m6 := vop(p.As)
4343 m5 := singleElementMask(p.As)
4344 v3 := p.Reg
4345 if v3 == 0 {
4346 v3 = p.To.Reg
4347 }
4348 zVRRc(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(v3), m6, m5, m4, asm)
4349
4350 case 119:
4351 op, m4, m6 := vop(p.As)
4352 m5 := singleElementMask(p.As)
4353 v2 := p.Reg
4354 if v2 == 0 {
4355 v2 = p.To.Reg
4356 }
4357 zVRRc(op, uint32(p.To.Reg), uint32(v2), uint32(p.From.Reg), m6, m5, m4, asm)
4358
4359 case 120:
4360 op, m6, m5 := vop(p.As)
4361 v1 := uint32(p.To.Reg)
4362 v2 := uint32(p.From.Reg)
4363 v3 := uint32(p.Reg)
4364 v4 := uint32(p.GetFrom3().Reg)
4365 zVRRd(op, v1, v2, v3, m6, m5, v4, asm)
4366
4367 case 121:
4368 op, m6, _ := vop(p.As)
4369 m5 := singleElementMask(p.As)
4370 v1 := uint32(p.To.Reg)
4371 v2 := uint32(p.From.Reg)
4372 v3 := uint32(p.Reg)
4373 v4 := uint32(p.GetFrom3().Reg)
4374 zVRRe(op, v1, v2, v3, m6, m5, v4, asm)
4375
4376 case 122:
4377 op, _, _ := vop(p.As)
4378 zVRRf(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm)
4379
4380 case 123:
4381 op, _, _ := vop(p.As)
4382 m4 := c.regoff(&p.From)
4383 zVRRc(op, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), 0, 0, uint32(m4), asm)
4384
4385 case 124:
4386 var opcode uint32
4387 switch p.As {
4388 default:
4389 c.ctxt.Diag("unexpected opcode %v", p.As)
4390 case AKM, AKMC, AKLMD:
4391 if p.From.Reg == REG_R0 {
4392 c.ctxt.Diag("input must not be R0 in %v", p)
4393 }
4394 if p.From.Reg&1 != 0 {
4395 c.ctxt.Diag("input must be even register in %v", p)
4396 }
4397 if p.To.Reg == REG_R0 {
4398 c.ctxt.Diag("second argument must not be R0 in %v", p)
4399 }
4400 if p.To.Reg&1 != 0 {
4401 c.ctxt.Diag("second argument must be even register in %v", p)
4402 }
4403 if p.As == AKM {
4404 opcode = op_KM
4405 } else if p.As == AKMC {
4406 opcode = op_KMC
4407 } else {
4408 opcode = op_KLMD
4409 }
4410 case AKIMD:
4411 if p.To.Reg == REG_R0 {
4412 c.ctxt.Diag("second argument must not be R0 in %v", p)
4413 }
4414 if p.To.Reg&1 != 0 {
4415 c.ctxt.Diag("second argument must be even register in %v", p)
4416 }
4417 opcode = op_KIMD
4418 }
4419 zRRE(opcode, uint32(p.From.Reg), uint32(p.To.Reg), asm)
4420
4421 case 125:
4422 if p.To.Reg == REG_R0 {
4423 c.ctxt.Diag("second argument must not be R0 in %v", p)
4424 }
4425 if p.To.Reg&1 != 0 {
4426 c.ctxt.Diag("second argument must be an even register in %v", p)
4427 }
4428 zRRE(op_KDSA, uint32(p.From.Reg), uint32(p.To.Reg), asm)
4429
4430 case 126:
4431 var opcode uint32
4432 switch p.As {
4433 default:
4434 c.ctxt.Diag("unexpected opcode %v", p.As)
4435 case AKMA, AKMCTR:
4436 if p.From.Reg == REG_R0 {
4437 c.ctxt.Diag("input argument must not be R0 in %v", p)
4438 }
4439 if p.From.Reg&1 != 0 {
4440 c.ctxt.Diag("input argument must be even register in %v", p)
4441 }
4442 if p.To.Reg == REG_R0 {
4443 c.ctxt.Diag("output argument must not be R0 in %v", p)
4444 }
4445 if p.To.Reg&1 != 0 {
4446 c.ctxt.Diag("output argument must be an even register in %v", p)
4447 }
4448 if p.Reg == REG_R0 {
4449 c.ctxt.Diag("third argument must not be R0 in %v", p)
4450 }
4451 if p.Reg&1 != 0 {
4452 c.ctxt.Diag("third argument must be even register in %v", p)
4453 }
4454 if p.As == AKMA {
4455 opcode = op_KMA
4456 } else if p.As == AKMCTR {
4457 opcode = op_KMCTR
4458 }
4459 }
4460 zRRF(opcode, uint32(p.Reg), 0, uint32(p.From.Reg), uint32(p.To.Reg), asm)
4461
4462 case 127:
4463
4464
4465
4466
4467
4468 d2 := c.regoff(&p.From)
4469 if p.To.Reg&1 != 0 {
4470 c.ctxt.Diag("output argument must be even register in %v", p)
4471 }
4472 if p.Reg&1 != 0 {
4473 c.ctxt.Diag("input argument must be an even register in %v", p)
4474 }
4475 if (p.From.Reg == p.To.Reg) || (p.From.Reg == p.Reg) {
4476 c.ctxt.Diag("padding byte register cannot be same as input or output register %v", p)
4477 }
4478 zRS(op_MVCLE, uint32(p.To.Reg), uint32(p.Reg), uint32(p.From.Reg), uint32(d2), asm)
4479
4480 case 128:
4481 op, m4, _ := vop(p.As)
4482 m5 := singleElementMask(p.As)
4483 m6 := uint32(c.vregoff(&p.From))
4484 zVRRc(op, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), m6, m5, m4, asm)
4485 }
4486 }
4487
4488 func (c *ctxtz) vregoff(a *obj.Addr) int64 {
4489 c.instoffset = 0
4490 if a != nil {
4491 c.aclass(a)
4492 }
4493 return c.instoffset
4494 }
4495
4496 func (c *ctxtz) regoff(a *obj.Addr) int32 {
4497 return int32(c.vregoff(a))
4498 }
4499
4500
4501 func isU12(displacement int32) bool {
4502 return displacement >= 0 && displacement < DISP12
4503 }
4504
4505
4506 func (c *ctxtz) zopload12(a obj.As) (uint32, bool) {
4507 switch a {
4508 case AFMOVD:
4509 return op_LD, true
4510 case AFMOVS:
4511 return op_LE, true
4512 }
4513 return 0, false
4514 }
4515
4516
4517 func (c *ctxtz) zopload(a obj.As) uint32 {
4518 switch a {
4519
4520 case AMOVD:
4521 return op_LG
4522 case AMOVW:
4523 return op_LGF
4524 case AMOVWZ:
4525 return op_LLGF
4526 case AMOVH:
4527 return op_LGH
4528 case AMOVHZ:
4529 return op_LLGH
4530 case AMOVB:
4531 return op_LGB
4532 case AMOVBZ:
4533 return op_LLGC
4534
4535
4536 case AFMOVD:
4537 return op_LDY
4538 case AFMOVS:
4539 return op_LEY
4540
4541
4542 case AMOVDBR:
4543 return op_LRVG
4544 case AMOVWBR:
4545 return op_LRV
4546 case AMOVHBR:
4547 return op_LRVH
4548 }
4549
4550 c.ctxt.Diag("unknown store opcode %v", a)
4551 return 0
4552 }
4553
4554
4555 func (c *ctxtz) zopstore12(a obj.As) (uint32, bool) {
4556 switch a {
4557 case AFMOVD:
4558 return op_STD, true
4559 case AFMOVS:
4560 return op_STE, true
4561 case AMOVW, AMOVWZ:
4562 return op_ST, true
4563 case AMOVH, AMOVHZ:
4564 return op_STH, true
4565 case AMOVB, AMOVBZ:
4566 return op_STC, true
4567 }
4568 return 0, false
4569 }
4570
4571
4572 func (c *ctxtz) zopstore(a obj.As) uint32 {
4573 switch a {
4574
4575 case AMOVD:
4576 return op_STG
4577 case AMOVW, AMOVWZ:
4578 return op_STY
4579 case AMOVH, AMOVHZ:
4580 return op_STHY
4581 case AMOVB, AMOVBZ:
4582 return op_STCY
4583
4584
4585 case AFMOVD:
4586 return op_STDY
4587 case AFMOVS:
4588 return op_STEY
4589
4590
4591 case AMOVDBR:
4592 return op_STRVG
4593 case AMOVWBR:
4594 return op_STRV
4595 case AMOVHBR:
4596 return op_STRVH
4597 }
4598
4599 c.ctxt.Diag("unknown store opcode %v", a)
4600 return 0
4601 }
4602
4603
4604 func (c *ctxtz) zoprre(a obj.As) uint32 {
4605 switch a {
4606 case ACMP:
4607 return op_CGR
4608 case ACMPU:
4609 return op_CLGR
4610 case AFCMPO:
4611 return op_KDBR
4612 case AFCMPU:
4613 return op_CDBR
4614 case ACEBR:
4615 return op_CEBR
4616 }
4617 c.ctxt.Diag("unknown rre opcode %v", a)
4618 return 0
4619 }
4620
4621
4622 func (c *ctxtz) zoprr(a obj.As) uint32 {
4623 switch a {
4624 case ACMPW:
4625 return op_CR
4626 case ACMPWU:
4627 return op_CLR
4628 }
4629 c.ctxt.Diag("unknown rr opcode %v", a)
4630 return 0
4631 }
4632
4633
4634 func (c *ctxtz) zopril(a obj.As) uint32 {
4635 switch a {
4636 case ACMP:
4637 return op_CGFI
4638 case ACMPU:
4639 return op_CLGFI
4640 case ACMPW:
4641 return op_CFI
4642 case ACMPWU:
4643 return op_CLFI
4644 }
4645 c.ctxt.Diag("unknown ril opcode %v", a)
4646 return 0
4647 }
4648
4649
4650 const (
4651 sizeE = 2
4652 sizeI = 2
4653 sizeIE = 4
4654 sizeMII = 6
4655 sizeRI = 4
4656 sizeRI1 = 4
4657 sizeRI2 = 4
4658 sizeRI3 = 4
4659 sizeRIE = 6
4660 sizeRIE1 = 6
4661 sizeRIE2 = 6
4662 sizeRIE3 = 6
4663 sizeRIE4 = 6
4664 sizeRIE5 = 6
4665 sizeRIE6 = 6
4666 sizeRIL = 6
4667 sizeRIL1 = 6
4668 sizeRIL2 = 6
4669 sizeRIL3 = 6
4670 sizeRIS = 6
4671 sizeRR = 2
4672 sizeRRD = 4
4673 sizeRRE = 4
4674 sizeRRF = 4
4675 sizeRRF1 = 4
4676 sizeRRF2 = 4
4677 sizeRRF3 = 4
4678 sizeRRF4 = 4
4679 sizeRRF5 = 4
4680 sizeRRR = 2
4681 sizeRRS = 6
4682 sizeRS = 4
4683 sizeRS1 = 4
4684 sizeRS2 = 4
4685 sizeRSI = 4
4686 sizeRSL = 6
4687 sizeRSY = 6
4688 sizeRSY1 = 6
4689 sizeRSY2 = 6
4690 sizeRX = 4
4691 sizeRX1 = 4
4692 sizeRX2 = 4
4693 sizeRXE = 6
4694 sizeRXF = 6
4695 sizeRXY = 6
4696 sizeRXY1 = 6
4697 sizeRXY2 = 6
4698 sizeS = 4
4699 sizeSI = 4
4700 sizeSIL = 6
4701 sizeSIY = 6
4702 sizeSMI = 6
4703 sizeSS = 6
4704 sizeSS1 = 6
4705 sizeSS2 = 6
4706 sizeSS3 = 6
4707 sizeSS4 = 6
4708 sizeSS5 = 6
4709 sizeSS6 = 6
4710 sizeSSE = 6
4711 sizeSSF = 6
4712 )
4713
4714
4715 type form int
4716
4717 const (
4718 _a form = iota
4719 _b
4720 _c
4721 _d
4722 _e
4723 _f
4724 )
4725
4726 func zE(op uint32, asm *[]byte) {
4727 *asm = append(*asm, uint8(op>>8), uint8(op))
4728 }
4729
4730 func zI(op, i1 uint32, asm *[]byte) {
4731 *asm = append(*asm, uint8(op>>8), uint8(i1))
4732 }
4733
4734 func zRI(op, r1_m1, i2_ri2 uint32, asm *[]byte) {
4735 *asm = append(*asm,
4736 uint8(op>>8),
4737 (uint8(r1_m1)<<4)|(uint8(op)&0x0F),
4738 uint8(i2_ri2>>8),
4739 uint8(i2_ri2))
4740 }
4741
4742
4743
4744
4745
4746
4747
4748
4749
4750
4751
4752
4753 func zRIE(f form, op, r1, r2_m3_r3, i2_ri4_ri2, i3, i4, m3, i2_i5 uint32, asm *[]byte) {
4754 *asm = append(*asm, uint8(op>>8), uint8(r1)<<4|uint8(r2_m3_r3&0x0F))
4755
4756 switch f {
4757 default:
4758 *asm = append(*asm, uint8(i2_ri4_ri2>>8), uint8(i2_ri4_ri2))
4759 case _f:
4760 *asm = append(*asm, uint8(i3), uint8(i4))
4761 }
4762
4763 switch f {
4764 case _a, _b:
4765 *asm = append(*asm, uint8(m3)<<4)
4766 default:
4767 *asm = append(*asm, uint8(i2_i5))
4768 }
4769
4770 *asm = append(*asm, uint8(op))
4771 }
4772
4773 func zRIL(f form, op, r1_m1, i2_ri2 uint32, asm *[]byte) {
4774 if f == _a || f == _b {
4775 r1_m1 = r1_m1 - obj.RBaseS390X
4776 }
4777 *asm = append(*asm,
4778 uint8(op>>8),
4779 (uint8(r1_m1)<<4)|(uint8(op)&0x0F),
4780 uint8(i2_ri2>>24),
4781 uint8(i2_ri2>>16),
4782 uint8(i2_ri2>>8),
4783 uint8(i2_ri2))
4784 }
4785
4786 func zRR(op, r1, r2 uint32, asm *[]byte) {
4787 *asm = append(*asm, uint8(op>>8), (uint8(r1)<<4)|uint8(r2&0x0F))
4788 }
4789
4790 func zRRD(op, r1, r3, r2 uint32, asm *[]byte) {
4791 *asm = append(*asm,
4792 uint8(op>>8),
4793 uint8(op),
4794 uint8(r1)<<4,
4795 (uint8(r3)<<4)|uint8(r2&0x0F))
4796 }
4797
4798 func zRRE(op, r1, r2 uint32, asm *[]byte) {
4799 *asm = append(*asm,
4800 uint8(op>>8),
4801 uint8(op),
4802 0,
4803 (uint8(r1)<<4)|uint8(r2&0x0F))
4804 }
4805
4806 func zRRF(op, r3_m3, m4, r1, r2 uint32, asm *[]byte) {
4807 *asm = append(*asm,
4808 uint8(op>>8),
4809 uint8(op),
4810 (uint8(r3_m3)<<4)|uint8(m4&0x0F),
4811 (uint8(r1)<<4)|uint8(r2&0x0F))
4812 }
4813
4814 func zRS(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) {
4815 *asm = append(*asm,
4816 uint8(op>>8),
4817 (uint8(r1)<<4)|uint8(r3_m3&0x0F),
4818 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4819 uint8(d2))
4820 }
4821
4822 func zRSY(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) {
4823 dl2 := uint16(d2) & 0x0FFF
4824 *asm = append(*asm,
4825 uint8(op>>8),
4826 (uint8(r1)<<4)|uint8(r3_m3&0x0F),
4827 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F),
4828 uint8(dl2),
4829 uint8(d2>>12),
4830 uint8(op))
4831 }
4832
4833 func zRX(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) {
4834 *asm = append(*asm,
4835 uint8(op>>8),
4836 (uint8(r1_m1)<<4)|uint8(x2&0x0F),
4837 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4838 uint8(d2))
4839 }
4840
4841 func zRXE(op, r1, x2, b2, d2, m3 uint32, asm *[]byte) {
4842 *asm = append(*asm,
4843 uint8(op>>8),
4844 (uint8(r1)<<4)|uint8(x2&0x0F),
4845 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4846 uint8(d2),
4847 uint8(m3)<<4,
4848 uint8(op))
4849 }
4850
4851 func zRXY(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) {
4852 dl2 := uint16(d2) & 0x0FFF
4853 *asm = append(*asm,
4854 uint8(op>>8),
4855 (uint8(r1_m1)<<4)|uint8(x2&0x0F),
4856 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F),
4857 uint8(dl2),
4858 uint8(d2>>12),
4859 uint8(op))
4860 }
4861
4862 func zS(op, b2, d2 uint32, asm *[]byte) {
4863 *asm = append(*asm,
4864 uint8(op>>8),
4865 uint8(op),
4866 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4867 uint8(d2))
4868 }
4869
4870 func zSI(op, i2, b1, d1 uint32, asm *[]byte) {
4871 *asm = append(*asm,
4872 uint8(op>>8),
4873 uint8(i2),
4874 (uint8(b1)<<4)|uint8((d1>>8)&0x0F),
4875 uint8(d1))
4876 }
4877
4878 func zSIL(op, b1, d1, i2 uint32, asm *[]byte) {
4879 *asm = append(*asm,
4880 uint8(op>>8),
4881 uint8(op),
4882 (uint8(b1)<<4)|uint8((d1>>8)&0x0F),
4883 uint8(d1),
4884 uint8(i2>>8),
4885 uint8(i2))
4886 }
4887
4888 func zSIY(op, i2, b1, d1 uint32, asm *[]byte) {
4889 dl1 := uint16(d1) & 0x0FFF
4890 *asm = append(*asm,
4891 uint8(op>>8),
4892 uint8(i2),
4893 (uint8(b1)<<4)|(uint8(dl1>>8)&0x0F),
4894 uint8(dl1),
4895 uint8(d1>>12),
4896 uint8(op))
4897 }
4898
4899
4900
4901
4902
4903
4904
4905
4906
4907
4908
4909 func zSS(f form, op, l1_r1, l2_i3_r3, b1_b2, d1_d2, b2_b4, d2_d4 uint32, asm *[]byte) {
4910 *asm = append(*asm, uint8(op>>8))
4911
4912 switch f {
4913 case _a:
4914 *asm = append(*asm, uint8(l1_r1))
4915 case _b, _c, _d, _e:
4916 *asm = append(*asm, (uint8(l1_r1)<<4)|uint8(l2_i3_r3&0x0F))
4917 case _f:
4918 *asm = append(*asm, uint8(l2_i3_r3))
4919 }
4920
4921 *asm = append(*asm,
4922 (uint8(b1_b2)<<4)|uint8((d1_d2>>8)&0x0F),
4923 uint8(d1_d2),
4924 (uint8(b2_b4)<<4)|uint8((d2_d4>>8)&0x0F),
4925 uint8(d2_d4))
4926 }
4927
4928 func rxb(va, vb, vc, vd uint32) uint8 {
4929 mask := uint8(0)
4930 if va >= REG_V16 && va <= REG_V31 {
4931 mask |= 0x8
4932 }
4933 if vb >= REG_V16 && vb <= REG_V31 {
4934 mask |= 0x4
4935 }
4936 if vc >= REG_V16 && vc <= REG_V31 {
4937 mask |= 0x2
4938 }
4939 if vd >= REG_V16 && vd <= REG_V31 {
4940 mask |= 0x1
4941 }
4942 return mask
4943 }
4944
4945 func zVRX(op, v1, x2, b2, d2, m3 uint32, asm *[]byte) {
4946 *asm = append(*asm,
4947 uint8(op>>8),
4948 (uint8(v1)<<4)|(uint8(x2)&0xf),
4949 (uint8(b2)<<4)|(uint8(d2>>8)&0xf),
4950 uint8(d2),
4951 (uint8(m3)<<4)|rxb(v1, 0, 0, 0),
4952 uint8(op))
4953 }
4954
4955 func zVRV(op, v1, v2, b2, d2, m3 uint32, asm *[]byte) {
4956 *asm = append(*asm,
4957 uint8(op>>8),
4958 (uint8(v1)<<4)|(uint8(v2)&0xf),
4959 (uint8(b2)<<4)|(uint8(d2>>8)&0xf),
4960 uint8(d2),
4961 (uint8(m3)<<4)|rxb(v1, v2, 0, 0),
4962 uint8(op))
4963 }
4964
4965 func zVRS(op, v1, v3_r3, b2, d2, m4 uint32, asm *[]byte) {
4966 *asm = append(*asm,
4967 uint8(op>>8),
4968 (uint8(v1)<<4)|(uint8(v3_r3)&0xf),
4969 (uint8(b2)<<4)|(uint8(d2>>8)&0xf),
4970 uint8(d2),
4971 (uint8(m4)<<4)|rxb(v1, v3_r3, 0, 0),
4972 uint8(op))
4973 }
4974
4975 func zVRRa(op, v1, v2, m5, m4, m3 uint32, asm *[]byte) {
4976 *asm = append(*asm,
4977 uint8(op>>8),
4978 (uint8(v1)<<4)|(uint8(v2)&0xf),
4979 0,
4980 (uint8(m5)<<4)|(uint8(m4)&0xf),
4981 (uint8(m3)<<4)|rxb(v1, v2, 0, 0),
4982 uint8(op))
4983 }
4984
4985 func zVRRb(op, v1, v2, v3, m5, m4 uint32, asm *[]byte) {
4986 *asm = append(*asm,
4987 uint8(op>>8),
4988 (uint8(v1)<<4)|(uint8(v2)&0xf),
4989 uint8(v3)<<4,
4990 uint8(m5)<<4,
4991 (uint8(m4)<<4)|rxb(v1, v2, v3, 0),
4992 uint8(op))
4993 }
4994
4995 func zVRRc(op, v1, v2, v3, m6, m5, m4 uint32, asm *[]byte) {
4996 *asm = append(*asm,
4997 uint8(op>>8),
4998 (uint8(v1)<<4)|(uint8(v2)&0xf),
4999 uint8(v3)<<4,
5000 (uint8(m6)<<4)|(uint8(m5)&0xf),
5001 (uint8(m4)<<4)|rxb(v1, v2, v3, 0),
5002 uint8(op))
5003 }
5004
5005 func zVRRd(op, v1, v2, v3, m5, m6, v4 uint32, asm *[]byte) {
5006 *asm = append(*asm,
5007 uint8(op>>8),
5008 (uint8(v1)<<4)|(uint8(v2)&0xf),
5009 (uint8(v3)<<4)|(uint8(m5)&0xf),
5010 uint8(m6)<<4,
5011 (uint8(v4)<<4)|rxb(v1, v2, v3, v4),
5012 uint8(op))
5013 }
5014
5015 func zVRRe(op, v1, v2, v3, m6, m5, v4 uint32, asm *[]byte) {
5016 *asm = append(*asm,
5017 uint8(op>>8),
5018 (uint8(v1)<<4)|(uint8(v2)&0xf),
5019 (uint8(v3)<<4)|(uint8(m6)&0xf),
5020 uint8(m5),
5021 (uint8(v4)<<4)|rxb(v1, v2, v3, v4),
5022 uint8(op))
5023 }
5024
5025 func zVRRf(op, v1, r2, r3 uint32, asm *[]byte) {
5026 *asm = append(*asm,
5027 uint8(op>>8),
5028 (uint8(v1)<<4)|(uint8(r2)&0xf),
5029 uint8(r3)<<4,
5030 0,
5031 rxb(v1, 0, 0, 0),
5032 uint8(op))
5033 }
5034
5035 func zVRIa(op, v1, i2, m3 uint32, asm *[]byte) {
5036 *asm = append(*asm,
5037 uint8(op>>8),
5038 uint8(v1)<<4,
5039 uint8(i2>>8),
5040 uint8(i2),
5041 (uint8(m3)<<4)|rxb(v1, 0, 0, 0),
5042 uint8(op))
5043 }
5044
5045 func zVRIb(op, v1, i2, i3, m4 uint32, asm *[]byte) {
5046 *asm = append(*asm,
5047 uint8(op>>8),
5048 uint8(v1)<<4,
5049 uint8(i2),
5050 uint8(i3),
5051 (uint8(m4)<<4)|rxb(v1, 0, 0, 0),
5052 uint8(op))
5053 }
5054
5055 func zVRIc(op, v1, v3, i2, m4 uint32, asm *[]byte) {
5056 *asm = append(*asm,
5057 uint8(op>>8),
5058 (uint8(v1)<<4)|(uint8(v3)&0xf),
5059 uint8(i2>>8),
5060 uint8(i2),
5061 (uint8(m4)<<4)|rxb(v1, v3, 0, 0),
5062 uint8(op))
5063 }
5064
5065 func zVRId(op, v1, v2, v3, i4, m5 uint32, asm *[]byte) {
5066 *asm = append(*asm,
5067 uint8(op>>8),
5068 (uint8(v1)<<4)|(uint8(v2)&0xf),
5069 uint8(v3)<<4,
5070 uint8(i4),
5071 (uint8(m5)<<4)|rxb(v1, v2, v3, 0),
5072 uint8(op))
5073 }
5074
5075 func zVRIe(op, v1, v2, i3, m5, m4 uint32, asm *[]byte) {
5076 *asm = append(*asm,
5077 uint8(op>>8),
5078 (uint8(v1)<<4)|(uint8(v2)&0xf),
5079 uint8(i3>>4),
5080 (uint8(i3)<<4)|(uint8(m5)&0xf),
5081 (uint8(m4)<<4)|rxb(v1, v2, 0, 0),
5082 uint8(op))
5083 }
5084
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