Source file src/cmd/internal/obj/ppc64/asm9.go

     1  // cmd/9l/optab.c, cmd/9l/asmout.c from Vita Nuova.
     2  //
     3  //	Copyright © 1994-1999 Lucent Technologies Inc.  All rights reserved.
     4  //	Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
     5  //	Portions Copyright © 1997-1999 Vita Nuova Limited
     6  //	Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com)
     7  //	Portions Copyright © 2004,2006 Bruce Ellis
     8  //	Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
     9  //	Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others
    10  //	Portions Copyright © 2009 The Go Authors. All rights reserved.
    11  //
    12  // Permission is hereby granted, free of charge, to any person obtaining a copy
    13  // of this software and associated documentation files (the "Software"), to deal
    14  // in the Software without restriction, including without limitation the rights
    15  // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    16  // copies of the Software, and to permit persons to whom the Software is
    17  // furnished to do so, subject to the following conditions:
    18  //
    19  // The above copyright notice and this permission notice shall be included in
    20  // all copies or substantial portions of the Software.
    21  //
    22  // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    23  // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    24  // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
    25  // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    26  // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    27  // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
    28  // THE SOFTWARE.
    29  
    30  package ppc64
    31  
    32  import (
    33  	"cmd/internal/obj"
    34  	"cmd/internal/objabi"
    35  	"encoding/binary"
    36  	"fmt"
    37  	"internal/buildcfg"
    38  	"log"
    39  	"math"
    40  	"math/bits"
    41  	"sort"
    42  )
    43  
    44  // ctxt9 holds state while assembling a single function.
    45  // Each function gets a fresh ctxt9.
    46  // This allows for multiple functions to be safely concurrently assembled.
    47  type ctxt9 struct {
    48  	ctxt       *obj.Link
    49  	newprog    obj.ProgAlloc
    50  	cursym     *obj.LSym
    51  	autosize   int32
    52  	instoffset int64
    53  	pc         int64
    54  }
    55  
    56  // Instruction layout.
    57  
    58  const (
    59  	r0iszero = 1
    60  )
    61  
    62  const (
    63  	// R bit option in prefixed load/store/add D-form operations
    64  	PFX_R_ABS   = 0 // Offset is absolute
    65  	PFX_R_PCREL = 1 // Offset is relative to PC, RA should be 0
    66  )
    67  
    68  const (
    69  	// The preferred hardware nop instruction.
    70  	NOP = 0x60000000
    71  )
    72  
    73  type Optab struct {
    74  	as    obj.As // Opcode
    75  	a1    uint8  // p.From argument (obj.Addr). p is of type obj.Prog.
    76  	a2    uint8  // p.Reg argument (int16 Register)
    77  	a3    uint8  // p.RestArgs[0]  (obj.AddrPos)
    78  	a4    uint8  // p.RestArgs[1]
    79  	a5    uint8  // p.RestARgs[2]
    80  	a6    uint8  // p.To (obj.Addr)
    81  	type_ int8   // cases in asmout below. E.g., 44 = st r,(ra+rb); 45 = ld (ra+rb), r
    82  	size  int8   // Text space in bytes to lay operation
    83  
    84  	// A prefixed instruction is generated by this opcode. This cannot be placed
    85  	// across a 64B PC address. Opcodes should not translate to more than one
    86  	// prefixed instruction. The prefixed instruction should be written first
    87  	// (e.g when Optab.size > 8).
    88  	ispfx bool
    89  
    90  	asmout func(*ctxt9, *obj.Prog, *Optab, *[5]uint32)
    91  }
    92  
    93  // optab contains an array to be sliced of accepted operand combinations for an
    94  // instruction. Unused arguments and fields are not explicitly enumerated, and
    95  // should not be listed for clarity. Unused arguments and values should always
    96  // assume the default value for the given type.
    97  //
    98  // optab does not list every valid ppc64 opcode, it enumerates representative
    99  // operand combinations for a class of instruction.  The variable oprange indexes
   100  // all valid ppc64 opcodes.
   101  //
   102  // oprange is initialized to point a slice within optab which contains the valid
   103  // operand combinations for a given instruction.  This is initialized from buildop.
   104  //
   105  // Likewise, each slice of optab is dynamically sorted using the ocmp Sort interface
   106  // to arrange entries to minimize text size of each opcode.
   107  //
   108  // optab is the sorted result of combining optabBase, optabGen, and prefixableOptab.
   109  var optab []Optab
   110  
   111  var optabBase = []Optab{
   112  	{as: obj.ATEXT, a1: C_LOREG, a6: C_TEXTSIZE, type_: 0, size: 0},
   113  	{as: obj.ATEXT, a1: C_LOREG, a3: C_32CON, a6: C_TEXTSIZE, type_: 0, size: 0},
   114  	{as: obj.ATEXT, a1: C_ADDR, a6: C_TEXTSIZE, type_: 0, size: 0},
   115  	{as: obj.ATEXT, a1: C_ADDR, a3: C_32CON, a6: C_TEXTSIZE, type_: 0, size: 0},
   116  	/* move register */
   117  	{as: AADD, a1: C_REG, a2: C_REG, a6: C_REG, type_: 2, size: 4},
   118  	{as: AADD, a1: C_REG, a6: C_REG, type_: 2, size: 4},
   119  	{as: AADD, a1: C_S16CON, a2: C_REG, a6: C_REG, type_: 4, size: 4},
   120  	{as: AADD, a1: C_S16CON, a6: C_REG, type_: 4, size: 4},
   121  	{as: AADD, a1: C_U16CON, a2: C_REG, a6: C_REG, type_: 22, size: 8},
   122  	{as: AADD, a1: C_U16CON, a6: C_REG, type_: 22, size: 8},
   123  	{as: AADDIS, a1: C_S16CON, a2: C_REG, a6: C_REG, type_: 20, size: 4},
   124  	{as: AADDIS, a1: C_S16CON, a6: C_REG, type_: 20, size: 4},
   125  	{as: AADDC, a1: C_REG, a2: C_REG, a6: C_REG, type_: 2, size: 4},
   126  	{as: AADDC, a1: C_REG, a6: C_REG, type_: 2, size: 4},
   127  	{as: AADDC, a1: C_S16CON, a2: C_REG, a6: C_REG, type_: 4, size: 4},
   128  	{as: AADDC, a1: C_S16CON, a6: C_REG, type_: 4, size: 4},
   129  	{as: AADDC, a1: C_32CON, a2: C_REG, a6: C_REG, type_: 22, size: 12},
   130  	{as: AADDC, a1: C_32CON, a6: C_REG, type_: 22, size: 12},
   131  	{as: AAND, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4}, /* logical, no literal */
   132  	{as: AAND, a1: C_REG, a6: C_REG, type_: 6, size: 4},
   133  	{as: AANDCC, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
   134  	{as: AANDCC, a1: C_REG, a6: C_REG, type_: 6, size: 4},
   135  	{as: AANDCC, a1: C_U16CON, a6: C_REG, type_: 58, size: 4},
   136  	{as: AANDCC, a1: C_U16CON, a2: C_REG, a6: C_REG, type_: 58, size: 4},
   137  	{as: AANDCC, a1: C_S16CON, a6: C_REG, type_: 23, size: 8},
   138  	{as: AANDCC, a1: C_S16CON, a2: C_REG, a6: C_REG, type_: 23, size: 8},
   139  	{as: AANDCC, a1: C_32CON, a6: C_REG, type_: 23, size: 12},
   140  	{as: AANDCC, a1: C_32CON, a2: C_REG, a6: C_REG, type_: 23, size: 12},
   141  	{as: AANDISCC, a1: C_U16CON, a6: C_REG, type_: 58, size: 4},
   142  	{as: AANDISCC, a1: C_U16CON, a2: C_REG, a6: C_REG, type_: 58, size: 4},
   143  	{as: AMULLW, a1: C_REG, a2: C_REG, a6: C_REG, type_: 2, size: 4},
   144  	{as: AMULLW, a1: C_REG, a6: C_REG, type_: 2, size: 4},
   145  	{as: AMULLW, a1: C_S16CON, a2: C_REG, a6: C_REG, type_: 4, size: 4},
   146  	{as: AMULLW, a1: C_S16CON, a6: C_REG, type_: 4, size: 4},
   147  	{as: AMULLW, a1: C_32CON, a2: C_REG, a6: C_REG, type_: 22, size: 12},
   148  	{as: AMULLW, a1: C_32CON, a6: C_REG, type_: 22, size: 12},
   149  	{as: ASUBC, a1: C_REG, a2: C_REG, a6: C_REG, type_: 10, size: 4},
   150  	{as: ASUBC, a1: C_REG, a6: C_REG, type_: 10, size: 4},
   151  	{as: ASUBC, a1: C_REG, a3: C_S16CON, a6: C_REG, type_: 27, size: 4},
   152  	{as: ASUBC, a1: C_REG, a3: C_32CON, a6: C_REG, type_: 28, size: 12},
   153  	{as: AOR, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4}, /* logical, literal not cc (or/xor) */
   154  	{as: AOR, a1: C_REG, a6: C_REG, type_: 6, size: 4},
   155  	{as: AOR, a1: C_U16CON, a6: C_REG, type_: 58, size: 4},
   156  	{as: AOR, a1: C_U16CON, a2: C_REG, a6: C_REG, type_: 58, size: 4},
   157  	{as: AOR, a1: C_S16CON, a6: C_REG, type_: 23, size: 8},
   158  	{as: AOR, a1: C_S16CON, a2: C_REG, a6: C_REG, type_: 23, size: 8},
   159  	{as: AOR, a1: C_U32CON, a2: C_REG, a6: C_REG, type_: 21, size: 8},
   160  	{as: AOR, a1: C_U32CON, a6: C_REG, type_: 21, size: 8},
   161  	{as: AOR, a1: C_32CON, a6: C_REG, type_: 23, size: 12},
   162  	{as: AOR, a1: C_32CON, a2: C_REG, a6: C_REG, type_: 23, size: 12},
   163  	{as: AORIS, a1: C_U16CON, a6: C_REG, type_: 58, size: 4},
   164  	{as: AORIS, a1: C_U16CON, a2: C_REG, a6: C_REG, type_: 58, size: 4},
   165  	{as: ADIVW, a1: C_REG, a2: C_REG, a6: C_REG, type_: 2, size: 4}, /* op r1[,r2],r3 */
   166  	{as: ADIVW, a1: C_REG, a6: C_REG, type_: 2, size: 4},
   167  	{as: ASUB, a1: C_REG, a2: C_REG, a6: C_REG, type_: 10, size: 4}, /* op r2[,r1],r3 */
   168  	{as: ASUB, a1: C_REG, a6: C_REG, type_: 10, size: 4},
   169  	{as: ASLW, a1: C_REG, a6: C_REG, type_: 6, size: 4},
   170  	{as: ASLW, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
   171  	{as: ASLD, a1: C_REG, a6: C_REG, type_: 6, size: 4},
   172  	{as: ASLD, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
   173  	{as: ASLD, a1: C_U15CON, a2: C_REG, a6: C_REG, type_: 25, size: 4},
   174  	{as: ASLD, a1: C_U15CON, a6: C_REG, type_: 25, size: 4},
   175  	{as: AEXTSWSLI, a1: C_U15CON, a6: C_REG, type_: 25, size: 4},
   176  	{as: AEXTSWSLI, a1: C_U15CON, a2: C_REG, a6: C_REG, type_: 25, size: 4},
   177  	{as: ASLW, a1: C_U15CON, a2: C_REG, a6: C_REG, type_: 57, size: 4},
   178  	{as: ASLW, a1: C_U15CON, a6: C_REG, type_: 57, size: 4},
   179  	{as: ASRAW, a1: C_REG, a6: C_REG, type_: 6, size: 4},
   180  	{as: ASRAW, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
   181  	{as: ASRAW, a1: C_U15CON, a2: C_REG, a6: C_REG, type_: 56, size: 4},
   182  	{as: ASRAW, a1: C_U15CON, a6: C_REG, type_: 56, size: 4},
   183  	{as: ASRAD, a1: C_REG, a6: C_REG, type_: 6, size: 4},
   184  	{as: ASRAD, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
   185  	{as: ASRAD, a1: C_U15CON, a2: C_REG, a6: C_REG, type_: 56, size: 4},
   186  	{as: ASRAD, a1: C_U15CON, a6: C_REG, type_: 56, size: 4},
   187  	{as: ARLWNM, a1: C_U15CON, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 63, size: 4},
   188  	{as: ARLWNM, a1: C_U15CON, a2: C_REG, a3: C_U15CON, a4: C_U15CON, a6: C_REG, type_: 63, size: 4},
   189  	{as: ARLWNM, a1: C_REG, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 63, size: 4},
   190  	{as: ARLWNM, a1: C_REG, a2: C_REG, a3: C_U15CON, a4: C_U15CON, a6: C_REG, type_: 63, size: 4},
   191  	{as: ACLRLSLWI, a1: C_U15CON, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 62, size: 4},
   192  	{as: ARLDMI, a1: C_U15CON, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 30, size: 4},
   193  	{as: ARLDC, a1: C_U15CON, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 29, size: 4},
   194  	{as: ARLDC, a1: C_REG, a3: C_U8CON, a4: C_U8CON, a6: C_REG, type_: 9, size: 4},
   195  	{as: ARLDCL, a1: C_U15CON, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 29, size: 4},
   196  	{as: ARLDCL, a1: C_REG, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 14, size: 4},
   197  	{as: ARLDICL, a1: C_REG, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 14, size: 4},
   198  	{as: ARLDICL, a1: C_U15CON, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 14, size: 4},
   199  	{as: ARLDCL, a1: C_REG, a3: C_32CON, a6: C_REG, type_: 14, size: 4},
   200  	{as: AFADD, a1: C_FREG, a6: C_FREG, type_: 2, size: 4},
   201  	{as: AFADD, a1: C_FREG, a2: C_FREG, a6: C_FREG, type_: 2, size: 4},
   202  	{as: ADADDQ, a1: C_FREGP, a6: C_FREGP, type_: 2, size: 4},
   203  	{as: ADADDQ, a1: C_FREGP, a2: C_FREGP, a6: C_FREGP, type_: 2, size: 4},
   204  	{as: AFABS, a1: C_FREG, a6: C_FREG, type_: 33, size: 4},
   205  	{as: AFABS, a6: C_FREG, type_: 33, size: 4},
   206  	{as: AFMADD, a1: C_FREG, a2: C_FREG, a3: C_FREG, a6: C_FREG, type_: 34, size: 4},
   207  	{as: AFMUL, a1: C_FREG, a6: C_FREG, type_: 32, size: 4},
   208  	{as: AFMUL, a1: C_FREG, a2: C_FREG, a6: C_FREG, type_: 32, size: 4},
   209  	{as: ADMULQ, a1: C_FREGP, a6: C_FREGP, type_: 32, size: 4},
   210  	{as: ADMULQ, a1: C_FREGP, a2: C_FREGP, a6: C_FREGP, type_: 32, size: 4},
   211  
   212  	{as: AMOVBU, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
   213  	{as: AMOVBU, a1: C_REG, a6: C_XOREG, type_: 108, size: 4},
   214  	{as: AMOVBU, a1: C_SOREG, a6: C_REG, type_: 8, size: 8},
   215  	{as: AMOVBU, a1: C_XOREG, a6: C_REG, type_: 109, size: 8},
   216  
   217  	{as: AMOVBZU, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
   218  	{as: AMOVBZU, a1: C_REG, a6: C_XOREG, type_: 108, size: 4},
   219  	{as: AMOVBZU, a1: C_SOREG, a6: C_REG, type_: 8, size: 4},
   220  	{as: AMOVBZU, a1: C_XOREG, a6: C_REG, type_: 109, size: 4},
   221  
   222  	{as: AMOVHBR, a1: C_REG, a6: C_XOREG, type_: 44, size: 4},
   223  	{as: AMOVHBR, a1: C_XOREG, a6: C_REG, type_: 45, size: 4},
   224  
   225  	{as: AMOVB, a1: C_SOREG, a6: C_REG, type_: 8, size: 8},
   226  	{as: AMOVB, a1: C_XOREG, a6: C_REG, type_: 109, size: 8},
   227  	{as: AMOVB, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
   228  	{as: AMOVB, a1: C_REG, a6: C_XOREG, type_: 108, size: 4},
   229  	{as: AMOVB, a1: C_REG, a6: C_REG, type_: 13, size: 4},
   230  
   231  	{as: AMOVBZ, a1: C_SOREG, a6: C_REG, type_: 8, size: 4},
   232  	{as: AMOVBZ, a1: C_XOREG, a6: C_REG, type_: 109, size: 4},
   233  	{as: AMOVBZ, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
   234  	{as: AMOVBZ, a1: C_REG, a6: C_XOREG, type_: 108, size: 4},
   235  	{as: AMOVBZ, a1: C_REG, a6: C_REG, type_: 13, size: 4},
   236  
   237  	{as: AMOVD, a1: C_16CON, a6: C_REG, type_: 3, size: 4},
   238  	{as: AMOVD, a1: C_SACON, a6: C_REG, type_: 3, size: 4},
   239  	{as: AMOVD, a1: C_SOREG, a6: C_REG, type_: 8, size: 4},
   240  	{as: AMOVD, a1: C_XOREG, a6: C_REG, type_: 109, size: 4},
   241  	{as: AMOVD, a1: C_SOREG, a6: C_SPR, type_: 107, size: 8},
   242  	{as: AMOVD, a1: C_SPR, a6: C_REG, type_: 66, size: 4},
   243  	{as: AMOVD, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
   244  	{as: AMOVD, a1: C_REG, a6: C_XOREG, type_: 108, size: 4},
   245  	{as: AMOVD, a1: C_SPR, a6: C_SOREG, type_: 106, size: 8},
   246  	{as: AMOVD, a1: C_REG, a6: C_SPR, type_: 66, size: 4},
   247  	{as: AMOVD, a1: C_REG, a6: C_REG, type_: 13, size: 4},
   248  
   249  	{as: AMOVW, a1: C_16CON, a6: C_REG, type_: 3, size: 4},
   250  	{as: AMOVW, a1: C_SACON, a6: C_REG, type_: 3, size: 4},
   251  	{as: AMOVW, a1: C_CREG, a6: C_REG, type_: 68, size: 4},
   252  	{as: AMOVW, a1: C_SOREG, a6: C_REG, type_: 8, size: 4},
   253  	{as: AMOVW, a1: C_XOREG, a6: C_REG, type_: 109, size: 4},
   254  	{as: AMOVW, a1: C_SPR, a6: C_REG, type_: 66, size: 4},
   255  	{as: AMOVW, a1: C_REG, a6: C_CREG, type_: 69, size: 4},
   256  	{as: AMOVW, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
   257  	{as: AMOVW, a1: C_REG, a6: C_XOREG, type_: 108, size: 4},
   258  	{as: AMOVW, a1: C_REG, a6: C_SPR, type_: 66, size: 4},
   259  	{as: AMOVW, a1: C_REG, a6: C_REG, type_: 13, size: 4},
   260  
   261  	{as: AFMOVD, a1: C_S16CON, a6: C_FREG, type_: 24, size: 8},
   262  	{as: AFMOVD, a1: C_SOREG, a6: C_FREG, type_: 8, size: 4},
   263  	{as: AFMOVD, a1: C_XOREG, a6: C_FREG, type_: 109, size: 4},
   264  	{as: AFMOVD, a1: C_ZCON, a6: C_FREG, type_: 24, size: 4},
   265  	{as: AFMOVD, a1: C_FREG, a6: C_FREG, type_: 33, size: 4},
   266  	{as: AFMOVD, a1: C_FREG, a6: C_SOREG, type_: 7, size: 4},
   267  	{as: AFMOVD, a1: C_FREG, a6: C_XOREG, type_: 108, size: 4},
   268  
   269  	{as: AFMOVSX, a1: C_XOREG, a6: C_FREG, type_: 45, size: 4},
   270  	{as: AFMOVSX, a1: C_FREG, a6: C_XOREG, type_: 44, size: 4},
   271  
   272  	{as: AFMOVSZ, a1: C_ZOREG, a6: C_FREG, type_: 45, size: 4},
   273  	{as: AFMOVSZ, a1: C_XOREG, a6: C_FREG, type_: 45, size: 4},
   274  
   275  	{as: AMOVFL, a1: C_CREG, a6: C_CREG, type_: 67, size: 4},
   276  	{as: AMOVFL, a1: C_FPSCR, a6: C_CREG, type_: 73, size: 4},
   277  	{as: AMOVFL, a1: C_FPSCR, a6: C_FREG, type_: 53, size: 4},
   278  	{as: AMOVFL, a1: C_FREG, a3: C_32CON, a6: C_FPSCR, type_: 64, size: 4},
   279  	{as: AMOVFL, a1: C_FREG, a6: C_FPSCR, type_: 64, size: 4},
   280  	{as: AMOVFL, a1: C_32CON, a6: C_FPSCR, type_: 65, size: 4},
   281  	{as: AMOVFL, a1: C_REG, a6: C_CREG, type_: 69, size: 4},
   282  	{as: AMOVFL, a1: C_REG, a6: C_32CON, type_: 69, size: 4},
   283  
   284  	{as: ASYSCALL, type_: 5, size: 4},
   285  	{as: ASYSCALL, a1: C_REG, type_: 77, size: 12},
   286  	{as: ASYSCALL, a1: C_U15CON, type_: 77, size: 12},
   287  	{as: ABEQ, a6: C_BRA, type_: 16, size: 4},
   288  	{as: ABEQ, a1: C_CREG, a6: C_BRA, type_: 16, size: 4},
   289  	{as: ABEQ, a1: C_CREG, a6: C_LR, type_: 17, size: 4},
   290  	{as: ABR, a6: C_BRA, type_: 11, size: 4},                                         // b label
   291  	{as: ABR, a6: C_BRAPIC, type_: 11, size: 8},                                      // b label; nop
   292  	{as: ABR, a6: C_LR, type_: 18, size: 4},                                          // blr
   293  	{as: ABR, a6: C_CTR, type_: 18, size: 4},                                         // bctr
   294  	{as: ABC, a1: C_U15CON, a2: C_CRBIT, a6: C_BRA, type_: 16, size: 4},              // bc bo, bi, label
   295  	{as: ABC, a1: C_U15CON, a2: C_CRBIT, a6: C_LR, type_: 18, size: 4},               // bclr bo, bi
   296  	{as: ABC, a1: C_U15CON, a2: C_CRBIT, a3: C_U15CON, a6: C_LR, type_: 18, size: 4}, // bclr bo, bi, bh
   297  	{as: ABC, a1: C_U15CON, a2: C_CRBIT, a6: C_CTR, type_: 18, size: 4},              // bcctr bo, bi
   298  	{as: ABDNZ, a6: C_BRA, type_: 16, size: 4},
   299  	{as: ASYNC, type_: 46, size: 4},
   300  	{as: AWORD, a1: C_32CON, type_: 40, size: 4},
   301  	{as: ADWORD, a1: C_64CON, type_: 31, size: 8},
   302  	{as: ADWORD, a1: C_LACON, type_: 31, size: 8},
   303  	{as: AADDME, a1: C_REG, a6: C_REG, type_: 47, size: 4},
   304  	{as: AEXTSB, a1: C_REG, a6: C_REG, type_: 48, size: 4},
   305  	{as: AEXTSB, a6: C_REG, type_: 48, size: 4},
   306  	{as: AISEL, a1: C_U5CON, a2: C_REG, a3: C_REG, a6: C_REG, type_: 84, size: 4},
   307  	{as: AISEL, a1: C_CRBIT, a2: C_REG, a3: C_REG, a6: C_REG, type_: 84, size: 4},
   308  	{as: ANEG, a1: C_REG, a6: C_REG, type_: 47, size: 4},
   309  	{as: ANEG, a6: C_REG, type_: 47, size: 4},
   310  	{as: AREM, a1: C_REG, a6: C_REG, type_: 50, size: 12},
   311  	{as: AREM, a1: C_REG, a2: C_REG, a6: C_REG, type_: 50, size: 12},
   312  	{as: AREMU, a1: C_REG, a6: C_REG, type_: 50, size: 16},
   313  	{as: AREMU, a1: C_REG, a2: C_REG, a6: C_REG, type_: 50, size: 16},
   314  	{as: AREMD, a1: C_REG, a6: C_REG, type_: 51, size: 12},
   315  	{as: AREMD, a1: C_REG, a2: C_REG, a6: C_REG, type_: 51, size: 12},
   316  	{as: AMTFSB0, a1: C_U15CON, type_: 52, size: 4},
   317  	/* Other ISA 2.05+ instructions */
   318  	{as: APOPCNTD, a1: C_REG, a6: C_REG, type_: 93, size: 4},            /* population count, x-form */
   319  	{as: ACMPB, a1: C_REG, a2: C_REG, a6: C_REG, type_: 92, size: 4},    /* compare byte, x-form */
   320  	{as: ACMPEQB, a1: C_REG, a2: C_REG, a6: C_CREG, type_: 92, size: 4}, /* compare equal byte, x-form, ISA 3.0 */
   321  	{as: ACMPEQB, a1: C_REG, a6: C_REG, type_: 70, size: 4},
   322  	{as: AFTDIV, a1: C_FREG, a2: C_FREG, a6: C_U15CON, type_: 92, size: 4},          /* floating test for sw divide, x-form */
   323  	{as: AFTSQRT, a1: C_FREG, a6: C_U15CON, type_: 93, size: 4},                     /* floating test for sw square root, x-form */
   324  	{as: ACOPY, a1: C_REG, a6: C_REG, type_: 92, size: 4},                           /* copy/paste facility, x-form */
   325  	{as: ADARN, a1: C_U15CON, a6: C_REG, type_: 92, size: 4},                        /* deliver random number, x-form */
   326  	{as: AMADDHD, a1: C_REG, a2: C_REG, a3: C_REG, a6: C_REG, type_: 83, size: 4},   /* multiply-add high/low doubleword, va-form */
   327  	{as: AADDEX, a1: C_REG, a2: C_REG, a3: C_U15CON, a6: C_REG, type_: 94, size: 4}, /* add extended using alternate carry, z23-form */
   328  	{as: ACRAND, a1: C_CRBIT, a2: C_CRBIT, a6: C_CRBIT, type_: 2, size: 4},          /* logical ops for condition register bits xl-form */
   329  
   330  	/* Misc ISA 3.0 instructions */
   331  	{as: ASETB, a1: C_CREG, a6: C_REG, type_: 110, size: 4},
   332  	{as: AVCLZLSBB, a1: C_VREG, a6: C_REG, type_: 85, size: 4},
   333  
   334  	/* Vector instructions */
   335  
   336  	/* Vector load */
   337  	{as: ALVEBX, a1: C_XOREG, a6: C_VREG, type_: 45, size: 4}, /* vector load, x-form */
   338  
   339  	/* Vector store */
   340  	{as: ASTVEBX, a1: C_VREG, a6: C_XOREG, type_: 44, size: 4}, /* vector store, x-form */
   341  
   342  	/* Vector logical */
   343  	{as: AVAND, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4}, /* vector and, vx-form */
   344  	{as: AVOR, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},  /* vector or, vx-form */
   345  
   346  	/* Vector add */
   347  	{as: AVADDUM, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},            /* vector add unsigned modulo, vx-form */
   348  	{as: AVADDCU, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},            /* vector add & write carry unsigned, vx-form */
   349  	{as: AVADDUS, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},            /* vector add unsigned saturate, vx-form */
   350  	{as: AVADDSS, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},            /* vector add signed saturate, vx-form */
   351  	{as: AVADDE, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4}, /* vector add extended, va-form */
   352  
   353  	/* Vector subtract */
   354  	{as: AVSUBUM, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},            /* vector subtract unsigned modulo, vx-form */
   355  	{as: AVSUBCU, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},            /* vector subtract & write carry unsigned, vx-form */
   356  	{as: AVSUBUS, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},            /* vector subtract unsigned saturate, vx-form */
   357  	{as: AVSUBSS, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},            /* vector subtract signed saturate, vx-form */
   358  	{as: AVSUBE, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4}, /* vector subtract extended, va-form */
   359  
   360  	/* Vector multiply */
   361  	{as: AVMULESB, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},              /* vector multiply, vx-form */
   362  	{as: AVPMSUM, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},               /* vector polynomial multiply & sum, vx-form */
   363  	{as: AVMSUMUDM, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4}, /* vector multiply-sum, va-form */
   364  
   365  	/* Vector rotate */
   366  	{as: AVR, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4}, /* vector rotate, vx-form */
   367  
   368  	/* Vector shift */
   369  	{as: AVS, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},                 /* vector shift, vx-form */
   370  	{as: AVSA, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},                /* vector shift algebraic, vx-form */
   371  	{as: AVSOI, a1: C_U16CON, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4}, /* vector shift by octet immediate, va-form */
   372  
   373  	/* Vector count */
   374  	{as: AVCLZ, a1: C_VREG, a6: C_VREG, type_: 85, size: 4},    /* vector count leading zeros, vx-form */
   375  	{as: AVPOPCNT, a1: C_VREG, a6: C_VREG, type_: 85, size: 4}, /* vector population count, vx-form */
   376  
   377  	/* Vector compare */
   378  	{as: AVCMPEQ, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},   /* vector compare equal, vc-form */
   379  	{as: AVCMPGT, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},   /* vector compare greater than, vc-form */
   380  	{as: AVCMPNEZB, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4}, /* vector compare not equal, vx-form */
   381  
   382  	/* Vector merge */
   383  	{as: AVMRGOW, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4}, /* vector merge odd word, vx-form */
   384  
   385  	/* Vector permute */
   386  	{as: AVPERM, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4}, /* vector permute, va-form */
   387  
   388  	/* Vector bit permute */
   389  	{as: AVBPERMQ, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4}, /* vector bit permute, vx-form */
   390  
   391  	/* Vector select */
   392  	{as: AVSEL, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4}, /* vector select, va-form */
   393  
   394  	/* Vector splat */
   395  	{as: AVSPLTB, a1: C_S16CON, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
   396  	{as: AVSPLTISB, a1: C_S16CON, a6: C_VREG, type_: 82, size: 4},
   397  
   398  	/* Vector AES */
   399  	{as: AVCIPH, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},  /* vector AES cipher, vx-form */
   400  	{as: AVNCIPH, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4}, /* vector AES inverse cipher, vx-form */
   401  	{as: AVSBOX, a1: C_VREG, a6: C_VREG, type_: 82, size: 4},              /* vector AES subbytes, vx-form */
   402  
   403  	/* Vector SHA */
   404  	{as: AVSHASIGMA, a1: C_U16CON, a2: C_VREG, a3: C_U16CON, a6: C_VREG, type_: 82, size: 4}, /* vector SHA sigma, vx-form */
   405  
   406  	/* VSX vector load */
   407  	{as: ALXVD2X, a1: C_XOREG, a6: C_VSREG, type_: 87, size: 4},        /* vsx vector load, xx1-form */
   408  	{as: ALXV, a1: C_SOREG, a6: C_VSREG, type_: 96, size: 4},           /* vsx vector load, dq-form */
   409  	{as: ALXVL, a1: C_REG, a2: C_REG, a6: C_VSREG, type_: 98, size: 4}, /* vsx vector load length */
   410  
   411  	/* VSX vector store */
   412  	{as: ASTXVD2X, a1: C_VSREG, a6: C_XOREG, type_: 86, size: 4},        /* vsx vector store, xx1-form */
   413  	{as: ASTXV, a1: C_VSREG, a6: C_SOREG, type_: 97, size: 4},           /* vsx vector store, dq-form */
   414  	{as: ASTXVL, a1: C_VSREG, a2: C_REG, a6: C_REG, type_: 99, size: 4}, /* vsx vector store with length x-form */
   415  
   416  	/* VSX scalar load */
   417  	{as: ALXSDX, a1: C_XOREG, a6: C_VSREG, type_: 87, size: 4}, /* vsx scalar load, xx1-form */
   418  
   419  	/* VSX scalar store */
   420  	{as: ASTXSDX, a1: C_VSREG, a6: C_XOREG, type_: 86, size: 4}, /* vsx scalar store, xx1-form */
   421  
   422  	/* VSX scalar as integer load */
   423  	{as: ALXSIWAX, a1: C_XOREG, a6: C_VSREG, type_: 87, size: 4}, /* vsx scalar as integer load, xx1-form */
   424  
   425  	/* VSX scalar store as integer */
   426  	{as: ASTXSIWX, a1: C_VSREG, a6: C_XOREG, type_: 86, size: 4}, /* vsx scalar as integer store, xx1-form */
   427  
   428  	/* VSX move from VSR */
   429  	{as: AMFVSRD, a1: C_VSREG, a6: C_REG, type_: 88, size: 4},
   430  	{as: AMFVSRD, a1: C_FREG, a6: C_REG, type_: 88, size: 4},
   431  
   432  	/* VSX move to VSR */
   433  	{as: AMTVSRD, a1: C_REG, a6: C_VSREG, type_: 104, size: 4},
   434  	{as: AMTVSRD, a1: C_REG, a6: C_FREG, type_: 104, size: 4},
   435  	{as: AMTVSRDD, a1: C_REG, a2: C_REG, a6: C_VSREG, type_: 104, size: 4},
   436  
   437  	/* VSX xx3-form */
   438  	{as: AXXLAND, a1: C_FREG, a2: C_FREG, a6: C_FREG, type_: 90, size: 4},    /* vsx xx3-form (FPR usage) */
   439  	{as: AXXLAND, a1: C_VSREG, a2: C_VSREG, a6: C_VSREG, type_: 90, size: 4}, /* vsx xx3-form */
   440  
   441  	/* VSX select */
   442  	{as: AXXSEL, a1: C_VSREG, a2: C_VSREG, a3: C_VSREG, a6: C_VSREG, type_: 91, size: 4}, /* vsx select, xx4-form */
   443  
   444  	/* VSX merge */
   445  	{as: AXXMRGHW, a1: C_VSREG, a2: C_VSREG, a6: C_VSREG, type_: 90, size: 4}, /* vsx merge, xx3-form */
   446  
   447  	/* VSX splat */
   448  	{as: AXXSPLTW, a1: C_VSREG, a3: C_U15CON, a6: C_VSREG, type_: 89, size: 4}, /* vsx splat, xx2-form */
   449  	{as: AXXSPLTIB, a1: C_U15CON, a6: C_VSREG, type_: 100, size: 4},            /* vsx splat, xx2-form */
   450  
   451  	/* VSX permute */
   452  	{as: AXXPERM, a1: C_VSREG, a2: C_VSREG, a6: C_VSREG, type_: 90, size: 4}, /* vsx permute, xx3-form */
   453  
   454  	/* VSX shift */
   455  	{as: AXXSLDWI, a1: C_VSREG, a2: C_VSREG, a3: C_U15CON, a6: C_VSREG, type_: 90, size: 4}, /* vsx shift immediate, xx3-form */
   456  
   457  	/* VSX reverse bytes */
   458  	{as: AXXBRQ, a1: C_VSREG, a6: C_VSREG, type_: 101, size: 4}, /* vsx reverse bytes */
   459  
   460  	/* VSX scalar FP-FP conversion */
   461  	{as: AXSCVDPSP, a1: C_VSREG, a6: C_VSREG, type_: 89, size: 4}, /* vsx scalar fp-fp conversion, xx2-form */
   462  
   463  	/* VSX vector FP-FP conversion */
   464  	{as: AXVCVDPSP, a1: C_VSREG, a6: C_VSREG, type_: 89, size: 4}, /* vsx vector fp-fp conversion, xx2-form */
   465  
   466  	/* VSX scalar FP-integer conversion */
   467  	{as: AXSCVDPSXDS, a1: C_VSREG, a6: C_VSREG, type_: 89, size: 4}, /* vsx scalar fp-integer conversion, xx2-form */
   468  
   469  	/* VSX scalar integer-FP conversion */
   470  	{as: AXSCVSXDDP, a1: C_VSREG, a6: C_VSREG, type_: 89, size: 4}, /* vsx scalar integer-fp conversion, xx2-form */
   471  
   472  	/* VSX vector FP-integer conversion */
   473  	{as: AXVCVDPSXDS, a1: C_VSREG, a6: C_VSREG, type_: 89, size: 4}, /* vsx vector fp-integer conversion, xx2-form */
   474  
   475  	/* VSX vector integer-FP conversion */
   476  	{as: AXVCVSXDDP, a1: C_VSREG, a6: C_VSREG, type_: 89, size: 4}, /* vsx vector integer-fp conversion, xx2-form */
   477  
   478  	{as: ACMP, a1: C_REG, a6: C_REG, type_: 70, size: 4},
   479  	{as: ACMP, a1: C_REG, a2: C_CREG, a6: C_REG, type_: 70, size: 4},
   480  	{as: ACMP, a1: C_REG, a6: C_S16CON, type_: 70, size: 4},
   481  	{as: ACMP, a1: C_REG, a2: C_CREG, a6: C_S16CON, type_: 70, size: 4},
   482  	{as: ACMPU, a1: C_REG, a6: C_REG, type_: 70, size: 4},
   483  	{as: ACMPU, a1: C_REG, a2: C_CREG, a6: C_REG, type_: 70, size: 4},
   484  	{as: ACMPU, a1: C_REG, a6: C_U16CON, type_: 70, size: 4},
   485  	{as: ACMPU, a1: C_REG, a2: C_CREG, a6: C_U16CON, type_: 70, size: 4},
   486  	{as: AFCMPO, a1: C_FREG, a6: C_FREG, type_: 70, size: 4},
   487  	{as: AFCMPO, a1: C_FREG, a2: C_CREG, a6: C_FREG, type_: 70, size: 4},
   488  	{as: ADCMPOQ, a1: C_FREGP, a6: C_FREGP, type_: 70, size: 4},
   489  	{as: ADCMPOQ, a1: C_FREGP, a2: C_CREG, a6: C_FREGP, type_: 70, size: 4},
   490  	{as: ATW, a1: C_32CON, a2: C_REG, a6: C_REG, type_: 60, size: 4},
   491  	{as: ATW, a1: C_32CON, a2: C_REG, a6: C_S16CON, type_: 61, size: 4},
   492  	{as: ADCBF, a1: C_SOREG, type_: 43, size: 4},
   493  	{as: ADCBF, a1: C_XOREG, type_: 43, size: 4},
   494  	{as: ADCBF, a1: C_XOREG, a2: C_REG, a6: C_U15CON, type_: 43, size: 4},
   495  	{as: ADCBF, a1: C_SOREG, a6: C_U15CON, type_: 43, size: 4},
   496  	{as: ADCBF, a1: C_XOREG, a6: C_U15CON, type_: 43, size: 4},
   497  	{as: ASTDCCC, a1: C_REG, a2: C_REG, a6: C_XOREG, type_: 44, size: 4},
   498  	{as: ASTDCCC, a1: C_REG, a6: C_XOREG, type_: 44, size: 4},
   499  	{as: ALDAR, a1: C_XOREG, a6: C_REG, type_: 45, size: 4},
   500  	{as: ALDAR, a1: C_XOREG, a3: C_U16CON, a6: C_REG, type_: 45, size: 4},
   501  	{as: AEIEIO, type_: 46, size: 4},
   502  	{as: ATLBIE, a1: C_REG, type_: 49, size: 4},
   503  	{as: ATLBIE, a1: C_U15CON, a6: C_REG, type_: 49, size: 4},
   504  	{as: ASLBMFEE, a1: C_REG, a6: C_REG, type_: 55, size: 4},
   505  	{as: ASLBMTE, a1: C_REG, a6: C_REG, type_: 55, size: 4},
   506  	{as: ASTSW, a1: C_REG, a6: C_XOREG, type_: 44, size: 4},
   507  	{as: ASTSW, a1: C_REG, a3: C_32CON, a6: C_ZOREG, type_: 41, size: 4},
   508  	{as: ALSW, a1: C_XOREG, a6: C_REG, type_: 45, size: 4},
   509  	{as: ALSW, a1: C_ZOREG, a3: C_32CON, a6: C_REG, type_: 42, size: 4},
   510  
   511  	{as: obj.AUNDEF, type_: 78, size: 4},
   512  	{as: obj.APCDATA, a1: C_32CON, a6: C_32CON, type_: 0, size: 0},
   513  	{as: obj.AFUNCDATA, a1: C_U15CON, a6: C_ADDR, type_: 0, size: 0},
   514  	{as: obj.ANOP, type_: 0, size: 0},
   515  	{as: obj.ANOP, a1: C_32CON, type_: 0, size: 0}, // NOP operand variations added for #40689
   516  	{as: obj.ANOP, a1: C_REG, type_: 0, size: 0},   // to preserve previous behavior
   517  	{as: obj.ANOP, a1: C_FREG, type_: 0, size: 0},
   518  	{as: obj.ADUFFZERO, a6: C_BRA, type_: 11, size: 4}, // same as ABR/ABL
   519  	{as: obj.ADUFFCOPY, a6: C_BRA, type_: 11, size: 4}, // same as ABR/ABL
   520  	{as: obj.APCALIGN, a1: C_32CON, type_: 0, size: 0}, // align code
   521  }
   522  
   523  // These are opcodes above which may generate different sequences depending on whether prefix opcode support
   524  // is available
   525  type PrefixableOptab struct {
   526  	Optab
   527  	minGOPPC64 int  // Minimum GOPPC64 required to support this.
   528  	pfxsize    int8 // Instruction sequence size when prefixed opcodes are used
   529  }
   530  
   531  // The prefixable optab entry contains the pseudo-opcodes which generate relocations, or may generate
   532  // a more efficient sequence of instructions if a prefixed version exists (ex. paddi instead of oris/ori/add).
   533  //
   534  // This table is meant to transform all sequences which might be TOC-relative into an equivalent PC-relative
   535  // sequence. It also encompasses several transformations which do not involve relocations, those could be
   536  // separated and applied to AIX and other non-ELF targets. Likewise, the prefixed forms do not have encoding
   537  // restrictions on the offset, so they are also used for static binary to allow better code generation. e.x
   538  //
   539  //	MOVD something-byte-aligned(Rx), Ry
   540  //	MOVD 3(Rx), Ry
   541  //
   542  // is allowed when the prefixed forms are used.
   543  //
   544  // This requires an ISA 3.1 compatible cpu (e.g Power10), and when linking externally an ELFv2 1.5 compliant.
   545  var prefixableOptab = []PrefixableOptab{
   546  	{Optab: Optab{as: AMOVD, a1: C_S34CON, a6: C_REG, type_: 19, size: 8}, minGOPPC64: 10, pfxsize: 8},
   547  	{Optab: Optab{as: AMOVD, a1: C_ADDR, a6: C_REG, type_: 75, size: 8}, minGOPPC64: 10, pfxsize: 8},
   548  	{Optab: Optab{as: AMOVD, a1: C_TLS_LE, a6: C_REG, type_: 79, size: 8}, minGOPPC64: 10, pfxsize: 8},
   549  	{Optab: Optab{as: AMOVD, a1: C_TLS_IE, a6: C_REG, type_: 80, size: 12}, minGOPPC64: 10, pfxsize: 12},
   550  	{Optab: Optab{as: AMOVD, a1: C_LACON, a6: C_REG, type_: 26, size: 8}, minGOPPC64: 10, pfxsize: 8},
   551  	{Optab: Optab{as: AMOVD, a1: C_LOREG, a6: C_REG, type_: 36, size: 8}, minGOPPC64: 10, pfxsize: 8},
   552  	{Optab: Optab{as: AMOVD, a1: C_REG, a6: C_LOREG, type_: 35, size: 8}, minGOPPC64: 10, pfxsize: 8},
   553  	{Optab: Optab{as: AMOVD, a1: C_REG, a6: C_ADDR, type_: 74, size: 8}, minGOPPC64: 10, pfxsize: 8},
   554  
   555  	{Optab: Optab{as: AMOVW, a1: C_32CON, a6: C_REG, type_: 19, size: 8}, minGOPPC64: 10, pfxsize: 8},
   556  	{Optab: Optab{as: AMOVW, a1: C_LACON, a6: C_REG, type_: 26, size: 8}, minGOPPC64: 10, pfxsize: 8},
   557  	{Optab: Optab{as: AMOVW, a1: C_LOREG, a6: C_REG, type_: 36, size: 8}, minGOPPC64: 10, pfxsize: 8},
   558  	{Optab: Optab{as: AMOVW, a1: C_ADDR, a6: C_REG, type_: 75, size: 8}, minGOPPC64: 10, pfxsize: 8},
   559  	{Optab: Optab{as: AMOVW, a1: C_REG, a6: C_LOREG, type_: 35, size: 8}, minGOPPC64: 10, pfxsize: 8},
   560  	{Optab: Optab{as: AMOVW, a1: C_REG, a6: C_ADDR, type_: 74, size: 8}, minGOPPC64: 10, pfxsize: 8},
   561  
   562  	{Optab: Optab{as: AMOVB, a1: C_REG, a6: C_LOREG, type_: 35, size: 8}, minGOPPC64: 10, pfxsize: 8},
   563  	{Optab: Optab{as: AMOVB, a1: C_LOREG, a6: C_REG, type_: 36, size: 12}, minGOPPC64: 10, pfxsize: 12},
   564  	{Optab: Optab{as: AMOVB, a1: C_ADDR, a6: C_REG, type_: 75, size: 12}, minGOPPC64: 10, pfxsize: 12},
   565  	{Optab: Optab{as: AMOVB, a1: C_REG, a6: C_ADDR, type_: 74, size: 8}, minGOPPC64: 10, pfxsize: 8},
   566  
   567  	{Optab: Optab{as: AMOVBZ, a1: C_LOREG, a6: C_REG, type_: 36, size: 8}, minGOPPC64: 10, pfxsize: 8},
   568  	{Optab: Optab{as: AMOVBZ, a1: C_ADDR, a6: C_REG, type_: 75, size: 8}, minGOPPC64: 10, pfxsize: 8},
   569  	{Optab: Optab{as: AMOVBZ, a1: C_REG, a6: C_LOREG, type_: 35, size: 8}, minGOPPC64: 10, pfxsize: 8},
   570  	{Optab: Optab{as: AMOVBZ, a1: C_REG, a6: C_ADDR, type_: 74, size: 8}, minGOPPC64: 10, pfxsize: 8},
   571  
   572  	{Optab: Optab{as: AFMOVD, a1: C_LOREG, a6: C_FREG, type_: 36, size: 8}, minGOPPC64: 10, pfxsize: 8},
   573  	{Optab: Optab{as: AFMOVD, a1: C_ADDR, a6: C_FREG, type_: 75, size: 8}, minGOPPC64: 10, pfxsize: 8},
   574  	{Optab: Optab{as: AFMOVD, a1: C_FREG, a6: C_LOREG, type_: 35, size: 8}, minGOPPC64: 10, pfxsize: 8},
   575  	{Optab: Optab{as: AFMOVD, a1: C_FREG, a6: C_ADDR, type_: 74, size: 8}, minGOPPC64: 10, pfxsize: 8},
   576  
   577  	{Optab: Optab{as: AADD, a1: C_32CON, a2: C_REG, a6: C_REG, type_: 22, size: 12}, minGOPPC64: 10, pfxsize: 8},
   578  	{Optab: Optab{as: AADD, a1: C_32CON, a6: C_REG, type_: 22, size: 12}, minGOPPC64: 10, pfxsize: 8},
   579  	{Optab: Optab{as: AADD, a1: C_S34CON, a2: C_REG, a6: C_REG, type_: 22, size: 20}, minGOPPC64: 10, pfxsize: 8},
   580  	{Optab: Optab{as: AADD, a1: C_S34CON, a6: C_REG, type_: 22, size: 20}, minGOPPC64: 10, pfxsize: 8},
   581  }
   582  
   583  var oprange [ALAST & obj.AMask][]Optab
   584  
   585  var xcmp [C_NCLASS][C_NCLASS]bool
   586  
   587  var pfxEnabled = false // ISA 3.1 prefixed instructions are supported.
   588  var buildOpCfg = ""    // Save the os/cpu/arch tuple used to configure the assembler in buildop
   589  
   590  // padding bytes to add to align code as requested.
   591  func addpad(pc, a int64, ctxt *obj.Link, cursym *obj.LSym) int {
   592  	switch a {
   593  	case 8, 16, 32, 64:
   594  		// By default function alignment is 16. If an alignment > 16 is
   595  		// requested then the function alignment must also be promoted.
   596  		// The function alignment is not promoted on AIX at this time.
   597  		// TODO: Investigate AIX function alignment.
   598  		if ctxt.Headtype != objabi.Haix && cursym.Func().Align < int32(a) {
   599  			cursym.Func().Align = int32(a)
   600  		}
   601  		if pc&(a-1) != 0 {
   602  			return int(a - (pc & (a - 1)))
   603  		}
   604  	default:
   605  		ctxt.Diag("Unexpected alignment: %d for PCALIGN directive\n", a)
   606  	}
   607  	return 0
   608  }
   609  
   610  func span9(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) {
   611  	p := cursym.Func().Text
   612  	if p == nil || p.Link == nil { // handle external functions and ELF section symbols
   613  		return
   614  	}
   615  
   616  	if oprange[AANDN&obj.AMask] == nil {
   617  		ctxt.Diag("ppc64 ops not initialized, call ppc64.buildop first")
   618  	}
   619  
   620  	c := ctxt9{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset)}
   621  
   622  	pc := int64(0)
   623  	p.Pc = pc
   624  
   625  	var m int
   626  	var o *Optab
   627  	for p = p.Link; p != nil; p = p.Link {
   628  		p.Pc = pc
   629  		o = c.oplook(p)
   630  		m = int(o.size)
   631  		if m == 0 {
   632  			if p.As == obj.APCALIGN {
   633  				a := c.vregoff(&p.From)
   634  				m = addpad(pc, a, ctxt, cursym)
   635  			} else {
   636  				if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA {
   637  					ctxt.Diag("zero-width instruction\n%v", p)
   638  				}
   639  				continue
   640  			}
   641  		}
   642  		pc += int64(m)
   643  	}
   644  
   645  	c.cursym.Size = pc
   646  
   647  	/*
   648  	 * if any procedure is large enough to
   649  	 * generate a large SBRA branch, then
   650  	 * generate extra passes putting branches
   651  	 * around jmps to fix. this is rare.
   652  	 */
   653  	bflag := 1
   654  
   655  	var otxt int64
   656  	var q *obj.Prog
   657  	var out [5]uint32
   658  	var falign int32 // Track increased alignment requirements for prefix.
   659  	for bflag != 0 {
   660  		bflag = 0
   661  		pc = 0
   662  		falign = 0 // Note, linker bumps function symbols to funcAlign.
   663  		for p = c.cursym.Func().Text.Link; p != nil; p = p.Link {
   664  			p.Pc = pc
   665  			o = c.oplook(p)
   666  
   667  			// very large conditional branches
   668  			if (o.type_ == 16 || o.type_ == 17) && p.To.Target() != nil {
   669  				otxt = p.To.Target().Pc - pc
   670  				if otxt < -(1<<15)+10 || otxt >= (1<<15)-10 {
   671  					// Assemble the instruction with a target not too far to figure out BI and BO fields.
   672  					// If only the CTR or BI (the CR bit) are tested, the conditional branch can be inverted,
   673  					// and only one extra branch is needed to reach the target.
   674  					tgt := p.To.Target()
   675  					p.To.SetTarget(p.Link)
   676  					o.asmout(&c, p, o, &out)
   677  					p.To.SetTarget(tgt)
   678  
   679  					bo := int64(out[0]>>21) & 31
   680  					bi := int16((out[0] >> 16) & 31)
   681  					invertible := false
   682  
   683  					if bo&0x14 == 0x14 {
   684  						// A conditional branch that is unconditionally taken. This cannot be inverted.
   685  					} else if bo&0x10 == 0x10 {
   686  						// A branch based on the value of CTR. Invert the CTR comparison against zero bit.
   687  						bo ^= 0x2
   688  						invertible = true
   689  					} else if bo&0x04 == 0x04 {
   690  						// A branch based on CR bit. Invert the BI comparison bit.
   691  						bo ^= 0x8
   692  						invertible = true
   693  					}
   694  
   695  					if invertible {
   696  						// Rewrite
   697  						//     BC bo,...,far_away_target
   698  						//     NEXT_INSN
   699  						// to:
   700  						//     BC invert(bo),next_insn
   701  						//     JMP far_away_target
   702  						//   next_insn:
   703  						//     NEXT_INSN
   704  						p.As = ABC
   705  						p.From = obj.Addr{Type: obj.TYPE_CONST, Name: obj.NAME_NONE, Offset: bo}
   706  						q = c.newprog()
   707  						q.As = ABR
   708  						q.To.Type = obj.TYPE_BRANCH
   709  						q.To.SetTarget(p.To.Target())
   710  						q.Link = p.Link
   711  						p.To.SetTarget(p.Link)
   712  						p.Link = q
   713  						p.Reg = REG_CRBIT0 + bi
   714  					} else {
   715  						// Rewrite
   716  						//     BC ...,far_away_target
   717  						//     NEXT_INSN
   718  						// to
   719  						//     BC ...,tmp
   720  						//     JMP next_insn
   721  						//   tmp:
   722  						//     JMP far_away_target
   723  						//   next_insn:
   724  						//     NEXT_INSN
   725  						q = c.newprog()
   726  						q.Link = p.Link
   727  						p.Link = q
   728  						q.As = ABR
   729  						q.To.Type = obj.TYPE_BRANCH
   730  						q.To.SetTarget(p.To.Target())
   731  						p.To.SetTarget(q)
   732  						q = c.newprog()
   733  						q.Link = p.Link
   734  						p.Link = q
   735  						q.As = ABR
   736  						q.To.Type = obj.TYPE_BRANCH
   737  						q.To.SetTarget(q.Link.Link)
   738  					}
   739  					bflag = 1
   740  				}
   741  			}
   742  
   743  			m = int(o.size)
   744  			if m == 0 {
   745  				if p.As == obj.APCALIGN {
   746  					a := c.vregoff(&p.From)
   747  					m = addpad(pc, a, ctxt, cursym)
   748  				} else {
   749  					if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA {
   750  						ctxt.Diag("zero-width instruction\n%v", p)
   751  					}
   752  					continue
   753  				}
   754  			}
   755  
   756  			// Prefixed instructions cannot be placed across a 64B boundary.
   757  			// Mark and adjust the PC of those which do. A nop will be
   758  			// inserted during final assembly.
   759  			if o.ispfx {
   760  				mark := p.Mark &^ PFX_X64B
   761  				if pc&63 == 60 {
   762  					p.Pc += 4
   763  					m += 4
   764  					mark |= PFX_X64B
   765  				}
   766  
   767  				// Marks may be adjusted if a too-far conditional branch is
   768  				// fixed up above. Likewise, inserting a NOP may cause a
   769  				// branch target to become too far away.  We need to run
   770  				// another iteration and verify no additional changes
   771  				// are needed.
   772  				if mark != p.Mark {
   773  					bflag = 1
   774  					p.Mark = mark
   775  				}
   776  
   777  				// Check for 16 or 32B crossing of this prefixed insn.
   778  				// These do no require padding, but do require increasing
   779  				// the function alignment to prevent them from potentially
   780  				// crossing a 64B boundary when the linker assigns the final
   781  				// PC.
   782  				switch p.Pc & 31 {
   783  				case 28: // 32B crossing
   784  					falign = 64
   785  				case 12: // 16B crossing
   786  					if falign < 64 {
   787  						falign = 32
   788  					}
   789  				}
   790  			}
   791  
   792  			pc += int64(m)
   793  		}
   794  
   795  		c.cursym.Size = pc
   796  	}
   797  
   798  	c.cursym.Size = pc
   799  	c.cursym.Func().Align = falign
   800  	c.cursym.Grow(c.cursym.Size)
   801  
   802  	// lay out the code, emitting code and data relocations.
   803  
   804  	bp := c.cursym.P
   805  	var i int32
   806  	for p := c.cursym.Func().Text.Link; p != nil; p = p.Link {
   807  		c.pc = p.Pc
   808  		o = c.oplook(p)
   809  		if int(o.size) > 4*len(out) {
   810  			log.Fatalf("out array in span9 is too small, need at least %d for %v", o.size/4, p)
   811  		}
   812  		// asmout is not set up to add large amounts of padding
   813  		if o.type_ == 0 && p.As == obj.APCALIGN {
   814  			aln := c.vregoff(&p.From)
   815  			v := addpad(p.Pc, aln, c.ctxt, c.cursym)
   816  			if v > 0 {
   817  				// Same padding instruction for all
   818  				for i = 0; i < int32(v/4); i++ {
   819  					c.ctxt.Arch.ByteOrder.PutUint32(bp, NOP)
   820  					bp = bp[4:]
   821  				}
   822  			}
   823  		} else {
   824  			if p.Mark&PFX_X64B != 0 {
   825  				c.ctxt.Arch.ByteOrder.PutUint32(bp, NOP)
   826  				bp = bp[4:]
   827  			}
   828  			o.asmout(&c, p, o, &out)
   829  			for i = 0; i < int32(o.size/4); i++ {
   830  				c.ctxt.Arch.ByteOrder.PutUint32(bp, out[i])
   831  				bp = bp[4:]
   832  			}
   833  		}
   834  	}
   835  }
   836  
   837  func isint32(v int64) bool {
   838  	return int64(int32(v)) == v
   839  }
   840  
   841  func isuint32(v uint64) bool {
   842  	return uint64(uint32(v)) == v
   843  }
   844  
   845  func (c *ctxt9) aclassreg(reg int16) int {
   846  	if REG_R0 <= reg && reg <= REG_R31 {
   847  		return C_REGP + int(reg&1)
   848  	}
   849  	if REG_F0 <= reg && reg <= REG_F31 {
   850  		return C_FREGP + int(reg&1)
   851  	}
   852  	if REG_V0 <= reg && reg <= REG_V31 {
   853  		return C_VREG
   854  	}
   855  	if REG_VS0 <= reg && reg <= REG_VS63 {
   856  		return C_VSREGP + int(reg&1)
   857  	}
   858  	if REG_CR0 <= reg && reg <= REG_CR7 || reg == REG_CR {
   859  		return C_CREG
   860  	}
   861  	if REG_CR0LT <= reg && reg <= REG_CR7SO {
   862  		return C_CRBIT
   863  	}
   864  	if REG_SPR0 <= reg && reg <= REG_SPR0+1023 {
   865  		switch reg {
   866  		case REG_LR:
   867  			return C_LR
   868  
   869  		case REG_CTR:
   870  			return C_CTR
   871  		}
   872  
   873  		return C_SPR
   874  	}
   875  	if REG_A0 <= reg && reg <= REG_A7 {
   876  		return C_AREG
   877  	}
   878  	if reg == REG_FPSCR {
   879  		return C_FPSCR
   880  	}
   881  	return C_GOK
   882  }
   883  
   884  func (c *ctxt9) aclass(a *obj.Addr) int {
   885  	switch a.Type {
   886  	case obj.TYPE_NONE:
   887  		return C_NONE
   888  
   889  	case obj.TYPE_REG:
   890  		return c.aclassreg(a.Reg)
   891  
   892  	case obj.TYPE_MEM:
   893  		if a.Index != 0 {
   894  			if a.Name != obj.NAME_NONE || a.Offset != 0 {
   895  				c.ctxt.Logf("Unexpected Instruction operand index %d offset %d class %d \n", a.Index, a.Offset, a.Class)
   896  
   897  			}
   898  			return C_XOREG
   899  		}
   900  		switch a.Name {
   901  		case obj.NAME_GOTREF, obj.NAME_TOCREF:
   902  			return C_ADDR
   903  
   904  		case obj.NAME_EXTERN,
   905  			obj.NAME_STATIC:
   906  			c.instoffset = a.Offset
   907  			if a.Sym == nil {
   908  				break
   909  			} else if a.Sym.Type == objabi.STLSBSS {
   910  				// For PIC builds, use 12 byte got initial-exec TLS accesses.
   911  				if c.ctxt.Flag_shared {
   912  					return C_TLS_IE
   913  				}
   914  				// Otherwise, use 8 byte local-exec TLS accesses.
   915  				return C_TLS_LE
   916  			} else {
   917  				return C_ADDR
   918  			}
   919  
   920  		case obj.NAME_AUTO:
   921  			a.Reg = REGSP
   922  			c.instoffset = int64(c.autosize) + a.Offset
   923  			if c.instoffset >= -BIG && c.instoffset < BIG {
   924  				return C_SOREG
   925  			}
   926  			return C_LOREG
   927  
   928  		case obj.NAME_PARAM:
   929  			a.Reg = REGSP
   930  			c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize
   931  			if c.instoffset >= -BIG && c.instoffset < BIG {
   932  				return C_SOREG
   933  			}
   934  			return C_LOREG
   935  
   936  		case obj.NAME_NONE:
   937  			c.instoffset = a.Offset
   938  			if a.Offset == 0 && a.Index == 0 {
   939  				return C_ZOREG
   940  			} else if c.instoffset >= -BIG && c.instoffset < BIG {
   941  				return C_SOREG
   942  			} else {
   943  				return C_LOREG
   944  			}
   945  		}
   946  
   947  		return C_GOK
   948  
   949  	case obj.TYPE_TEXTSIZE:
   950  		return C_TEXTSIZE
   951  
   952  	case obj.TYPE_FCONST:
   953  		// The only cases where FCONST will occur are with float64 +/- 0.
   954  		// All other float constants are generated in memory.
   955  		f64 := a.Val.(float64)
   956  		if f64 == 0 {
   957  			if math.Signbit(f64) {
   958  				return C_S16CON
   959  			}
   960  			return C_ZCON
   961  		}
   962  		log.Fatalf("Unexpected nonzero FCONST operand %v", a)
   963  
   964  	case obj.TYPE_CONST,
   965  		obj.TYPE_ADDR:
   966  		switch a.Name {
   967  		case obj.NAME_NONE:
   968  			c.instoffset = a.Offset
   969  			if a.Reg != 0 {
   970  				if -BIG <= c.instoffset && c.instoffset < BIG {
   971  					return C_SACON
   972  				}
   973  				if isint32(c.instoffset) {
   974  					return C_LACON
   975  				}
   976  				return C_DACON
   977  			}
   978  
   979  		case obj.NAME_EXTERN,
   980  			obj.NAME_STATIC:
   981  			s := a.Sym
   982  			if s == nil {
   983  				return C_GOK
   984  			}
   985  			c.instoffset = a.Offset
   986  			return C_LACON
   987  
   988  		case obj.NAME_AUTO:
   989  			a.Reg = REGSP
   990  			c.instoffset = int64(c.autosize) + a.Offset
   991  			if c.instoffset >= -BIG && c.instoffset < BIG {
   992  				return C_SACON
   993  			}
   994  			return C_LACON
   995  
   996  		case obj.NAME_PARAM:
   997  			a.Reg = REGSP
   998  			c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize
   999  			if c.instoffset >= -BIG && c.instoffset < BIG {
  1000  				return C_SACON
  1001  			}
  1002  			return C_LACON
  1003  
  1004  		default:
  1005  			return C_GOK
  1006  		}
  1007  
  1008  		if c.instoffset >= 0 {
  1009  			sbits := bits.Len64(uint64(c.instoffset))
  1010  			switch {
  1011  			case sbits <= 5:
  1012  				return C_ZCON + sbits
  1013  			case sbits <= 8:
  1014  				return C_U8CON
  1015  			case sbits <= 15:
  1016  				return C_U15CON
  1017  			case sbits <= 16:
  1018  				return C_U16CON
  1019  			case sbits <= 31:
  1020  				return C_U31CON
  1021  			case sbits <= 32:
  1022  				return C_U32CON
  1023  			case sbits <= 33:
  1024  				return C_S34CON
  1025  			default:
  1026  				return C_64CON
  1027  			}
  1028  		} else {
  1029  			sbits := bits.Len64(uint64(^c.instoffset))
  1030  			switch {
  1031  			case sbits <= 15:
  1032  				return C_S16CON
  1033  			case sbits <= 31:
  1034  				return C_S32CON
  1035  			case sbits <= 33:
  1036  				return C_S34CON
  1037  			default:
  1038  				return C_64CON
  1039  			}
  1040  		}
  1041  
  1042  	case obj.TYPE_BRANCH:
  1043  		if a.Sym != nil && c.ctxt.Flag_dynlink && !pfxEnabled {
  1044  			return C_BRAPIC
  1045  		}
  1046  		return C_BRA
  1047  	}
  1048  
  1049  	return C_GOK
  1050  }
  1051  
  1052  func prasm(p *obj.Prog) {
  1053  	fmt.Printf("%v\n", p)
  1054  }
  1055  
  1056  func (c *ctxt9) oplook(p *obj.Prog) *Optab {
  1057  	a1 := int(p.Optab)
  1058  	if a1 != 0 {
  1059  		return &optab[a1-1]
  1060  	}
  1061  	a1 = int(p.From.Class)
  1062  	if a1 == 0 {
  1063  		a1 = c.aclass(&p.From) + 1
  1064  		p.From.Class = int8(a1)
  1065  	}
  1066  	a1--
  1067  
  1068  	argsv := [3]int{C_NONE + 1, C_NONE + 1, C_NONE + 1}
  1069  	for i, ap := range p.RestArgs {
  1070  		argsv[i] = int(ap.Addr.Class)
  1071  		if argsv[i] == 0 {
  1072  			argsv[i] = c.aclass(&ap.Addr) + 1
  1073  			ap.Addr.Class = int8(argsv[i])
  1074  		}
  1075  
  1076  	}
  1077  	a3 := argsv[0] - 1
  1078  	a4 := argsv[1] - 1
  1079  	a5 := argsv[2] - 1
  1080  
  1081  	a6 := int(p.To.Class)
  1082  	if a6 == 0 {
  1083  		a6 = c.aclass(&p.To) + 1
  1084  		p.To.Class = int8(a6)
  1085  	}
  1086  	a6--
  1087  
  1088  	a2 := C_NONE
  1089  	if p.Reg != 0 {
  1090  		a2 = c.aclassreg(p.Reg)
  1091  	}
  1092  
  1093  	// c.ctxt.Logf("oplook %v %d %d %d %d\n", p, a1, a2, a3, a4, a5, a6)
  1094  	ops := oprange[p.As&obj.AMask]
  1095  	c1 := &xcmp[a1]
  1096  	c2 := &xcmp[a2]
  1097  	c3 := &xcmp[a3]
  1098  	c4 := &xcmp[a4]
  1099  	c5 := &xcmp[a5]
  1100  	c6 := &xcmp[a6]
  1101  	for i := range ops {
  1102  		op := &ops[i]
  1103  		if c1[op.a1] && c2[op.a2] && c3[op.a3] && c4[op.a4] && c5[op.a5] && c6[op.a6] {
  1104  			p.Optab = uint16(cap(optab) - cap(ops) + i + 1)
  1105  			return op
  1106  		}
  1107  	}
  1108  
  1109  	c.ctxt.Diag("illegal combination %v %v %v %v %v %v %v", p.As, DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4), DRconv(a5), DRconv(a6))
  1110  	prasm(p)
  1111  	if ops == nil {
  1112  		ops = optab
  1113  	}
  1114  	return &ops[0]
  1115  }
  1116  
  1117  // Compare two operand types (ex C_REG, or C_U15CON)
  1118  // and return true if b is compatible with a.
  1119  //
  1120  // Argument comparison isn't reflexitive, so care must be taken.
  1121  // a is the argument type as found in optab, b is the argument as
  1122  // fitted by aclass.
  1123  func cmp(a int, b int) bool {
  1124  	if a == b {
  1125  		return true
  1126  	}
  1127  	switch a {
  1128  
  1129  	case C_SPR:
  1130  		if b == C_LR || b == C_CTR {
  1131  			return true
  1132  		}
  1133  
  1134  	case C_U1CON:
  1135  		return cmp(C_ZCON, b)
  1136  	case C_U2CON:
  1137  		return cmp(C_U1CON, b)
  1138  	case C_U3CON:
  1139  		return cmp(C_U2CON, b)
  1140  	case C_U4CON:
  1141  		return cmp(C_U3CON, b)
  1142  	case C_U5CON:
  1143  		return cmp(C_U4CON, b)
  1144  	case C_U8CON:
  1145  		return cmp(C_U5CON, b)
  1146  	case C_U15CON:
  1147  		return cmp(C_U8CON, b)
  1148  	case C_S16CON:
  1149  		return cmp(C_U15CON, b)
  1150  	case C_U16CON:
  1151  		return cmp(C_U15CON, b)
  1152  	case C_16CON:
  1153  		return cmp(C_S16CON, b) || cmp(C_U16CON, b)
  1154  	case C_U31CON:
  1155  		return cmp(C_U16CON, b)
  1156  	case C_U32CON:
  1157  		return cmp(C_U31CON, b)
  1158  	case C_S32CON:
  1159  		return cmp(C_U31CON, b) || cmp(C_S16CON, b)
  1160  	case C_32CON:
  1161  		return cmp(C_S32CON, b) || cmp(C_U32CON, b)
  1162  	case C_S34CON:
  1163  		return cmp(C_32CON, b)
  1164  	case C_64CON:
  1165  		return cmp(C_S34CON, b)
  1166  
  1167  	case C_LACON:
  1168  		return cmp(C_SACON, b)
  1169  
  1170  	case C_SOREG:
  1171  		return cmp(C_ZOREG, b)
  1172  
  1173  	case C_LOREG:
  1174  		return cmp(C_SOREG, b)
  1175  
  1176  	case C_XOREG:
  1177  		return cmp(C_REG, b) || cmp(C_ZOREG, b)
  1178  
  1179  	// An even/odd register input always matches the regular register types.
  1180  	case C_REG:
  1181  		return cmp(C_REGP, b) || (b == C_ZCON && r0iszero != 0)
  1182  	case C_FREG:
  1183  		return cmp(C_FREGP, b)
  1184  	case C_VSREG:
  1185  		/* Allow any VR argument as a VSR operand. */
  1186  		return cmp(C_VSREGP, b) || cmp(C_VREG, b)
  1187  
  1188  	case C_ANY:
  1189  		return true
  1190  	}
  1191  
  1192  	return false
  1193  }
  1194  
  1195  // Used when sorting the optab. Sorting is
  1196  // done in a way so that the best choice of
  1197  // opcode/operand combination is considered first.
  1198  func optabLess(i, j int) bool {
  1199  	p1 := &optab[i]
  1200  	p2 := &optab[j]
  1201  	n := int(p1.as) - int(p2.as)
  1202  	// same opcode
  1203  	if n != 0 {
  1204  		return n < 0
  1205  	}
  1206  	// Consider those that generate fewer
  1207  	// instructions first.
  1208  	n = int(p1.size) - int(p2.size)
  1209  	if n != 0 {
  1210  		return n < 0
  1211  	}
  1212  	// operand order should match
  1213  	// better choices first
  1214  	n = int(p1.a1) - int(p2.a1)
  1215  	if n != 0 {
  1216  		return n < 0
  1217  	}
  1218  	n = int(p1.a2) - int(p2.a2)
  1219  	if n != 0 {
  1220  		return n < 0
  1221  	}
  1222  	n = int(p1.a3) - int(p2.a3)
  1223  	if n != 0 {
  1224  		return n < 0
  1225  	}
  1226  	n = int(p1.a4) - int(p2.a4)
  1227  	if n != 0 {
  1228  		return n < 0
  1229  	}
  1230  	n = int(p1.a5) - int(p2.a5)
  1231  	if n != 0 {
  1232  		return n < 0
  1233  	}
  1234  	n = int(p1.a6) - int(p2.a6)
  1235  	if n != 0 {
  1236  		return n < 0
  1237  	}
  1238  	return false
  1239  }
  1240  
  1241  // Add an entry to the opcode table for
  1242  // a new opcode b0 with the same operand combinations
  1243  // as opcode a.
  1244  func opset(a, b0 obj.As) {
  1245  	oprange[a&obj.AMask] = oprange[b0]
  1246  }
  1247  
  1248  // Determine if the build configuration requires a TOC pointer.
  1249  // It is assumed this always called after buildop.
  1250  func NeedTOCpointer(ctxt *obj.Link) bool {
  1251  	return !pfxEnabled && ctxt.Flag_shared
  1252  }
  1253  
  1254  // Build the opcode table
  1255  func buildop(ctxt *obj.Link) {
  1256  	// Limit PC-relative prefix instruction usage to supported and tested targets.
  1257  	pfxEnabled = buildcfg.GOPPC64 >= 10 && buildcfg.GOOS == "linux"
  1258  	cfg := fmt.Sprintf("power%d/%s/%s", buildcfg.GOPPC64, buildcfg.GOARCH, buildcfg.GOOS)
  1259  	if cfg == buildOpCfg {
  1260  		// Already initialized to correct OS/cpu; stop now.
  1261  		// This happens in the cmd/asm tests,
  1262  		// each of which re-initializes the arch.
  1263  		return
  1264  	}
  1265  	buildOpCfg = cfg
  1266  
  1267  	// Configure the optab entries which may generate prefix opcodes.
  1268  	prefixOptab := make([]Optab, 0, len(prefixableOptab))
  1269  	for _, entry := range prefixableOptab {
  1270  		entry := entry
  1271  		if pfxEnabled && buildcfg.GOPPC64 >= entry.minGOPPC64 {
  1272  			// Enable prefix opcode generation and resize.
  1273  			entry.ispfx = true
  1274  			entry.size = entry.pfxsize
  1275  		}
  1276  		prefixOptab = append(prefixOptab, entry.Optab)
  1277  
  1278  	}
  1279  
  1280  	for i := 0; i < C_NCLASS; i++ {
  1281  		for n := 0; n < C_NCLASS; n++ {
  1282  			if cmp(n, i) {
  1283  				xcmp[i][n] = true
  1284  			}
  1285  		}
  1286  	}
  1287  
  1288  	// Append the generated entries, sort, and fill out oprange.
  1289  	optab = make([]Optab, 0, len(optabBase)+len(optabGen)+len(prefixOptab))
  1290  	optab = append(optab, optabBase...)
  1291  	optab = append(optab, optabGen...)
  1292  	optab = append(optab, prefixOptab...)
  1293  	sort.Slice(optab, optabLess)
  1294  
  1295  	for i := range optab {
  1296  		// Use the legacy assembler function if none provided.
  1297  		if optab[i].asmout == nil {
  1298  			optab[i].asmout = asmout
  1299  		}
  1300  	}
  1301  
  1302  	for i := 0; i < len(optab); {
  1303  		r := optab[i].as
  1304  		r0 := r & obj.AMask
  1305  		start := i
  1306  		for i < len(optab) && optab[i].as == r {
  1307  			i++
  1308  		}
  1309  		oprange[r0] = optab[start:i]
  1310  
  1311  		switch r {
  1312  		default:
  1313  			if !opsetGen(r) {
  1314  				ctxt.Diag("unknown op in build: %v", r)
  1315  				log.Fatalf("instruction missing from switch in asm9.go:buildop: %v", r)
  1316  			}
  1317  
  1318  		case ADCBF: /* unary indexed: op (b+a); op (b) */
  1319  			opset(ADCBI, r0)
  1320  
  1321  			opset(ADCBST, r0)
  1322  			opset(ADCBT, r0)
  1323  			opset(ADCBTST, r0)
  1324  			opset(ADCBZ, r0)
  1325  			opset(AICBI, r0)
  1326  
  1327  		case ASTDCCC: /* indexed store: op s,(b+a); op s,(b) */
  1328  			opset(ASTWCCC, r0)
  1329  			opset(ASTHCCC, r0)
  1330  			opset(ASTBCCC, r0)
  1331  
  1332  		case AREM: /* macro */
  1333  			opset(AREM, r0)
  1334  
  1335  		case AREMU:
  1336  			opset(AREMU, r0)
  1337  
  1338  		case AREMD:
  1339  			opset(AREMDU, r0)
  1340  
  1341  		case AMULLW:
  1342  			opset(AMULLD, r0)
  1343  
  1344  		case ADIVW: /* op Rb[,Ra],Rd */
  1345  			opset(AMULHW, r0)
  1346  
  1347  			opset(AMULHWCC, r0)
  1348  			opset(AMULHWU, r0)
  1349  			opset(AMULHWUCC, r0)
  1350  			opset(AMULLWCC, r0)
  1351  			opset(AMULLWVCC, r0)
  1352  			opset(AMULLWV, r0)
  1353  			opset(ADIVWCC, r0)
  1354  			opset(ADIVWV, r0)
  1355  			opset(ADIVWVCC, r0)
  1356  			opset(ADIVWU, r0)
  1357  			opset(ADIVWUCC, r0)
  1358  			opset(ADIVWUV, r0)
  1359  			opset(ADIVWUVCC, r0)
  1360  			opset(AMODUD, r0)
  1361  			opset(AMODUW, r0)
  1362  			opset(AMODSD, r0)
  1363  			opset(AMODSW, r0)
  1364  			opset(AADDCC, r0)
  1365  			opset(AADDCV, r0)
  1366  			opset(AADDCVCC, r0)
  1367  			opset(AADDV, r0)
  1368  			opset(AADDVCC, r0)
  1369  			opset(AADDE, r0)
  1370  			opset(AADDECC, r0)
  1371  			opset(AADDEV, r0)
  1372  			opset(AADDEVCC, r0)
  1373  			opset(AMULHD, r0)
  1374  			opset(AMULHDCC, r0)
  1375  			opset(AMULHDU, r0)
  1376  			opset(AMULHDUCC, r0)
  1377  			opset(AMULLDCC, r0)
  1378  			opset(AMULLDVCC, r0)
  1379  			opset(AMULLDV, r0)
  1380  			opset(ADIVD, r0)
  1381  			opset(ADIVDCC, r0)
  1382  			opset(ADIVDE, r0)
  1383  			opset(ADIVDEU, r0)
  1384  			opset(ADIVDECC, r0)
  1385  			opset(ADIVDEUCC, r0)
  1386  			opset(ADIVDVCC, r0)
  1387  			opset(ADIVDV, r0)
  1388  			opset(ADIVDU, r0)
  1389  			opset(ADIVDUV, r0)
  1390  			opset(ADIVDUVCC, r0)
  1391  			opset(ADIVDUCC, r0)
  1392  
  1393  		case ACRAND:
  1394  			opset(ACRANDN, r0)
  1395  			opset(ACREQV, r0)
  1396  			opset(ACRNAND, r0)
  1397  			opset(ACRNOR, r0)
  1398  			opset(ACROR, r0)
  1399  			opset(ACRORN, r0)
  1400  			opset(ACRXOR, r0)
  1401  
  1402  		case APOPCNTD: /* popcntd, popcntw, popcntb, cnttzw, cnttzd */
  1403  			opset(APOPCNTW, r0)
  1404  			opset(APOPCNTB, r0)
  1405  			opset(ACNTTZW, r0)
  1406  			opset(ACNTTZWCC, r0)
  1407  			opset(ACNTTZD, r0)
  1408  			opset(ACNTTZDCC, r0)
  1409  
  1410  		case ACOPY: /* copy, paste. */
  1411  			opset(APASTECC, r0)
  1412  
  1413  		case AMADDHD: /* maddhd, maddhdu, maddld */
  1414  			opset(AMADDHDU, r0)
  1415  			opset(AMADDLD, r0)
  1416  
  1417  		case AMOVBZ: /* lbz, stz, rlwm(r/r), lhz, lha, stz, and x variants */
  1418  			opset(AMOVH, r0)
  1419  			opset(AMOVHZ, r0)
  1420  
  1421  		case AMOVBZU: /* lbz[x]u, stb[x]u, lhz[x]u, lha[x]u, sth[u]x, ld[x]u, std[u]x */
  1422  			opset(AMOVHU, r0)
  1423  
  1424  			opset(AMOVHZU, r0)
  1425  			opset(AMOVWU, r0)
  1426  			opset(AMOVWZU, r0)
  1427  			opset(AMOVDU, r0)
  1428  			opset(AMOVMW, r0)
  1429  
  1430  		case ALVEBX: /* lvebx, lvehx, lvewx, lvx, lvxl, lvsl, lvsr */
  1431  			opset(ALVEHX, r0)
  1432  			opset(ALVEWX, r0)
  1433  			opset(ALVX, r0)
  1434  			opset(ALVXL, r0)
  1435  			opset(ALVSL, r0)
  1436  			opset(ALVSR, r0)
  1437  
  1438  		case ASTVEBX: /* stvebx, stvehx, stvewx, stvx, stvxl */
  1439  			opset(ASTVEHX, r0)
  1440  			opset(ASTVEWX, r0)
  1441  			opset(ASTVX, r0)
  1442  			opset(ASTVXL, r0)
  1443  
  1444  		case AVAND: /* vand, vandc, vnand */
  1445  			opset(AVAND, r0)
  1446  			opset(AVANDC, r0)
  1447  			opset(AVNAND, r0)
  1448  
  1449  		case AVMRGOW: /* vmrgew, vmrgow */
  1450  			opset(AVMRGEW, r0)
  1451  
  1452  		case AVOR: /* vor, vorc, vxor, vnor, veqv */
  1453  			opset(AVOR, r0)
  1454  			opset(AVORC, r0)
  1455  			opset(AVXOR, r0)
  1456  			opset(AVNOR, r0)
  1457  			opset(AVEQV, r0)
  1458  
  1459  		case AVADDUM: /* vaddubm, vadduhm, vadduwm, vaddudm, vadduqm */
  1460  			opset(AVADDUBM, r0)
  1461  			opset(AVADDUHM, r0)
  1462  			opset(AVADDUWM, r0)
  1463  			opset(AVADDUDM, r0)
  1464  			opset(AVADDUQM, r0)
  1465  
  1466  		case AVADDCU: /* vaddcuq, vaddcuw */
  1467  			opset(AVADDCUQ, r0)
  1468  			opset(AVADDCUW, r0)
  1469  
  1470  		case AVADDUS: /* vaddubs, vadduhs, vadduws */
  1471  			opset(AVADDUBS, r0)
  1472  			opset(AVADDUHS, r0)
  1473  			opset(AVADDUWS, r0)
  1474  
  1475  		case AVADDSS: /* vaddsbs, vaddshs, vaddsws */
  1476  			opset(AVADDSBS, r0)
  1477  			opset(AVADDSHS, r0)
  1478  			opset(AVADDSWS, r0)
  1479  
  1480  		case AVADDE: /* vaddeuqm, vaddecuq */
  1481  			opset(AVADDEUQM, r0)
  1482  			opset(AVADDECUQ, r0)
  1483  
  1484  		case AVSUBUM: /* vsububm, vsubuhm, vsubuwm, vsubudm, vsubuqm */
  1485  			opset(AVSUBUBM, r0)
  1486  			opset(AVSUBUHM, r0)
  1487  			opset(AVSUBUWM, r0)
  1488  			opset(AVSUBUDM, r0)
  1489  			opset(AVSUBUQM, r0)
  1490  
  1491  		case AVSUBCU: /* vsubcuq, vsubcuw */
  1492  			opset(AVSUBCUQ, r0)
  1493  			opset(AVSUBCUW, r0)
  1494  
  1495  		case AVSUBUS: /* vsububs, vsubuhs, vsubuws */
  1496  			opset(AVSUBUBS, r0)
  1497  			opset(AVSUBUHS, r0)
  1498  			opset(AVSUBUWS, r0)
  1499  
  1500  		case AVSUBSS: /* vsubsbs, vsubshs, vsubsws */
  1501  			opset(AVSUBSBS, r0)
  1502  			opset(AVSUBSHS, r0)
  1503  			opset(AVSUBSWS, r0)
  1504  
  1505  		case AVSUBE: /* vsubeuqm, vsubecuq */
  1506  			opset(AVSUBEUQM, r0)
  1507  			opset(AVSUBECUQ, r0)
  1508  
  1509  		case AVMULESB: /* vmulesb, vmulosb, vmuleub, vmuloub, vmulosh, vmulouh, vmulesw, vmulosw, vmuleuw, vmulouw, vmuluwm */
  1510  			opset(AVMULOSB, r0)
  1511  			opset(AVMULEUB, r0)
  1512  			opset(AVMULOUB, r0)
  1513  			opset(AVMULESH, r0)
  1514  			opset(AVMULOSH, r0)
  1515  			opset(AVMULEUH, r0)
  1516  			opset(AVMULOUH, r0)
  1517  			opset(AVMULESW, r0)
  1518  			opset(AVMULOSW, r0)
  1519  			opset(AVMULEUW, r0)
  1520  			opset(AVMULOUW, r0)
  1521  			opset(AVMULUWM, r0)
  1522  		case AVPMSUM: /* vpmsumb, vpmsumh, vpmsumw, vpmsumd */
  1523  			opset(AVPMSUMB, r0)
  1524  			opset(AVPMSUMH, r0)
  1525  			opset(AVPMSUMW, r0)
  1526  			opset(AVPMSUMD, r0)
  1527  
  1528  		case AVR: /* vrlb, vrlh, vrlw, vrld */
  1529  			opset(AVRLB, r0)
  1530  			opset(AVRLH, r0)
  1531  			opset(AVRLW, r0)
  1532  			opset(AVRLD, r0)
  1533  
  1534  		case AVS: /* vs[l,r], vs[l,r]o, vs[l,r]b, vs[l,r]h, vs[l,r]w, vs[l,r]d */
  1535  			opset(AVSLB, r0)
  1536  			opset(AVSLH, r0)
  1537  			opset(AVSLW, r0)
  1538  			opset(AVSL, r0)
  1539  			opset(AVSLO, r0)
  1540  			opset(AVSRB, r0)
  1541  			opset(AVSRH, r0)
  1542  			opset(AVSRW, r0)
  1543  			opset(AVSR, r0)
  1544  			opset(AVSRO, r0)
  1545  			opset(AVSLD, r0)
  1546  			opset(AVSRD, r0)
  1547  
  1548  		case AVSA: /* vsrab, vsrah, vsraw, vsrad */
  1549  			opset(AVSRAB, r0)
  1550  			opset(AVSRAH, r0)
  1551  			opset(AVSRAW, r0)
  1552  			opset(AVSRAD, r0)
  1553  
  1554  		case AVSOI: /* vsldoi */
  1555  			opset(AVSLDOI, r0)
  1556  
  1557  		case AVCLZ: /* vclzb, vclzh, vclzw, vclzd */
  1558  			opset(AVCLZB, r0)
  1559  			opset(AVCLZH, r0)
  1560  			opset(AVCLZW, r0)
  1561  			opset(AVCLZD, r0)
  1562  
  1563  		case AVPOPCNT: /* vpopcntb, vpopcnth, vpopcntw, vpopcntd */
  1564  			opset(AVPOPCNTB, r0)
  1565  			opset(AVPOPCNTH, r0)
  1566  			opset(AVPOPCNTW, r0)
  1567  			opset(AVPOPCNTD, r0)
  1568  
  1569  		case AVCMPEQ: /* vcmpequb[.], vcmpequh[.], vcmpequw[.], vcmpequd[.] */
  1570  			opset(AVCMPEQUB, r0)
  1571  			opset(AVCMPEQUBCC, r0)
  1572  			opset(AVCMPEQUH, r0)
  1573  			opset(AVCMPEQUHCC, r0)
  1574  			opset(AVCMPEQUW, r0)
  1575  			opset(AVCMPEQUWCC, r0)
  1576  			opset(AVCMPEQUD, r0)
  1577  			opset(AVCMPEQUDCC, r0)
  1578  
  1579  		case AVCMPGT: /* vcmpgt[u,s]b[.], vcmpgt[u,s]h[.], vcmpgt[u,s]w[.], vcmpgt[u,s]d[.] */
  1580  			opset(AVCMPGTUB, r0)
  1581  			opset(AVCMPGTUBCC, r0)
  1582  			opset(AVCMPGTUH, r0)
  1583  			opset(AVCMPGTUHCC, r0)
  1584  			opset(AVCMPGTUW, r0)
  1585  			opset(AVCMPGTUWCC, r0)
  1586  			opset(AVCMPGTUD, r0)
  1587  			opset(AVCMPGTUDCC, r0)
  1588  			opset(AVCMPGTSB, r0)
  1589  			opset(AVCMPGTSBCC, r0)
  1590  			opset(AVCMPGTSH, r0)
  1591  			opset(AVCMPGTSHCC, r0)
  1592  			opset(AVCMPGTSW, r0)
  1593  			opset(AVCMPGTSWCC, r0)
  1594  			opset(AVCMPGTSD, r0)
  1595  			opset(AVCMPGTSDCC, r0)
  1596  
  1597  		case AVCMPNEZB: /* vcmpnezb[.] */
  1598  			opset(AVCMPNEZBCC, r0)
  1599  			opset(AVCMPNEB, r0)
  1600  			opset(AVCMPNEBCC, r0)
  1601  			opset(AVCMPNEH, r0)
  1602  			opset(AVCMPNEHCC, r0)
  1603  			opset(AVCMPNEW, r0)
  1604  			opset(AVCMPNEWCC, r0)
  1605  
  1606  		case AVPERM: /* vperm */
  1607  			opset(AVPERMXOR, r0)
  1608  			opset(AVPERMR, r0)
  1609  
  1610  		case AVBPERMQ: /* vbpermq, vbpermd */
  1611  			opset(AVBPERMD, r0)
  1612  
  1613  		case AVSEL: /* vsel */
  1614  			opset(AVSEL, r0)
  1615  
  1616  		case AVSPLTB: /* vspltb, vsplth, vspltw */
  1617  			opset(AVSPLTH, r0)
  1618  			opset(AVSPLTW, r0)
  1619  
  1620  		case AVSPLTISB: /* vspltisb, vspltish, vspltisw */
  1621  			opset(AVSPLTISH, r0)
  1622  			opset(AVSPLTISW, r0)
  1623  
  1624  		case AVCIPH: /* vcipher, vcipherlast */
  1625  			opset(AVCIPHER, r0)
  1626  			opset(AVCIPHERLAST, r0)
  1627  
  1628  		case AVNCIPH: /* vncipher, vncipherlast */
  1629  			opset(AVNCIPHER, r0)
  1630  			opset(AVNCIPHERLAST, r0)
  1631  
  1632  		case AVSBOX: /* vsbox */
  1633  			opset(AVSBOX, r0)
  1634  
  1635  		case AVSHASIGMA: /* vshasigmaw, vshasigmad */
  1636  			opset(AVSHASIGMAW, r0)
  1637  			opset(AVSHASIGMAD, r0)
  1638  
  1639  		case ALXVD2X: /* lxvd2x, lxvdsx, lxvw4x, lxvh8x, lxvb16x */
  1640  			opset(ALXVDSX, r0)
  1641  			opset(ALXVW4X, r0)
  1642  			opset(ALXVH8X, r0)
  1643  			opset(ALXVB16X, r0)
  1644  
  1645  		case ALXV: /* lxv */
  1646  			opset(ALXV, r0)
  1647  
  1648  		case ALXVL: /* lxvl, lxvll, lxvx */
  1649  			opset(ALXVLL, r0)
  1650  			opset(ALXVX, r0)
  1651  
  1652  		case ASTXVD2X: /* stxvd2x, stxvdsx, stxvw4x, stxvh8x, stxvb16x */
  1653  			opset(ASTXVW4X, r0)
  1654  			opset(ASTXVH8X, r0)
  1655  			opset(ASTXVB16X, r0)
  1656  
  1657  		case ASTXV: /* stxv */
  1658  			opset(ASTXV, r0)
  1659  
  1660  		case ASTXVL: /* stxvl, stxvll, stvx */
  1661  			opset(ASTXVLL, r0)
  1662  			opset(ASTXVX, r0)
  1663  
  1664  		case ALXSDX: /* lxsdx  */
  1665  			opset(ALXSDX, r0)
  1666  
  1667  		case ASTXSDX: /* stxsdx */
  1668  			opset(ASTXSDX, r0)
  1669  
  1670  		case ALXSIWAX: /* lxsiwax, lxsiwzx  */
  1671  			opset(ALXSIWZX, r0)
  1672  
  1673  		case ASTXSIWX: /* stxsiwx */
  1674  			opset(ASTXSIWX, r0)
  1675  
  1676  		case AMFVSRD: /* mfvsrd, mfvsrwz (and extended mnemonics), mfvsrld */
  1677  			opset(AMFFPRD, r0)
  1678  			opset(AMFVRD, r0)
  1679  			opset(AMFVSRWZ, r0)
  1680  			opset(AMFVSRLD, r0)
  1681  
  1682  		case AMTVSRD: /* mtvsrd, mtvsrwa, mtvsrwz (and extended mnemonics), mtvsrdd, mtvsrws */
  1683  			opset(AMTFPRD, r0)
  1684  			opset(AMTVRD, r0)
  1685  			opset(AMTVSRWA, r0)
  1686  			opset(AMTVSRWZ, r0)
  1687  			opset(AMTVSRWS, r0)
  1688  
  1689  		case AXXLAND:
  1690  			opset(AXXLANDC, r0)
  1691  			opset(AXXLEQV, r0)
  1692  			opset(AXXLNAND, r0)
  1693  			opset(AXXLORC, r0)
  1694  			opset(AXXLNOR, r0)
  1695  			opset(AXXLORQ, r0)
  1696  			opset(AXXLXOR, r0)
  1697  			opset(AXXLOR, r0)
  1698  			opset(AXSMAXJDP, r0)
  1699  			opset(AXSMINJDP, r0)
  1700  
  1701  		case AXXSEL: /* xxsel */
  1702  			opset(AXXSEL, r0)
  1703  
  1704  		case AXXMRGHW: /* xxmrghw, xxmrglw */
  1705  			opset(AXXMRGLW, r0)
  1706  
  1707  		case AXXSPLTW: /* xxspltw */
  1708  			opset(AXXSPLTW, r0)
  1709  
  1710  		case AXXSPLTIB: /* xxspltib */
  1711  			opset(AXXSPLTIB, r0)
  1712  
  1713  		case AXXPERM: /* xxpermdi */
  1714  			opset(AXXPERM, r0)
  1715  
  1716  		case AXXSLDWI: /* xxsldwi */
  1717  			opset(AXXPERMDI, r0)
  1718  			opset(AXXSLDWI, r0)
  1719  
  1720  		case AXXBRQ: /* xxbrq, xxbrd, xxbrw, xxbrh */
  1721  			opset(AXXBRD, r0)
  1722  			opset(AXXBRW, r0)
  1723  			opset(AXXBRH, r0)
  1724  
  1725  		case AXSCVDPSP: /* xscvdpsp, xscvspdp, xscvdpspn, xscvspdpn */
  1726  			opset(AXSCVSPDP, r0)
  1727  			opset(AXSCVDPSPN, r0)
  1728  			opset(AXSCVSPDPN, r0)
  1729  
  1730  		case AXVCVDPSP: /* xvcvdpsp, xvcvspdp */
  1731  			opset(AXVCVSPDP, r0)
  1732  
  1733  		case AXSCVDPSXDS: /* xscvdpsxds, xscvdpsxws, xscvdpuxds, xscvdpuxws */
  1734  			opset(AXSCVDPSXWS, r0)
  1735  			opset(AXSCVDPUXDS, r0)
  1736  			opset(AXSCVDPUXWS, r0)
  1737  
  1738  		case AXSCVSXDDP: /* xscvsxddp, xscvuxddp, xscvsxdsp, xscvuxdsp */
  1739  			opset(AXSCVUXDDP, r0)
  1740  			opset(AXSCVSXDSP, r0)
  1741  			opset(AXSCVUXDSP, r0)
  1742  
  1743  		case AXVCVDPSXDS: /* xvcvdpsxds, xvcvdpsxws, xvcvdpuxds, xvcvdpuxws, xvcvspsxds, xvcvspsxws, xvcvspuxds, xvcvspuxws */
  1744  			opset(AXVCVDPSXDS, r0)
  1745  			opset(AXVCVDPSXWS, r0)
  1746  			opset(AXVCVDPUXDS, r0)
  1747  			opset(AXVCVDPUXWS, r0)
  1748  			opset(AXVCVSPSXDS, r0)
  1749  			opset(AXVCVSPSXWS, r0)
  1750  			opset(AXVCVSPUXDS, r0)
  1751  			opset(AXVCVSPUXWS, r0)
  1752  
  1753  		case AXVCVSXDDP: /* xvcvsxddp, xvcvsxwdp, xvcvuxddp, xvcvuxwdp, xvcvsxdsp, xvcvsxwsp, xvcvuxdsp, xvcvuxwsp */
  1754  			opset(AXVCVSXWDP, r0)
  1755  			opset(AXVCVUXDDP, r0)
  1756  			opset(AXVCVUXWDP, r0)
  1757  			opset(AXVCVSXDSP, r0)
  1758  			opset(AXVCVSXWSP, r0)
  1759  			opset(AXVCVUXDSP, r0)
  1760  			opset(AXVCVUXWSP, r0)
  1761  
  1762  		case AAND: /* logical op Rb,Rs,Ra; no literal */
  1763  			opset(AANDN, r0)
  1764  			opset(AANDNCC, r0)
  1765  			opset(AEQV, r0)
  1766  			opset(AEQVCC, r0)
  1767  			opset(ANAND, r0)
  1768  			opset(ANANDCC, r0)
  1769  			opset(ANOR, r0)
  1770  			opset(ANORCC, r0)
  1771  			opset(AORCC, r0)
  1772  			opset(AORN, r0)
  1773  			opset(AORNCC, r0)
  1774  			opset(AXORCC, r0)
  1775  
  1776  		case AADDME: /* op Ra, Rd */
  1777  			opset(AADDMECC, r0)
  1778  
  1779  			opset(AADDMEV, r0)
  1780  			opset(AADDMEVCC, r0)
  1781  			opset(AADDZE, r0)
  1782  			opset(AADDZECC, r0)
  1783  			opset(AADDZEV, r0)
  1784  			opset(AADDZEVCC, r0)
  1785  			opset(ASUBME, r0)
  1786  			opset(ASUBMECC, r0)
  1787  			opset(ASUBMEV, r0)
  1788  			opset(ASUBMEVCC, r0)
  1789  			opset(ASUBZE, r0)
  1790  			opset(ASUBZECC, r0)
  1791  			opset(ASUBZEV, r0)
  1792  			opset(ASUBZEVCC, r0)
  1793  
  1794  		case AADDC:
  1795  			opset(AADDCCC, r0)
  1796  
  1797  		case ABEQ:
  1798  			opset(ABGE, r0)
  1799  			opset(ABGT, r0)
  1800  			opset(ABLE, r0)
  1801  			opset(ABLT, r0)
  1802  			opset(ABNE, r0)
  1803  			opset(ABVC, r0)
  1804  			opset(ABVS, r0)
  1805  
  1806  		case ABR:
  1807  			opset(ABL, r0)
  1808  
  1809  		case ABC:
  1810  			opset(ABCL, r0)
  1811  
  1812  		case ABDNZ:
  1813  			opset(ABDZ, r0)
  1814  
  1815  		case AEXTSB: /* op Rs, Ra */
  1816  			opset(AEXTSBCC, r0)
  1817  
  1818  			opset(AEXTSH, r0)
  1819  			opset(AEXTSHCC, r0)
  1820  			opset(ACNTLZW, r0)
  1821  			opset(ACNTLZWCC, r0)
  1822  			opset(ACNTLZD, r0)
  1823  			opset(AEXTSW, r0)
  1824  			opset(AEXTSWCC, r0)
  1825  			opset(ACNTLZDCC, r0)
  1826  
  1827  		case AFABS: /* fop [s,]d */
  1828  			opset(AFABSCC, r0)
  1829  
  1830  			opset(AFNABS, r0)
  1831  			opset(AFNABSCC, r0)
  1832  			opset(AFNEG, r0)
  1833  			opset(AFNEGCC, r0)
  1834  			opset(AFRSP, r0)
  1835  			opset(AFRSPCC, r0)
  1836  			opset(AFCTIW, r0)
  1837  			opset(AFCTIWCC, r0)
  1838  			opset(AFCTIWZ, r0)
  1839  			opset(AFCTIWZCC, r0)
  1840  			opset(AFCTID, r0)
  1841  			opset(AFCTIDCC, r0)
  1842  			opset(AFCTIDZ, r0)
  1843  			opset(AFCTIDZCC, r0)
  1844  			opset(AFCFID, r0)
  1845  			opset(AFCFIDCC, r0)
  1846  			opset(AFCFIDU, r0)
  1847  			opset(AFCFIDUCC, r0)
  1848  			opset(AFCFIDS, r0)
  1849  			opset(AFCFIDSCC, r0)
  1850  			opset(AFRES, r0)
  1851  			opset(AFRESCC, r0)
  1852  			opset(AFRIM, r0)
  1853  			opset(AFRIMCC, r0)
  1854  			opset(AFRIP, r0)
  1855  			opset(AFRIPCC, r0)
  1856  			opset(AFRIZ, r0)
  1857  			opset(AFRIZCC, r0)
  1858  			opset(AFRIN, r0)
  1859  			opset(AFRINCC, r0)
  1860  			opset(AFRSQRTE, r0)
  1861  			opset(AFRSQRTECC, r0)
  1862  			opset(AFSQRT, r0)
  1863  			opset(AFSQRTCC, r0)
  1864  			opset(AFSQRTS, r0)
  1865  			opset(AFSQRTSCC, r0)
  1866  
  1867  		case AFADD:
  1868  			opset(AFADDS, r0)
  1869  			opset(AFADDCC, r0)
  1870  			opset(AFADDSCC, r0)
  1871  			opset(AFCPSGN, r0)
  1872  			opset(AFCPSGNCC, r0)
  1873  			opset(AFDIV, r0)
  1874  			opset(AFDIVS, r0)
  1875  			opset(AFDIVCC, r0)
  1876  			opset(AFDIVSCC, r0)
  1877  			opset(AFSUB, r0)
  1878  			opset(AFSUBS, r0)
  1879  			opset(AFSUBCC, r0)
  1880  			opset(AFSUBSCC, r0)
  1881  			opset(ADADD, r0)
  1882  			opset(ADDIV, r0)
  1883  			opset(ADSUB, r0)
  1884  
  1885  		case ADADDQ:
  1886  			opset(ADDIVQ, r0)
  1887  			opset(ADSUBQ, r0)
  1888  
  1889  		case AFMADD:
  1890  			opset(AFMADDCC, r0)
  1891  			opset(AFMADDS, r0)
  1892  			opset(AFMADDSCC, r0)
  1893  			opset(AFMSUB, r0)
  1894  			opset(AFMSUBCC, r0)
  1895  			opset(AFMSUBS, r0)
  1896  			opset(AFMSUBSCC, r0)
  1897  			opset(AFNMADD, r0)
  1898  			opset(AFNMADDCC, r0)
  1899  			opset(AFNMADDS, r0)
  1900  			opset(AFNMADDSCC, r0)
  1901  			opset(AFNMSUB, r0)
  1902  			opset(AFNMSUBCC, r0)
  1903  			opset(AFNMSUBS, r0)
  1904  			opset(AFNMSUBSCC, r0)
  1905  			opset(AFSEL, r0)
  1906  			opset(AFSELCC, r0)
  1907  
  1908  		case AFMUL:
  1909  			opset(AFMULS, r0)
  1910  			opset(AFMULCC, r0)
  1911  			opset(AFMULSCC, r0)
  1912  			opset(ADMUL, r0)
  1913  
  1914  		case ADMULQ:
  1915  			opset(ADMULQ, r0)
  1916  
  1917  		case AFCMPO:
  1918  			opset(AFCMPU, r0)
  1919  			opset(ADCMPU, r0)
  1920  			opset(ADCMPO, r0)
  1921  
  1922  		case ADCMPOQ:
  1923  			opset(ADCMPUQ, r0)
  1924  
  1925  		case AMTFSB0:
  1926  			opset(AMTFSB0CC, r0)
  1927  			opset(AMTFSB1, r0)
  1928  			opset(AMTFSB1CC, r0)
  1929  
  1930  		case ANEG: /* op [Ra,] Rd */
  1931  			opset(ANEGCC, r0)
  1932  
  1933  			opset(ANEGV, r0)
  1934  			opset(ANEGVCC, r0)
  1935  
  1936  		case AOR: /* or/xor Rb,Rs,Ra; ori/xori $uimm,Rs,R */
  1937  			opset(AXOR, r0)
  1938  
  1939  		case AORIS: /* oris/xoris $uimm,Rs,Ra */
  1940  			opset(AXORIS, r0)
  1941  
  1942  		case ASLW:
  1943  			opset(ASLWCC, r0)
  1944  			opset(ASRW, r0)
  1945  			opset(ASRWCC, r0)
  1946  			opset(AROTLW, r0)
  1947  
  1948  		case ASLD:
  1949  			opset(ASLDCC, r0)
  1950  			opset(ASRD, r0)
  1951  			opset(ASRDCC, r0)
  1952  			opset(AROTL, r0)
  1953  
  1954  		case ASRAW: /* sraw Rb,Rs,Ra; srawi sh,Rs,Ra */
  1955  			opset(ASRAWCC, r0)
  1956  
  1957  		case AEXTSWSLI:
  1958  			opset(AEXTSWSLICC, r0)
  1959  
  1960  		case ASRAD: /* sraw Rb,Rs,Ra; srawi sh,Rs,Ra */
  1961  			opset(ASRADCC, r0)
  1962  
  1963  		case ASUB: /* SUB Ra,Rb,Rd => subf Rd,ra,rb */
  1964  			opset(ASUB, r0)
  1965  
  1966  			opset(ASUBCC, r0)
  1967  			opset(ASUBV, r0)
  1968  			opset(ASUBVCC, r0)
  1969  			opset(ASUBCCC, r0)
  1970  			opset(ASUBCV, r0)
  1971  			opset(ASUBCVCC, r0)
  1972  			opset(ASUBE, r0)
  1973  			opset(ASUBECC, r0)
  1974  			opset(ASUBEV, r0)
  1975  			opset(ASUBEVCC, r0)
  1976  
  1977  		case ASYNC:
  1978  			opset(AISYNC, r0)
  1979  			opset(ALWSYNC, r0)
  1980  			opset(APTESYNC, r0)
  1981  			opset(ATLBSYNC, r0)
  1982  
  1983  		case ARLWNM:
  1984  			opset(ARLWNMCC, r0)
  1985  			opset(ARLWMI, r0)
  1986  			opset(ARLWMICC, r0)
  1987  
  1988  		case ARLDMI:
  1989  			opset(ARLDMICC, r0)
  1990  			opset(ARLDIMI, r0)
  1991  			opset(ARLDIMICC, r0)
  1992  
  1993  		case ARLDC:
  1994  			opset(ARLDCCC, r0)
  1995  
  1996  		case ARLDCL:
  1997  			opset(ARLDCR, r0)
  1998  			opset(ARLDCLCC, r0)
  1999  			opset(ARLDCRCC, r0)
  2000  
  2001  		case ARLDICL:
  2002  			opset(ARLDICLCC, r0)
  2003  			opset(ARLDICR, r0)
  2004  			opset(ARLDICRCC, r0)
  2005  			opset(ARLDIC, r0)
  2006  			opset(ARLDICCC, r0)
  2007  			opset(ACLRLSLDI, r0)
  2008  
  2009  		case AFMOVD:
  2010  			opset(AFMOVDCC, r0)
  2011  			opset(AFMOVDU, r0)
  2012  			opset(AFMOVS, r0)
  2013  			opset(AFMOVSU, r0)
  2014  
  2015  		case ALDAR:
  2016  			opset(ALBAR, r0)
  2017  			opset(ALHAR, r0)
  2018  			opset(ALWAR, r0)
  2019  
  2020  		case ASYSCALL: /* just the op; flow of control */
  2021  			opset(ARFI, r0)
  2022  
  2023  			opset(ARFCI, r0)
  2024  			opset(ARFID, r0)
  2025  			opset(AHRFID, r0)
  2026  
  2027  		case AMOVHBR:
  2028  			opset(AMOVWBR, r0)
  2029  			opset(AMOVDBR, r0)
  2030  
  2031  		case ASLBMFEE:
  2032  			opset(ASLBMFEV, r0)
  2033  
  2034  		case ATW:
  2035  			opset(ATD, r0)
  2036  
  2037  		case ATLBIE:
  2038  			opset(ASLBIE, r0)
  2039  			opset(ATLBIEL, r0)
  2040  
  2041  		case AEIEIO:
  2042  			opset(ASLBIA, r0)
  2043  
  2044  		case ACMP:
  2045  			opset(ACMPW, r0)
  2046  
  2047  		case ACMPU:
  2048  			opset(ACMPWU, r0)
  2049  
  2050  		case ACMPB:
  2051  			opset(ACMPB, r0)
  2052  
  2053  		case AFTDIV:
  2054  			opset(AFTDIV, r0)
  2055  
  2056  		case AFTSQRT:
  2057  			opset(AFTSQRT, r0)
  2058  
  2059  		case AMOVW: /* load/store/move word with sign extension; move 32-bit literals  */
  2060  			opset(AMOVWZ, r0) /* Same as above, but zero extended */
  2061  
  2062  		case AVCLZLSBB:
  2063  			opset(AVCTZLSBB, r0)
  2064  
  2065  		case AADD,
  2066  			AADDIS,
  2067  			AANDCC, /* and. Rb,Rs,Ra; andi. $uimm,Rs,Ra */
  2068  			AANDISCC,
  2069  			AFMOVSX,
  2070  			AFMOVSZ,
  2071  			ALSW,
  2072  			AMOVD,  /* load/store/move 64-bit values, including 32-bit literals with/without sign-extension */
  2073  			AMOVB,  /* macro: move byte with sign extension */
  2074  			AMOVBU, /* macro: move byte with sign extension & update */
  2075  			AMOVFL,
  2076  			/* op $s[,r2],r3; op r1[,r2],r3; no cc/v */
  2077  			ASUBC, /* op r1,$s,r3; op r1[,r2],r3 */
  2078  			ASTSW,
  2079  			ASLBMTE,
  2080  			AWORD,
  2081  			ADWORD,
  2082  			ADARN,
  2083  			AVMSUMUDM,
  2084  			AADDEX,
  2085  			ACMPEQB,
  2086  			ACLRLSLWI,
  2087  			AMTVSRDD,
  2088  			APNOP,
  2089  			AISEL,
  2090  			ASETB,
  2091  			obj.ANOP,
  2092  			obj.ATEXT,
  2093  			obj.AUNDEF,
  2094  			obj.AFUNCDATA,
  2095  			obj.APCALIGN,
  2096  			obj.APCDATA,
  2097  			obj.ADUFFZERO,
  2098  			obj.ADUFFCOPY:
  2099  			break
  2100  		}
  2101  	}
  2102  }
  2103  
  2104  func OPVXX1(o uint32, xo uint32, oe uint32) uint32 {
  2105  	return o<<26 | xo<<1 | oe<<11
  2106  }
  2107  
  2108  func OPVXX2(o uint32, xo uint32, oe uint32) uint32 {
  2109  	return o<<26 | xo<<2 | oe<<11
  2110  }
  2111  
  2112  func OPVXX2VA(o uint32, xo uint32, oe uint32) uint32 {
  2113  	return o<<26 | xo<<2 | oe<<16
  2114  }
  2115  
  2116  func OPVXX3(o uint32, xo uint32, oe uint32) uint32 {
  2117  	return o<<26 | xo<<3 | oe<<11
  2118  }
  2119  
  2120  func OPVXX4(o uint32, xo uint32, oe uint32) uint32 {
  2121  	return o<<26 | xo<<4 | oe<<11
  2122  }
  2123  
  2124  func OPDQ(o uint32, xo uint32, oe uint32) uint32 {
  2125  	return o<<26 | xo | oe<<4
  2126  }
  2127  
  2128  func OPVX(o uint32, xo uint32, oe uint32, rc uint32) uint32 {
  2129  	return o<<26 | xo | oe<<11 | rc&1
  2130  }
  2131  
  2132  func OPVC(o uint32, xo uint32, oe uint32, rc uint32) uint32 {
  2133  	return o<<26 | xo | oe<<11 | (rc&1)<<10
  2134  }
  2135  
  2136  func OPVCC(o uint32, xo uint32, oe uint32, rc uint32) uint32 {
  2137  	return o<<26 | xo<<1 | oe<<10 | rc&1
  2138  }
  2139  
  2140  /* Generate MD-form opcode */
  2141  func OPMD(o, xo, rc uint32) uint32 {
  2142  	return o<<26 | xo<<2 | rc&1
  2143  }
  2144  
  2145  /* the order is dest, a/s, b/imm for both arithmetic and logical operations. */
  2146  func AOP_RRR(op uint32, d uint32, a uint32, b uint32) uint32 {
  2147  	return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11
  2148  }
  2149  
  2150  /* VX-form 2-register operands, r/none/r */
  2151  func AOP_RR(op uint32, d uint32, a uint32) uint32 {
  2152  	return op | (d&31)<<21 | (a&31)<<11
  2153  }
  2154  
  2155  /* VA-form 4-register operands */
  2156  func AOP_RRRR(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 {
  2157  	return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c&31)<<6
  2158  }
  2159  
  2160  func AOP_IRR(op uint32, d uint32, a uint32, simm uint32) uint32 {
  2161  	return op | (d&31)<<21 | (a&31)<<16 | simm&0xFFFF
  2162  }
  2163  
  2164  /* VX-form 2-register + UIM operands */
  2165  func AOP_VIRR(op uint32, d uint32, a uint32, simm uint32) uint32 {
  2166  	return op | (d&31)<<21 | (simm&0xFFFF)<<16 | (a&31)<<11
  2167  }
  2168  
  2169  /* VX-form 2-register + ST + SIX operands */
  2170  func AOP_IIRR(op uint32, d uint32, a uint32, sbit uint32, simm uint32) uint32 {
  2171  	return op | (d&31)<<21 | (a&31)<<16 | (sbit&1)<<15 | (simm&0xF)<<11
  2172  }
  2173  
  2174  /* VA-form 3-register + SHB operands */
  2175  func AOP_IRRR(op uint32, d uint32, a uint32, b uint32, simm uint32) uint32 {
  2176  	return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (simm&0xF)<<6
  2177  }
  2178  
  2179  /* VX-form 1-register + SIM operands */
  2180  func AOP_IR(op uint32, d uint32, simm uint32) uint32 {
  2181  	return op | (d&31)<<21 | (simm&31)<<16
  2182  }
  2183  
  2184  /* XX1-form 3-register operands, 1 VSR operand */
  2185  func AOP_XX1(op uint32, r uint32, a uint32, b uint32) uint32 {
  2186  	return op | (r&31)<<21 | (a&31)<<16 | (b&31)<<11 | (r&32)>>5
  2187  }
  2188  
  2189  /* XX2-form 3-register operands, 2 VSR operands */
  2190  func AOP_XX2(op uint32, xt uint32, a uint32, xb uint32) uint32 {
  2191  	return op | (xt&31)<<21 | (a&3)<<16 | (xb&31)<<11 | (xb&32)>>4 | (xt&32)>>5
  2192  }
  2193  
  2194  /* XX3-form 3 VSR operands */
  2195  func AOP_XX3(op uint32, xt uint32, xa uint32, xb uint32) uint32 {
  2196  	return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5
  2197  }
  2198  
  2199  /* XX3-form 3 VSR operands + immediate */
  2200  func AOP_XX3I(op uint32, xt uint32, xa uint32, xb uint32, c uint32) uint32 {
  2201  	return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (c&3)<<8 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5
  2202  }
  2203  
  2204  /* XX4-form, 4 VSR operands */
  2205  func AOP_XX4(op uint32, xt uint32, xa uint32, xb uint32, xc uint32) uint32 {
  2206  	return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (xc&31)<<6 | (xc&32)>>2 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5
  2207  }
  2208  
  2209  /* DQ-form, VSR register, register + offset operands */
  2210  func AOP_DQ(op uint32, xt uint32, a uint32, b uint32) uint32 {
  2211  	/* The EA for this instruction form is (RA) + DQ << 4, where DQ is a 12-bit signed integer. */
  2212  	/* In order to match the output of the GNU objdump (and make the usage in Go asm easier), the */
  2213  	/* instruction is called using the sign extended value (i.e. a valid offset would be -32752 or 32752, */
  2214  	/* not -2047 or 2047), so 'b' needs to be adjusted to the expected 12-bit DQ value. Bear in mind that */
  2215  	/* bits 0 to 3 in 'dq' need to be zero, otherwise this will generate an illegal instruction. */
  2216  	/* If in doubt how this instruction form is encoded, refer to ISA 3.0b, pages 492 and 507. */
  2217  	dq := b >> 4
  2218  	return op | (xt&31)<<21 | (a&31)<<16 | (dq&4095)<<4 | (xt&32)>>2
  2219  }
  2220  
  2221  /* Z23-form, 3-register operands + CY field */
  2222  func AOP_Z23I(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 {
  2223  	return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c&3)<<9
  2224  }
  2225  
  2226  /* X-form, 3-register operands + EH field */
  2227  func AOP_RRRI(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 {
  2228  	return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c & 1)
  2229  }
  2230  
  2231  func LOP_RRR(op uint32, a uint32, s uint32, b uint32) uint32 {
  2232  	return op | (s&31)<<21 | (a&31)<<16 | (b&31)<<11
  2233  }
  2234  
  2235  func LOP_IRR(op uint32, a uint32, s uint32, uimm uint32) uint32 {
  2236  	return op | (s&31)<<21 | (a&31)<<16 | uimm&0xFFFF
  2237  }
  2238  
  2239  func OP_BR(op uint32, li uint32, aa uint32) uint32 {
  2240  	return op | li&0x03FFFFFC | aa<<1
  2241  }
  2242  
  2243  func OP_BC(op uint32, bo uint32, bi uint32, bd uint32, aa uint32) uint32 {
  2244  	return op | (bo&0x1F)<<21 | (bi&0x1F)<<16 | bd&0xFFFC | aa<<1
  2245  }
  2246  
  2247  func OP_BCR(op uint32, bo uint32, bi uint32) uint32 {
  2248  	return op | (bo&0x1F)<<21 | (bi&0x1F)<<16
  2249  }
  2250  
  2251  func OP_RLW(op uint32, a uint32, s uint32, sh uint32, mb uint32, me uint32) uint32 {
  2252  	return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | (mb&31)<<6 | (me&31)<<1
  2253  }
  2254  
  2255  func AOP_EXTSWSLI(op uint32, a uint32, s uint32, sh uint32) uint32 {
  2256  	return op | (a&31)<<21 | (s&31)<<16 | (sh&31)<<11 | ((sh&32)>>5)<<1
  2257  }
  2258  
  2259  func AOP_ISEL(op uint32, t uint32, a uint32, b uint32, bc uint32) uint32 {
  2260  	return op | (t&31)<<21 | (a&31)<<16 | (b&31)<<11 | (bc&0x1F)<<6
  2261  }
  2262  
  2263  /* MD-form 2-register, 2 6-bit immediate operands */
  2264  func AOP_MD(op uint32, a uint32, s uint32, sh uint32, m uint32) uint32 {
  2265  	return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | ((sh&32)>>5)<<1 | (m&31)<<6 | ((m&32)>>5)<<5
  2266  }
  2267  
  2268  /* MDS-form 3-register, 1 6-bit immediate operands. rsh argument is a register. */
  2269  func AOP_MDS(op, to, from, rsh, m uint32) uint32 {
  2270  	return AOP_MD(op, to, from, rsh&31, m)
  2271  }
  2272  
  2273  func AOP_PFX_00_8LS(r, ie uint32) uint32 {
  2274  	return 1<<26 | 0<<24 | 0<<23 | (r&1)<<20 | (ie & 0x3FFFF)
  2275  }
  2276  func AOP_PFX_10_MLS(r, ie uint32) uint32 {
  2277  	return 1<<26 | 2<<24 | 0<<23 | (r&1)<<20 | (ie & 0x3FFFF)
  2278  }
  2279  
  2280  const (
  2281  	/* each rhs is OPVCC(_, _, _, _) */
  2282  	OP_ADD      = 31<<26 | 266<<1 | 0<<10 | 0
  2283  	OP_ADDI     = 14<<26 | 0<<1 | 0<<10 | 0
  2284  	OP_ADDIS    = 15<<26 | 0<<1 | 0<<10 | 0
  2285  	OP_ANDI     = 28<<26 | 0<<1 | 0<<10 | 0
  2286  	OP_EXTSB    = 31<<26 | 954<<1 | 0<<10 | 0
  2287  	OP_EXTSH    = 31<<26 | 922<<1 | 0<<10 | 0
  2288  	OP_EXTSW    = 31<<26 | 986<<1 | 0<<10 | 0
  2289  	OP_ISEL     = 31<<26 | 15<<1 | 0<<10 | 0
  2290  	OP_MCRF     = 19<<26 | 0<<1 | 0<<10 | 0
  2291  	OP_MCRFS    = 63<<26 | 64<<1 | 0<<10 | 0
  2292  	OP_MCRXR    = 31<<26 | 512<<1 | 0<<10 | 0
  2293  	OP_MFCR     = 31<<26 | 19<<1 | 0<<10 | 0
  2294  	OP_MFFS     = 63<<26 | 583<<1 | 0<<10 | 0
  2295  	OP_MFSPR    = 31<<26 | 339<<1 | 0<<10 | 0
  2296  	OP_MFSR     = 31<<26 | 595<<1 | 0<<10 | 0
  2297  	OP_MFSRIN   = 31<<26 | 659<<1 | 0<<10 | 0
  2298  	OP_MTCRF    = 31<<26 | 144<<1 | 0<<10 | 0
  2299  	OP_MTFSF    = 63<<26 | 711<<1 | 0<<10 | 0
  2300  	OP_MTFSFI   = 63<<26 | 134<<1 | 0<<10 | 0
  2301  	OP_MTSPR    = 31<<26 | 467<<1 | 0<<10 | 0
  2302  	OP_MTSR     = 31<<26 | 210<<1 | 0<<10 | 0
  2303  	OP_MTSRIN   = 31<<26 | 242<<1 | 0<<10 | 0
  2304  	OP_MULLW    = 31<<26 | 235<<1 | 0<<10 | 0
  2305  	OP_MULLD    = 31<<26 | 233<<1 | 0<<10 | 0
  2306  	OP_OR       = 31<<26 | 444<<1 | 0<<10 | 0
  2307  	OP_ORI      = 24<<26 | 0<<1 | 0<<10 | 0
  2308  	OP_ORIS     = 25<<26 | 0<<1 | 0<<10 | 0
  2309  	OP_XORI     = 26<<26 | 0<<1 | 0<<10 | 0
  2310  	OP_XORIS    = 27<<26 | 0<<1 | 0<<10 | 0
  2311  	OP_RLWINM   = 21<<26 | 0<<1 | 0<<10 | 0
  2312  	OP_RLWNM    = 23<<26 | 0<<1 | 0<<10 | 0
  2313  	OP_SUBF     = 31<<26 | 40<<1 | 0<<10 | 0
  2314  	OP_RLDIC    = 30<<26 | 4<<1 | 0<<10 | 0
  2315  	OP_RLDICR   = 30<<26 | 2<<1 | 0<<10 | 0
  2316  	OP_RLDICL   = 30<<26 | 0<<1 | 0<<10 | 0
  2317  	OP_RLDCL    = 30<<26 | 8<<1 | 0<<10 | 0
  2318  	OP_EXTSWSLI = 31<<26 | 445<<2
  2319  	OP_SETB     = 31<<26 | 128<<1
  2320  )
  2321  
  2322  func pfxadd(rt, ra int16, r uint32, imm32 int64) (uint32, uint32) {
  2323  	return AOP_PFX_10_MLS(r, uint32(imm32>>16)), AOP_IRR(14<<26, uint32(rt), uint32(ra), uint32(imm32))
  2324  }
  2325  
  2326  func pfxload(a obj.As, reg int16, base int16, r uint32) (uint32, uint32) {
  2327  	switch a {
  2328  	case AMOVH:
  2329  		return AOP_PFX_10_MLS(r, 0), AOP_IRR(42<<26, uint32(reg), uint32(base), 0)
  2330  	case AMOVW:
  2331  		return AOP_PFX_00_8LS(r, 0), AOP_IRR(41<<26, uint32(reg), uint32(base), 0)
  2332  	case AMOVD:
  2333  		return AOP_PFX_00_8LS(r, 0), AOP_IRR(57<<26, uint32(reg), uint32(base), 0)
  2334  	case AMOVBZ, AMOVB:
  2335  		return AOP_PFX_10_MLS(r, 0), AOP_IRR(34<<26, uint32(reg), uint32(base), 0)
  2336  	case AMOVHZ:
  2337  		return AOP_PFX_10_MLS(r, 0), AOP_IRR(40<<26, uint32(reg), uint32(base), 0)
  2338  	case AMOVWZ:
  2339  		return AOP_PFX_10_MLS(r, 0), AOP_IRR(32<<26, uint32(reg), uint32(base), 0)
  2340  	case AFMOVS:
  2341  		return AOP_PFX_10_MLS(r, 0), AOP_IRR(48<<26, uint32(reg), uint32(base), 0)
  2342  	case AFMOVD:
  2343  		return AOP_PFX_10_MLS(r, 0), AOP_IRR(50<<26, uint32(reg), uint32(base), 0)
  2344  	}
  2345  	log.Fatalf("Error no pfxload for %v\n", a)
  2346  	return 0, 0
  2347  }
  2348  
  2349  func pfxstore(a obj.As, reg int16, base int16, r uint32) (uint32, uint32) {
  2350  	switch a {
  2351  	case AMOVD:
  2352  		return AOP_PFX_00_8LS(r, 0), AOP_IRR(61<<26, uint32(reg), uint32(base), 0)
  2353  	case AMOVBZ, AMOVB:
  2354  		return AOP_PFX_10_MLS(r, 0), AOP_IRR(38<<26, uint32(reg), uint32(base), 0)
  2355  	case AMOVHZ, AMOVH:
  2356  		return AOP_PFX_10_MLS(r, 0), AOP_IRR(44<<26, uint32(reg), uint32(base), 0)
  2357  	case AMOVWZ, AMOVW:
  2358  		return AOP_PFX_10_MLS(r, 0), AOP_IRR(36<<26, uint32(reg), uint32(base), 0)
  2359  	case AFMOVS:
  2360  		return AOP_PFX_10_MLS(r, 0), AOP_IRR(52<<26, uint32(reg), uint32(base), 0)
  2361  	case AFMOVD:
  2362  		return AOP_PFX_10_MLS(r, 0), AOP_IRR(54<<26, uint32(reg), uint32(base), 0)
  2363  	}
  2364  	log.Fatalf("Error no pfxstore for %v\n", a)
  2365  	return 0, 0
  2366  }
  2367  
  2368  func oclass(a *obj.Addr) int {
  2369  	return int(a.Class) - 1
  2370  }
  2371  
  2372  const (
  2373  	D_FORM = iota
  2374  	DS_FORM
  2375  )
  2376  
  2377  // This function determines when a non-indexed load or store is D or
  2378  // DS form for use in finding the size of the offset field in the instruction.
  2379  // The size is needed when setting the offset value in the instruction
  2380  // and when generating relocation for that field.
  2381  // DS form instructions include: ld, ldu, lwa, std, stdu.  All other
  2382  // loads and stores with an offset field are D form.  This function should
  2383  // only be called with the same opcodes as are handled by opstore and opload.
  2384  func (c *ctxt9) opform(insn uint32) int {
  2385  	switch insn {
  2386  	default:
  2387  		c.ctxt.Diag("bad insn in loadform: %x", insn)
  2388  	case OPVCC(58, 0, 0, 0), // ld
  2389  		OPVCC(58, 0, 0, 1),        // ldu
  2390  		OPVCC(58, 0, 0, 0) | 1<<1, // lwa
  2391  		OPVCC(62, 0, 0, 0),        // std
  2392  		OPVCC(62, 0, 0, 1):        //stdu
  2393  		return DS_FORM
  2394  	case OP_ADDI, // add
  2395  		OPVCC(32, 0, 0, 0), // lwz
  2396  		OPVCC(33, 0, 0, 0), // lwzu
  2397  		OPVCC(34, 0, 0, 0), // lbz
  2398  		OPVCC(35, 0, 0, 0), // lbzu
  2399  		OPVCC(40, 0, 0, 0), // lhz
  2400  		OPVCC(41, 0, 0, 0), // lhzu
  2401  		OPVCC(42, 0, 0, 0), // lha
  2402  		OPVCC(43, 0, 0, 0), // lhau
  2403  		OPVCC(46, 0, 0, 0), // lmw
  2404  		OPVCC(48, 0, 0, 0), // lfs
  2405  		OPVCC(49, 0, 0, 0), // lfsu
  2406  		OPVCC(50, 0, 0, 0), // lfd
  2407  		OPVCC(51, 0, 0, 0), // lfdu
  2408  		OPVCC(36, 0, 0, 0), // stw
  2409  		OPVCC(37, 0, 0, 0), // stwu
  2410  		OPVCC(38, 0, 0, 0), // stb
  2411  		OPVCC(39, 0, 0, 0), // stbu
  2412  		OPVCC(44, 0, 0, 0), // sth
  2413  		OPVCC(45, 0, 0, 0), // sthu
  2414  		OPVCC(47, 0, 0, 0), // stmw
  2415  		OPVCC(52, 0, 0, 0), // stfs
  2416  		OPVCC(53, 0, 0, 0), // stfsu
  2417  		OPVCC(54, 0, 0, 0), // stfd
  2418  		OPVCC(55, 0, 0, 0): // stfdu
  2419  		return D_FORM
  2420  	}
  2421  	return 0
  2422  }
  2423  
  2424  // Encode instructions and create relocation for accessing s+d according to the
  2425  // instruction op with source or destination (as appropriate) register reg.
  2426  // The caller must call c.cursym.AddRel(c.ctxt, rel) when finished editing rel.
  2427  func (c *ctxt9) symbolAccess(s *obj.LSym, d int64, reg int16, op uint32, reuse bool) (o1, o2 uint32, rel obj.Reloc) {
  2428  	if c.ctxt.Headtype == objabi.Haix {
  2429  		// Every symbol access must be made via a TOC anchor.
  2430  		c.ctxt.Diag("symbolAccess called for %s", s.Name)
  2431  	}
  2432  	var base uint32
  2433  	form := c.opform(op)
  2434  	if c.ctxt.Flag_shared {
  2435  		base = REG_R2
  2436  	} else {
  2437  		base = REG_R0
  2438  	}
  2439  	// If reg can be reused when computing the symbol address,
  2440  	// use it instead of REGTMP.
  2441  	if !reuse {
  2442  		o1 = AOP_IRR(OP_ADDIS, REGTMP, base, 0)
  2443  		o2 = AOP_IRR(op, uint32(reg), REGTMP, 0)
  2444  	} else {
  2445  		o1 = AOP_IRR(OP_ADDIS, uint32(reg), base, 0)
  2446  		o2 = AOP_IRR(op, uint32(reg), uint32(reg), 0)
  2447  	}
  2448  	var typ objabi.RelocType
  2449  	if c.ctxt.Flag_shared {
  2450  		switch form {
  2451  		case D_FORM:
  2452  			typ = objabi.R_ADDRPOWER_TOCREL
  2453  		case DS_FORM:
  2454  			typ = objabi.R_ADDRPOWER_TOCREL_DS
  2455  		}
  2456  	} else {
  2457  		switch form {
  2458  		case D_FORM:
  2459  			typ = objabi.R_ADDRPOWER
  2460  		case DS_FORM:
  2461  			typ = objabi.R_ADDRPOWER_DS
  2462  		}
  2463  	}
  2464  	rel = obj.Reloc{
  2465  		Type: typ,
  2466  		Off:  int32(c.pc),
  2467  		Siz:  8,
  2468  		Sym:  s,
  2469  		Add:  d,
  2470  	}
  2471  	return
  2472  }
  2473  
  2474  // Determine the mask begin (mb) and mask end (me) values
  2475  // for a valid word rotate mask. A valid 32 bit mask is of
  2476  // the form 1+0*1+ or 0*1+0*.
  2477  //
  2478  // Note, me is inclusive.
  2479  func decodeMask32(mask uint32) (mb, me uint32, valid bool) {
  2480  	mb = uint32(bits.LeadingZeros32(mask))
  2481  	me = uint32(32 - bits.TrailingZeros32(mask))
  2482  	mbn := uint32(bits.LeadingZeros32(^mask))
  2483  	men := uint32(32 - bits.TrailingZeros32(^mask))
  2484  	// Check for a wrapping mask (e.g bits at 0 and 31)
  2485  	if mb == 0 && me == 32 {
  2486  		// swap the inverted values
  2487  		mb, me = men, mbn
  2488  	}
  2489  
  2490  	// Validate mask is of the binary form 1+0*1+ or 0*1+0*
  2491  	// Isolate rightmost 1 (if none 0) and add.
  2492  	v := mask
  2493  	vp := (v & -v) + v
  2494  	// Likewise, check for the wrapping (inverted) case.
  2495  	vn := ^v
  2496  	vpn := (vn & -vn) + vn
  2497  	return mb, (me - 1) & 31, (v&vp == 0 || vn&vpn == 0) && v != 0
  2498  }
  2499  
  2500  // Decompose a mask of contiguous bits into a begin (mb) and
  2501  // end (me) value.
  2502  //
  2503  // 64b mask values cannot wrap on any valid PPC64 instruction.
  2504  // Only masks of the form 0*1+0* are valid.
  2505  //
  2506  // Note, me is inclusive.
  2507  func decodeMask64(mask int64) (mb, me uint32, valid bool) {
  2508  	m := uint64(mask)
  2509  	mb = uint32(bits.LeadingZeros64(m))
  2510  	me = uint32(64 - bits.TrailingZeros64(m))
  2511  	valid = ((m&-m)+m)&m == 0 && m != 0
  2512  	return mb, (me - 1) & 63, valid
  2513  }
  2514  
  2515  // Load the lower 16 bits of a constant into register r.
  2516  func loadl16(r int, d int64) uint32 {
  2517  	v := uint16(d)
  2518  	if v == 0 {
  2519  		// Avoid generating "ori r,r,0", r != 0. Instead, generate the architecturally preferred nop.
  2520  		// For example, "ori r31,r31,0" is a special execution serializing nop on Power10 called "exser".
  2521  		return NOP
  2522  	}
  2523  	return LOP_IRR(OP_ORI, uint32(r), uint32(r), uint32(v))
  2524  }
  2525  
  2526  // Load the upper 16 bits of a 32b constant into register r.
  2527  func loadu32(r int, d int64) uint32 {
  2528  	v := int32(d >> 16)
  2529  	if isuint32(uint64(d)) {
  2530  		return LOP_IRR(OP_ORIS, uint32(r), REGZERO, uint32(v))
  2531  	}
  2532  	return AOP_IRR(OP_ADDIS, uint32(r), REGZERO, uint32(v))
  2533  }
  2534  
  2535  func high16adjusted(d int32) uint16 {
  2536  	if d&0x8000 != 0 {
  2537  		return uint16((d >> 16) + 1)
  2538  	}
  2539  	return uint16(d >> 16)
  2540  }
  2541  
  2542  func asmout(c *ctxt9, p *obj.Prog, o *Optab, out *[5]uint32) {
  2543  	o1 := uint32(0)
  2544  	o2 := uint32(0)
  2545  	o3 := uint32(0)
  2546  	o4 := uint32(0)
  2547  	o5 := uint32(0)
  2548  
  2549  	//print("%v => case %d\n", p, o->type);
  2550  	switch o.type_ {
  2551  	default:
  2552  		c.ctxt.Diag("unknown type %d", o.type_)
  2553  		prasm(p)
  2554  
  2555  	case 0: /* pseudo ops */
  2556  		break
  2557  
  2558  	case 2: /* int/cr/fp op Rb,[Ra],Rd */
  2559  		r := int(p.Reg)
  2560  
  2561  		if r == 0 {
  2562  			r = int(p.To.Reg)
  2563  		}
  2564  		o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg))
  2565  
  2566  	case 3: /* mov $soreg/16con, r ==> addi/ori $i,reg',r */
  2567  		d := c.vregoff(&p.From)
  2568  
  2569  		v := int32(d)
  2570  		r := int(p.From.Reg)
  2571  
  2572  		if r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0 && (r != 0 || v != 0) {
  2573  			c.ctxt.Diag("literal operation on R0\n%v", p)
  2574  		}
  2575  		if int64(int16(d)) == d {
  2576  			// MOVD $int16, Ry  or  MOVD $offset(Rx), Ry
  2577  			o1 = AOP_IRR(uint32(OP_ADDI), uint32(p.To.Reg), uint32(r), uint32(v))
  2578  		} else {
  2579  			// MOVD $uint16, Ry
  2580  			if int64(uint16(d)) != d || (r != 0 && r != REGZERO) {
  2581  				c.ctxt.Diag("Rule expects a uint16 constant load. got:\n%v", p)
  2582  			}
  2583  			o1 = LOP_IRR(uint32(OP_ORI), uint32(p.To.Reg), uint32(0), uint32(v))
  2584  		}
  2585  
  2586  	case 4: /* add/mul $scon,[r1],r2 */
  2587  		v := c.regoff(&p.From)
  2588  
  2589  		r := int(p.Reg)
  2590  		if r == 0 {
  2591  			r = int(p.To.Reg)
  2592  		}
  2593  		if r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0 {
  2594  			c.ctxt.Diag("literal operation on R0\n%v", p)
  2595  		}
  2596  		if int32(int16(v)) != v {
  2597  			log.Fatalf("mishandled instruction %v", p)
  2598  		}
  2599  		o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
  2600  
  2601  	case 5: /* syscall */
  2602  		o1 = c.oprrr(p.As)
  2603  
  2604  	case 6: /* logical op Rb,[Rs,]Ra; no literal */
  2605  		r := int(p.Reg)
  2606  
  2607  		if r == 0 {
  2608  			r = int(p.To.Reg)
  2609  		}
  2610  		// AROTL and AROTLW are extended mnemonics, which map to RLDCL and RLWNM.
  2611  		switch p.As {
  2612  		case AROTL:
  2613  			o1 = AOP_MD(OP_RLDCL, uint32(p.To.Reg), uint32(r), uint32(p.From.Reg), uint32(0))
  2614  		case AROTLW:
  2615  			o1 = OP_RLW(OP_RLWNM, uint32(p.To.Reg), uint32(r), uint32(p.From.Reg), 0, 31)
  2616  		default:
  2617  			if p.As == AOR && p.From.Type == obj.TYPE_CONST && p.From.Offset == 0 {
  2618  				// Compile "OR $0, Rx, Ry" into ori. If Rx == Ry == 0, this is the preferred
  2619  				// hardware no-op. This happens because $0 matches C_REG before C_ZCON.
  2620  				o1 = LOP_IRR(OP_ORI, uint32(p.To.Reg), uint32(r), 0)
  2621  			} else {
  2622  				o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg))
  2623  			}
  2624  		}
  2625  
  2626  	case 7: /* mov r, soreg ==> stw o(r) */
  2627  		r := int(p.To.Reg)
  2628  		v := c.regoff(&p.To)
  2629  		if int32(int16(v)) != v {
  2630  			log.Fatalf("mishandled instruction %v", p)
  2631  		}
  2632  		// Offsets in DS form stores must be a multiple of 4
  2633  		inst := c.opstore(p.As)
  2634  		if c.opform(inst) == DS_FORM && v&0x3 != 0 {
  2635  			log.Fatalf("invalid offset for DS form load/store %v", p)
  2636  		}
  2637  		o1 = AOP_IRR(inst, uint32(p.From.Reg), uint32(r), uint32(v))
  2638  
  2639  	case 8: /* mov soreg, r ==> lbz/lhz/lwz o(r), lbz o(r) + extsb r,r */
  2640  		r := int(p.From.Reg)
  2641  		v := c.regoff(&p.From)
  2642  		if int32(int16(v)) != v {
  2643  			log.Fatalf("mishandled instruction %v", p)
  2644  		}
  2645  		// Offsets in DS form loads must be a multiple of 4
  2646  		inst := c.opload(p.As)
  2647  		if c.opform(inst) == DS_FORM && v&0x3 != 0 {
  2648  			log.Fatalf("invalid offset for DS form load/store %v", p)
  2649  		}
  2650  		o1 = AOP_IRR(inst, uint32(p.To.Reg), uint32(r), uint32(v))
  2651  
  2652  		// Sign extend MOVB operations. This is ignored for other cases (o.size == 4).
  2653  		o2 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0)
  2654  
  2655  	case 9: /* RLDC Ra, $sh, $mb, Rb */
  2656  		sh := uint32(p.RestArgs[0].Addr.Offset) & 0x3F
  2657  		mb := uint32(p.RestArgs[1].Addr.Offset) & 0x3F
  2658  		o1 = AOP_RRR(c.opirr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), (uint32(sh) & 0x1F))
  2659  		o1 |= (sh & 0x20) >> 4 // sh[5] is placed in bit 1.
  2660  		o1 |= (mb & 0x1F) << 6 // mb[0:4] is placed in bits 6-10.
  2661  		o1 |= (mb & 0x20)      // mb[5] is placed in bit 5
  2662  
  2663  	case 10: /* sub Ra,[Rb],Rd => subf Rd,Ra,Rb */
  2664  		r := int(p.Reg)
  2665  
  2666  		if r == 0 {
  2667  			r = int(p.To.Reg)
  2668  		}
  2669  		o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(r))
  2670  
  2671  	case 11: /* br/bl bra */
  2672  		v := int32(0)
  2673  
  2674  		if p.To.Target() != nil {
  2675  			v = int32(p.To.Target().Pc - p.Pc)
  2676  			if v&03 != 0 {
  2677  				c.ctxt.Diag("odd branch target address\n%v", p)
  2678  				v &^= 03
  2679  			}
  2680  
  2681  			if v < -(1<<25) || v >= 1<<24 {
  2682  				c.ctxt.Diag("branch too far\n%v", p)
  2683  			}
  2684  		}
  2685  
  2686  		o1 = OP_BR(c.opirr(p.As), uint32(v), 0)
  2687  		if p.To.Sym != nil {
  2688  			v += int32(p.To.Offset)
  2689  			if v&03 != 0 {
  2690  				c.ctxt.Diag("odd branch target address\n%v", p)
  2691  				v &^= 03
  2692  			}
  2693  			c.cursym.AddRel(c.ctxt, obj.Reloc{
  2694  				Type: objabi.R_CALLPOWER,
  2695  				Off:  int32(c.pc),
  2696  				Siz:  4,
  2697  				Sym:  p.To.Sym,
  2698  				Add:  int64(v),
  2699  			})
  2700  		}
  2701  		o2 = NOP // nop, sometimes overwritten by ld r2, 24(r1) when dynamic linking
  2702  
  2703  	case 13: /* mov[bhwd]{z,} r,r */
  2704  		// This needs to handle "MOV* $0, Rx".  This shows up because $0 also
  2705  		// matches C_REG if r0iszero. This happens because C_REG sorts before C_U16CON
  2706  		// TODO: fix the above behavior and cleanup this exception.
  2707  		if p.From.Type == obj.TYPE_CONST {
  2708  			o1 = LOP_IRR(OP_ADDI, REGZERO, uint32(p.To.Reg), 0)
  2709  			break
  2710  		}
  2711  		if p.To.Type == obj.TYPE_CONST {
  2712  			c.ctxt.Diag("cannot move into constant 0\n%v", p)
  2713  		}
  2714  
  2715  		switch p.As {
  2716  		case AMOVB:
  2717  			o1 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.From.Reg), 0)
  2718  		case AMOVBZ:
  2719  			o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.From.Reg), 0, 24, 31)
  2720  		case AMOVH:
  2721  			o1 = LOP_RRR(OP_EXTSH, uint32(p.To.Reg), uint32(p.From.Reg), 0)
  2722  		case AMOVHZ:
  2723  			o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.From.Reg), 0, 16, 31)
  2724  		case AMOVW:
  2725  			o1 = LOP_RRR(OP_EXTSW, uint32(p.To.Reg), uint32(p.From.Reg), 0)
  2726  		case AMOVWZ:
  2727  			o1 = OP_RLW(OP_RLDIC, uint32(p.To.Reg), uint32(p.From.Reg), 0, 0, 0) | 1<<5 /* MB=32 */
  2728  		case AMOVD:
  2729  			o1 = LOP_RRR(OP_OR, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.From.Reg))
  2730  		default:
  2731  			c.ctxt.Diag("internal: bad register move/truncation\n%v", p)
  2732  		}
  2733  
  2734  	case 14: /* rldc[lr] Rb,Rs,$mask,Ra -- left, right give different masks */
  2735  		r := uint32(p.Reg)
  2736  
  2737  		if r == 0 {
  2738  			r = uint32(p.To.Reg)
  2739  		}
  2740  		d := c.vregoff(p.GetFrom3())
  2741  		switch p.As {
  2742  
  2743  		// These opcodes expect a mask operand that has to be converted into the
  2744  		// appropriate operand.  The way these were defined, not all valid masks are possible.
  2745  		// Left here for compatibility in case they were used or generated.
  2746  		case ARLDCL, ARLDCLCC:
  2747  			mb, me, valid := decodeMask64(d)
  2748  			if me != 63 || !valid {
  2749  				c.ctxt.Diag("invalid mask for rotate: %x (end != bit 63)\n%v", uint64(d), p)
  2750  			}
  2751  			o1 = AOP_MDS(c.oprrr(p.As), uint32(p.To.Reg), r, uint32(p.From.Reg), mb)
  2752  
  2753  		case ARLDCR, ARLDCRCC:
  2754  			mb, me, valid := decodeMask64(d)
  2755  			if mb != 0 || !valid {
  2756  				c.ctxt.Diag("invalid mask for rotate: %x (start != 0)\n%v", uint64(d), p)
  2757  			}
  2758  			o1 = AOP_MDS(c.oprrr(p.As), uint32(p.To.Reg), r, uint32(p.From.Reg), me)
  2759  
  2760  		// These opcodes use a shift count like the ppc64 asm, no mask conversion done
  2761  		case ARLDICR, ARLDICRCC:
  2762  			me := uint32(d)
  2763  			sh := c.regoff(&p.From)
  2764  			if me < 0 || me > 63 || sh > 63 {
  2765  				c.ctxt.Diag("Invalid me or sh for RLDICR: %x %x\n%v", int(d), sh, p)
  2766  			}
  2767  			o1 = AOP_MD(c.oprrr(p.As), uint32(p.To.Reg), r, uint32(sh), me)
  2768  
  2769  		case ARLDICL, ARLDICLCC, ARLDIC, ARLDICCC:
  2770  			mb := uint32(d)
  2771  			sh := c.regoff(&p.From)
  2772  			if mb < 0 || mb > 63 || sh > 63 {
  2773  				c.ctxt.Diag("Invalid mb or sh for RLDIC, RLDICL: %x %x\n%v", mb, sh, p)
  2774  			}
  2775  			o1 = AOP_MD(c.oprrr(p.As), uint32(p.To.Reg), r, uint32(sh), mb)
  2776  
  2777  		case ACLRLSLDI:
  2778  			// This is an extended mnemonic defined in the ISA section C.8.1
  2779  			// clrlsldi ra,rs,b,n --> rldic ra,rs,n,b-n
  2780  			// It maps onto RLDIC so is directly generated here based on the operands from
  2781  			// the clrlsldi.
  2782  			n := int32(d)
  2783  			b := c.regoff(&p.From)
  2784  			if n > b || b > 63 {
  2785  				c.ctxt.Diag("Invalid n or b for CLRLSLDI: %x %x\n%v", n, b, p)
  2786  			}
  2787  			o1 = AOP_MD(OP_RLDIC, uint32(p.To.Reg), uint32(r), uint32(n), uint32(b)-uint32(n))
  2788  
  2789  		default:
  2790  			c.ctxt.Diag("unexpected op in rldc case\n%v", p)
  2791  		}
  2792  
  2793  	case 16: /* bc bo,bi,bra */
  2794  		a := 0
  2795  
  2796  		r := int(p.Reg)
  2797  
  2798  		if p.From.Type == obj.TYPE_CONST {
  2799  			a = int(c.regoff(&p.From))
  2800  		} else if p.From.Type == obj.TYPE_REG {
  2801  			if r != 0 {
  2802  				c.ctxt.Diag("unexpected register setting for branch with CR: %d\n", r)
  2803  			}
  2804  			// BI values for the CR
  2805  			switch p.From.Reg {
  2806  			case REG_CR0:
  2807  				r = BI_CR0
  2808  			case REG_CR1:
  2809  				r = BI_CR1
  2810  			case REG_CR2:
  2811  				r = BI_CR2
  2812  			case REG_CR3:
  2813  				r = BI_CR3
  2814  			case REG_CR4:
  2815  				r = BI_CR4
  2816  			case REG_CR5:
  2817  				r = BI_CR5
  2818  			case REG_CR6:
  2819  				r = BI_CR6
  2820  			case REG_CR7:
  2821  				r = BI_CR7
  2822  			default:
  2823  				c.ctxt.Diag("unrecognized register: expecting CR\n")
  2824  			}
  2825  		}
  2826  		v := int32(0)
  2827  		if p.To.Target() != nil {
  2828  			v = int32(p.To.Target().Pc - p.Pc)
  2829  		}
  2830  		if v&03 != 0 {
  2831  			c.ctxt.Diag("odd branch target address\n%v", p)
  2832  			v &^= 03
  2833  		}
  2834  
  2835  		if v < -(1<<16) || v >= 1<<15 {
  2836  			c.ctxt.Diag("branch too far\n%v", p)
  2837  		}
  2838  		o1 = OP_BC(c.opirr(p.As), uint32(a), uint32(r), uint32(v), 0)
  2839  
  2840  	case 17:
  2841  		var bo int32
  2842  		bi := int(p.Reg)
  2843  
  2844  		if p.From.Reg == REG_CR {
  2845  			c.ctxt.Diag("unrecognized register: expected CR0-CR7\n")
  2846  		}
  2847  		bi = int(p.From.Reg&0x7) * 4
  2848  
  2849  		bo = BO_BCR
  2850  
  2851  		switch p.As {
  2852  		case ABLT:
  2853  			bi += BI_LT
  2854  		case ABGT:
  2855  			bi += BI_GT
  2856  		case ABEQ:
  2857  			bi += BI_EQ
  2858  		case ABNE:
  2859  			bo = BO_NOTBCR
  2860  			bi += BI_EQ
  2861  		case ABLE:
  2862  			bo = BO_NOTBCR
  2863  			bi += BI_GT
  2864  		case ABGE:
  2865  			bo = BO_NOTBCR
  2866  			bi += BI_LT
  2867  		case ABVS:
  2868  			bi += BI_FU
  2869  		case ABVC:
  2870  			bo = BO_NOTBCR
  2871  			bi += BI_FU
  2872  		default:
  2873  			c.ctxt.Diag("unexpected instruction: expecting BGT, BEQ, BNE, BLE, BGE, BVS, BVC \n%v", p)
  2874  
  2875  		}
  2876  		if oclass(&p.To) == C_LR {
  2877  			o1 = OPVCC(19, 16, 0, 0)
  2878  		} else {
  2879  			c.ctxt.Diag("bad optab entry (17): %d\n%v", p.To.Class, p)
  2880  		}
  2881  
  2882  		o1 = OP_BCR(o1, uint32(bo), uint32(bi))
  2883  
  2884  	case 18: /* br/bl (lr/ctr); bc/bcl bo,bi,(lr/ctr) */
  2885  		var v int32
  2886  		var bh uint32 = 0
  2887  		if p.As == ABC || p.As == ABCL {
  2888  			v = c.regoff(&p.From) & 31
  2889  		} else {
  2890  			v = 20 /* unconditional */
  2891  		}
  2892  		r := int(p.Reg)
  2893  		if r == 0 {
  2894  			r = 0
  2895  		}
  2896  		switch oclass(&p.To) {
  2897  		case C_CTR:
  2898  			o1 = OPVCC(19, 528, 0, 0)
  2899  
  2900  		case C_LR:
  2901  			o1 = OPVCC(19, 16, 0, 0)
  2902  
  2903  		default:
  2904  			c.ctxt.Diag("bad optab entry (18): %d\n%v", p.To.Class, p)
  2905  			v = 0
  2906  		}
  2907  
  2908  		// Insert optional branch hint for bclr[l]/bcctr[l]
  2909  		if p.From3Type() != obj.TYPE_NONE {
  2910  			bh = uint32(p.GetFrom3().Offset)
  2911  			if bh == 2 || bh > 3 {
  2912  				log.Fatalf("BH must be 0,1,3 for %v", p)
  2913  			}
  2914  			o1 |= bh << 11
  2915  		}
  2916  
  2917  		if p.As == ABL || p.As == ABCL {
  2918  			o1 |= 1
  2919  		}
  2920  		o1 = OP_BCR(o1, uint32(v), uint32(r))
  2921  
  2922  	case 19: /* mov $lcon,r ==> cau+or */
  2923  		d := c.vregoff(&p.From)
  2924  		if o.ispfx {
  2925  			o1, o2 = pfxadd(p.To.Reg, REG_R0, PFX_R_ABS, d)
  2926  		} else {
  2927  			o1 = loadu32(int(p.To.Reg), d)
  2928  			o2 = LOP_IRR(OP_ORI, uint32(p.To.Reg), uint32(p.To.Reg), uint32(int32(d)))
  2929  		}
  2930  
  2931  	case 20: /* add $ucon,,r | addis $addcon,r,r */
  2932  		v := c.regoff(&p.From)
  2933  
  2934  		r := int(p.Reg)
  2935  		if r == 0 {
  2936  			r = int(p.To.Reg)
  2937  		}
  2938  		o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
  2939  
  2940  	case 21: /* or $u32con,rx[,ry] => oris + ori (similar for xor) */
  2941  		var opu, opl uint32
  2942  		r := uint32(p.Reg)
  2943  		if r == 0 {
  2944  			r = uint32(p.To.Reg)
  2945  		}
  2946  		switch p.As {
  2947  		case AOR:
  2948  			opu, opl = OP_ORIS, OP_ORI
  2949  		case AXOR:
  2950  			opu, opl = OP_XORIS, OP_XORI
  2951  		default:
  2952  			c.ctxt.Diag("unhandled opcode.\n%v", p)
  2953  		}
  2954  		o1 = LOP_IRR(opu, uint32(p.To.Reg), r, uint32(p.From.Offset>>16))
  2955  		o2 = LOP_IRR(opl, uint32(p.To.Reg), uint32(p.To.Reg), uint32(p.From.Offset)&0xFFFF)
  2956  
  2957  	case 22: /* add $lcon/$andcon,r1,r2 ==> oris+ori+add/ori+add, add $s34con,r1 ==> addis+ori+slw+ori+add */
  2958  		if p.To.Reg == REGTMP || p.Reg == REGTMP {
  2959  			c.ctxt.Diag("can't synthesize large constant\n%v", p)
  2960  		}
  2961  		d := c.vregoff(&p.From)
  2962  		r := int(p.Reg)
  2963  		if r == 0 {
  2964  			r = int(p.To.Reg)
  2965  		}
  2966  		if p.From.Sym != nil {
  2967  			c.ctxt.Diag("%v is not supported", p)
  2968  		}
  2969  		if o.ispfx {
  2970  			o1, o2 = pfxadd(int16(p.To.Reg), int16(r), PFX_R_ABS, d)
  2971  		} else if o.size == 8 {
  2972  			o1 = LOP_IRR(OP_ORI, REGTMP, REGZERO, uint32(int32(d)))          // tmp = uint16(d)
  2973  			o2 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r)) // to = tmp + from
  2974  		} else if o.size == 12 {
  2975  			// Note, o1 is ADDIS if d is negative, ORIS otherwise.
  2976  			o1 = loadu32(REGTMP, d)                                          // tmp = d & 0xFFFF0000
  2977  			o2 = loadl16(REGTMP, d)                                          // tmp |= d & 0xFFFF
  2978  			o3 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r)) // to = from + tmp
  2979  		} else {
  2980  			// For backwards compatibility with GOPPC64 < 10, generate 34b constants in register.
  2981  			o1 = LOP_IRR(OP_ADDIS, REGZERO, REGTMP, uint32(d>>32)) // tmp = sign_extend((d>>32)&0xFFFF0000)
  2982  			o2 = loadl16(REGTMP, int64(d>>16))                     // tmp |= (d>>16)&0xFFFF
  2983  			o3 = AOP_MD(OP_RLDICR, REGTMP, REGTMP, 16, 63-16)      // tmp <<= 16
  2984  			o4 = loadl16(REGTMP, int64(uint16(d)))                 // tmp |= d&0xFFFF
  2985  			o5 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
  2986  		}
  2987  
  2988  	case 23: /* and $lcon/$addcon,r1,r2 ==> oris+ori+and/addi+and */
  2989  		if p.To.Reg == REGTMP || p.Reg == REGTMP {
  2990  			c.ctxt.Diag("can't synthesize large constant\n%v", p)
  2991  		}
  2992  		d := c.vregoff(&p.From)
  2993  		r := int(p.Reg)
  2994  		if r == 0 {
  2995  			r = int(p.To.Reg)
  2996  		}
  2997  
  2998  		// With S16CON operand, generate 2 instructions using ADDI for signed value,
  2999  		// with 32CON operand generate 3 instructions.
  3000  		if o.size == 8 {
  3001  			o1 = LOP_IRR(OP_ADDI, REGZERO, REGTMP, uint32(int32(d)))
  3002  			o2 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
  3003  		} else {
  3004  			o1 = loadu32(REGTMP, d)
  3005  			o2 = loadl16(REGTMP, d)
  3006  			o3 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
  3007  		}
  3008  		if p.From.Sym != nil {
  3009  			c.ctxt.Diag("%v is not supported", p)
  3010  		}
  3011  
  3012  	case 24: /* lfd fA,float64(0) -> xxlxor xsA,xsaA,xsaA + fneg for -0 */
  3013  		o1 = AOP_XX3I(c.oprrr(AXXLXOR), uint32(p.To.Reg), uint32(p.To.Reg), uint32(p.To.Reg), uint32(0))
  3014  		// This is needed for -0.
  3015  		if o.size == 8 {
  3016  			o2 = AOP_RRR(c.oprrr(AFNEG), uint32(p.To.Reg), 0, uint32(p.To.Reg))
  3017  		}
  3018  
  3019  	case 25:
  3020  		/* sld[.] $sh,rS,rA -> rldicr[.] $sh,rS,mask(0,63-sh),rA; srd[.] -> rldicl */
  3021  		v := c.regoff(&p.From)
  3022  
  3023  		if v < 0 {
  3024  			v = 0
  3025  		} else if v > 63 {
  3026  			v = 63
  3027  		}
  3028  		r := int(p.Reg)
  3029  		if r == 0 {
  3030  			r = int(p.To.Reg)
  3031  		}
  3032  		var a int
  3033  		op := uint32(0)
  3034  		switch p.As {
  3035  		case ASLD, ASLDCC:
  3036  			a = int(63 - v)
  3037  			op = OP_RLDICR
  3038  
  3039  		case ASRD, ASRDCC:
  3040  			a = int(v)
  3041  			v = 64 - v
  3042  			op = OP_RLDICL
  3043  		case AROTL:
  3044  			a = int(0)
  3045  			op = OP_RLDICL
  3046  		case AEXTSWSLI, AEXTSWSLICC:
  3047  			a = int(v)
  3048  		default:
  3049  			c.ctxt.Diag("unexpected op in sldi case\n%v", p)
  3050  			a = 0
  3051  			o1 = 0
  3052  		}
  3053  
  3054  		if p.As == AEXTSWSLI || p.As == AEXTSWSLICC {
  3055  			o1 = AOP_EXTSWSLI(OP_EXTSWSLI, uint32(r), uint32(p.To.Reg), uint32(v))
  3056  
  3057  		} else {
  3058  			o1 = AOP_MD(op, uint32(p.To.Reg), uint32(r), uint32(v), uint32(a))
  3059  		}
  3060  		if p.As == ASLDCC || p.As == ASRDCC || p.As == AEXTSWSLICC {
  3061  			o1 |= 1 // Set the condition code bit
  3062  		}
  3063  
  3064  	case 26: /* mov $lsext/auto/oreg,,r2 ==> addis+addi */
  3065  		v := c.vregoff(&p.From)
  3066  		r := int(p.From.Reg)
  3067  		var rel *obj.Reloc
  3068  
  3069  		switch p.From.Name {
  3070  		case obj.NAME_EXTERN, obj.NAME_STATIC:
  3071  			// Load a 32 bit constant, or relocation depending on if a symbol is attached
  3072  			var rel1 obj.Reloc
  3073  			o1, o2, rel1 = c.symbolAccess(p.From.Sym, v, p.To.Reg, OP_ADDI, true)
  3074  			rel = &rel1
  3075  		default:
  3076  			// Add a 32 bit offset to a register.
  3077  			o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), uint32(r), uint32(high16adjusted(int32(v))))
  3078  			o2 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), uint32(p.To.Reg), uint32(v))
  3079  		}
  3080  
  3081  		if o.ispfx {
  3082  			if rel == nil {
  3083  				o1, o2 = pfxadd(int16(p.To.Reg), int16(r), PFX_R_ABS, v)
  3084  			} else {
  3085  				o1, o2 = pfxadd(int16(p.To.Reg), REG_R0, PFX_R_PCREL, 0)
  3086  				rel.Type = objabi.R_ADDRPOWER_PCREL34
  3087  			}
  3088  		}
  3089  		if rel != nil {
  3090  			c.cursym.AddRel(c.ctxt, *rel)
  3091  		}
  3092  
  3093  	case 27: /* subc ra,$simm,rd => subfic rd,ra,$simm */
  3094  		v := c.regoff(p.GetFrom3())
  3095  
  3096  		r := int(p.From.Reg)
  3097  		o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
  3098  
  3099  	case 28: /* subc r1,$lcon,r2 ==> cau+or+subfc */
  3100  		if p.To.Reg == REGTMP || p.From.Reg == REGTMP {
  3101  			c.ctxt.Diag("can't synthesize large constant\n%v", p)
  3102  		}
  3103  		v := c.vregoff(p.GetFrom3())
  3104  		o1 = AOP_IRR(OP_ADDIS, REGTMP, REGZERO, uint32(v)>>16)
  3105  		o2 = loadl16(REGTMP, v)
  3106  		o3 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), REGTMP)
  3107  		if p.From.Sym != nil {
  3108  			c.ctxt.Diag("%v is not supported", p)
  3109  		}
  3110  
  3111  	case 29: /* rldic[lr]? $sh,s,$mask,a -- left, right, plain give different masks */
  3112  		sh := uint32(c.regoff(&p.From))
  3113  		d := c.vregoff(p.GetFrom3())
  3114  		mb, me, valid := decodeMask64(d)
  3115  		var a uint32
  3116  		switch p.As {
  3117  		case ARLDC, ARLDCCC:
  3118  			a = mb
  3119  			if me != (63-sh) || !valid {
  3120  				c.ctxt.Diag("invalid mask for shift: %016x (mb=%d,me=%d) (shift %d)\n%v", uint64(d), mb, me, sh, p)
  3121  			}
  3122  
  3123  		case ARLDCL, ARLDCLCC:
  3124  			a = mb
  3125  			if mb != 63 || !valid {
  3126  				c.ctxt.Diag("invalid mask for shift: %016x (mb=%d,me=%d) (shift %d)\n%v", uint64(d), mb, me, sh, p)
  3127  			}
  3128  
  3129  		case ARLDCR, ARLDCRCC:
  3130  			a = me
  3131  			if mb != 0 || !valid {
  3132  				c.ctxt.Diag("invalid mask for shift: %016x (mb=%d,me=%d) (shift %d)\n%v", uint64(d), mb, me, sh, p)
  3133  			}
  3134  
  3135  		default:
  3136  			c.ctxt.Diag("unexpected op in rldic case\n%v", p)
  3137  		}
  3138  		o1 = AOP_MD(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), sh, a)
  3139  
  3140  	case 30: /* rldimi $sh,s,$mask,a */
  3141  		sh := uint32(c.regoff(&p.From))
  3142  		d := c.vregoff(p.GetFrom3())
  3143  
  3144  		// Original opcodes had mask operands which had to be converted to a shift count as expected by
  3145  		// the ppc64 asm.
  3146  		switch p.As {
  3147  		case ARLDMI, ARLDMICC:
  3148  			mb, me, valid := decodeMask64(d)
  3149  			if me != (63-sh) || !valid {
  3150  				c.ctxt.Diag("invalid mask for shift: %x %x (shift %d)\n%v", uint64(d), me, sh, p)
  3151  			}
  3152  			o1 = AOP_MD(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), sh, mb)
  3153  
  3154  		// Opcodes with shift count operands.
  3155  		case ARLDIMI, ARLDIMICC:
  3156  			o1 = AOP_MD(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), sh, uint32(d))
  3157  		}
  3158  
  3159  	case 31: /* dword */
  3160  		d := c.vregoff(&p.From)
  3161  
  3162  		if c.ctxt.Arch.ByteOrder == binary.BigEndian {
  3163  			o1 = uint32(d >> 32)
  3164  			o2 = uint32(d)
  3165  		} else {
  3166  			o1 = uint32(d)
  3167  			o2 = uint32(d >> 32)
  3168  		}
  3169  
  3170  		if p.From.Sym != nil {
  3171  			c.cursym.AddRel(c.ctxt, obj.Reloc{
  3172  				Type: objabi.R_ADDR,
  3173  				Off:  int32(c.pc),
  3174  				Siz:  8,
  3175  				Sym:  p.From.Sym,
  3176  				Add:  p.From.Offset,
  3177  			})
  3178  			o2 = 0
  3179  			o1 = o2
  3180  		}
  3181  
  3182  	case 32: /* fmul frc,fra,frd */
  3183  		r := int(p.Reg)
  3184  
  3185  		if r == 0 {
  3186  			r = int(p.To.Reg)
  3187  		}
  3188  		o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0) | (uint32(p.From.Reg)&31)<<6
  3189  
  3190  	case 33: /* fabs [frb,]frd; fmr. frb,frd */
  3191  		r := int(p.From.Reg)
  3192  
  3193  		if oclass(&p.From) == C_NONE {
  3194  			r = int(p.To.Reg)
  3195  		}
  3196  		o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), 0, uint32(r))
  3197  
  3198  	case 34: /* FMADDx fra,frb,frc,frt (t=a*c±b) */
  3199  		o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) | (uint32(p.GetFrom3().Reg)&31)<<6
  3200  
  3201  	case 35: /* mov r,lext/lauto/loreg ==> cau $(v>>16),sb,r'; store o(r') */
  3202  		v := c.regoff(&p.To)
  3203  		r := int(p.To.Reg)
  3204  		// Offsets in DS form stores must be a multiple of 4
  3205  		if o.ispfx {
  3206  			o1, o2 = pfxstore(p.As, p.From.Reg, int16(r), PFX_R_ABS)
  3207  			o1 |= uint32((v >> 16) & 0x3FFFF)
  3208  			o2 |= uint32(v & 0xFFFF)
  3209  		} else {
  3210  			inst := c.opstore(p.As)
  3211  			if c.opform(inst) == DS_FORM && v&0x3 != 0 {
  3212  				log.Fatalf("invalid offset for DS form load/store %v", p)
  3213  			}
  3214  			o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v)))
  3215  			o2 = AOP_IRR(inst, uint32(p.From.Reg), REGTMP, uint32(v))
  3216  		}
  3217  
  3218  	case 36: /* mov b/bz/h/hz lext/lauto/lreg,r ==> lbz+extsb/lbz/lha/lhz etc */
  3219  		v := c.regoff(&p.From)
  3220  		r := int(p.From.Reg)
  3221  
  3222  		if o.ispfx {
  3223  			o1, o2 = pfxload(p.As, p.To.Reg, int16(r), PFX_R_ABS)
  3224  			o1 |= uint32((v >> 16) & 0x3FFFF)
  3225  			o2 |= uint32(v & 0xFFFF)
  3226  		} else {
  3227  			if o.a6 == C_REG {
  3228  				// Reuse the base register when loading a GPR (C_REG) to avoid
  3229  				// using REGTMP (R31) when possible.
  3230  				o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), uint32(r), uint32(high16adjusted(v)))
  3231  				o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), uint32(p.To.Reg), uint32(v))
  3232  			} else {
  3233  				o1 = AOP_IRR(OP_ADDIS, uint32(REGTMP), uint32(r), uint32(high16adjusted(v)))
  3234  				o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), uint32(REGTMP), uint32(v))
  3235  			}
  3236  		}
  3237  
  3238  		// Sign extend MOVB if needed
  3239  		o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0)
  3240  
  3241  	case 40: /* word */
  3242  		o1 = uint32(c.regoff(&p.From))
  3243  
  3244  	case 41: /* stswi */
  3245  		if p.To.Type == obj.TYPE_MEM && p.To.Index == 0 && p.To.Offset != 0 {
  3246  			c.ctxt.Diag("Invalid addressing mode used in index type instruction: %v", p.As)
  3247  		}
  3248  
  3249  		o1 = AOP_RRR(c.opirr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), 0) | (uint32(c.regoff(p.GetFrom3()))&0x7F)<<11
  3250  
  3251  	case 42: /* lswi */
  3252  		if p.From.Type == obj.TYPE_MEM && p.From.Index == 0 && p.From.Offset != 0 {
  3253  			c.ctxt.Diag("Invalid addressing mode used in index type instruction: %v", p.As)
  3254  		}
  3255  		o1 = AOP_RRR(c.opirr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), 0) | (uint32(c.regoff(p.GetFrom3()))&0x7F)<<11
  3256  
  3257  	case 43: /* data cache instructions: op (Ra+[Rb]), [th|l] */
  3258  		/* TH field for dcbt/dcbtst: */
  3259  		/* 0 = Block access - program will soon access EA. */
  3260  		/* 8-15 = Stream access - sequence of access (data stream). See section 4.3.2 of the ISA for details. */
  3261  		/* 16 = Block access - program will soon make a transient access to EA. */
  3262  		/* 17 = Block access - program will not access EA for a long time. */
  3263  
  3264  		/* L field for dcbf: */
  3265  		/* 0 = invalidates the block containing EA in all processors. */
  3266  		/* 1 = same as 0, but with limited scope (i.e. block in the current processor will not be reused soon). */
  3267  		/* 3 = same as 1, but with even more limited scope (i.e. block in the current processor primary cache will not be reused soon). */
  3268  		if p.To.Type == obj.TYPE_NONE {
  3269  			o1 = AOP_RRR(c.oprrr(p.As), 0, uint32(p.From.Index), uint32(p.From.Reg))
  3270  		} else {
  3271  			th := c.regoff(&p.To)
  3272  			o1 = AOP_RRR(c.oprrr(p.As), uint32(th), uint32(p.From.Index), uint32(p.From.Reg))
  3273  		}
  3274  
  3275  	case 44: /* indexed store */
  3276  		o1 = AOP_RRR(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg))
  3277  
  3278  	case 45: /* indexed load */
  3279  		switch p.As {
  3280  		/* The assembler accepts a 4-operand l*arx instruction. The fourth operand is an Exclusive Access Hint (EH) */
  3281  		/* The EH field can be used as a lock acquire/release hint as follows: */
  3282  		/* 0 = Atomic Update (fetch-and-operate or similar algorithm) */
  3283  		/* 1 = Exclusive Access (lock acquire and release) */
  3284  		case ALBAR, ALHAR, ALWAR, ALDAR:
  3285  			if p.From3Type() != obj.TYPE_NONE {
  3286  				eh := int(c.regoff(p.GetFrom3()))
  3287  				if eh > 1 {
  3288  					c.ctxt.Diag("illegal EH field\n%v", p)
  3289  				}
  3290  				o1 = AOP_RRRI(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg), uint32(eh))
  3291  			} else {
  3292  				o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg))
  3293  			}
  3294  		default:
  3295  			o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg))
  3296  		}
  3297  	case 46: /* plain op */
  3298  		o1 = c.oprrr(p.As)
  3299  
  3300  	case 47: /* op Ra, Rd; also op [Ra,] Rd */
  3301  		r := int(p.From.Reg)
  3302  
  3303  		if r == 0 {
  3304  			r = int(p.To.Reg)
  3305  		}
  3306  		o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0)
  3307  
  3308  	case 48: /* op Rs, Ra */
  3309  		r := int(p.From.Reg)
  3310  
  3311  		if r == 0 {
  3312  			r = int(p.To.Reg)
  3313  		}
  3314  		o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0)
  3315  
  3316  	case 49: /* op Rb; op $n, Rb */
  3317  		if p.From.Type != obj.TYPE_REG { /* tlbie $L, rB */
  3318  			v := c.regoff(&p.From) & 1
  3319  			o1 = AOP_RRR(c.oprrr(p.As), 0, 0, uint32(p.To.Reg)) | uint32(v)<<21
  3320  		} else {
  3321  			o1 = AOP_RRR(c.oprrr(p.As), 0, 0, uint32(p.From.Reg))
  3322  		}
  3323  
  3324  	case 50: /* rem[u] r1[,r2],r3 */
  3325  		r := int(p.Reg)
  3326  
  3327  		if r == 0 {
  3328  			r = int(p.To.Reg)
  3329  		}
  3330  		v := c.oprrr(p.As)
  3331  		t := v & (1<<10 | 1) /* OE|Rc */
  3332  		o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg))
  3333  		o2 = AOP_RRR(OP_MULLW, REGTMP, REGTMP, uint32(p.From.Reg))
  3334  		o3 = AOP_RRR(OP_SUBF|t, uint32(p.To.Reg), REGTMP, uint32(r))
  3335  		if p.As == AREMU {
  3336  			o4 = o3
  3337  
  3338  			/* Clear top 32 bits */
  3339  			o3 = OP_RLW(OP_RLDIC, REGTMP, REGTMP, 0, 0, 0) | 1<<5
  3340  		}
  3341  
  3342  	case 51: /* remd[u] r1[,r2],r3 */
  3343  		r := int(p.Reg)
  3344  
  3345  		if r == 0 {
  3346  			r = int(p.To.Reg)
  3347  		}
  3348  		v := c.oprrr(p.As)
  3349  		t := v & (1<<10 | 1) /* OE|Rc */
  3350  		o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg))
  3351  		o2 = AOP_RRR(OP_MULLD, REGTMP, REGTMP, uint32(p.From.Reg))
  3352  		o3 = AOP_RRR(OP_SUBF|t, uint32(p.To.Reg), REGTMP, uint32(r))
  3353  		/* cases 50,51: removed; can be reused. */
  3354  
  3355  		/* cases 50,51: removed; can be reused. */
  3356  
  3357  	case 52: /* mtfsbNx cr(n) */
  3358  		v := c.regoff(&p.From) & 31
  3359  
  3360  		o1 = AOP_RRR(c.oprrr(p.As), uint32(v), 0, 0)
  3361  
  3362  	case 53: /* mffsX ,fr1 */
  3363  		o1 = AOP_RRR(OP_MFFS, uint32(p.To.Reg), 0, 0)
  3364  
  3365  	case 55: /* op Rb, Rd */
  3366  		o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), 0, uint32(p.From.Reg))
  3367  
  3368  	case 56: /* sra $sh,[s,]a; srd $sh,[s,]a */
  3369  		v := c.regoff(&p.From)
  3370  
  3371  		r := int(p.Reg)
  3372  		if r == 0 {
  3373  			r = int(p.To.Reg)
  3374  		}
  3375  		o1 = AOP_RRR(c.opirr(p.As), uint32(r), uint32(p.To.Reg), uint32(v)&31)
  3376  		if (p.As == ASRAD || p.As == ASRADCC) && (v&0x20 != 0) {
  3377  			o1 |= 1 << 1 /* mb[5] */
  3378  		}
  3379  
  3380  	case 57: /* slw $sh,[s,]a -> rlwinm ... */
  3381  		v := c.regoff(&p.From)
  3382  
  3383  		r := int(p.Reg)
  3384  		if r == 0 {
  3385  			r = int(p.To.Reg)
  3386  		}
  3387  
  3388  		/*
  3389  			 * Let user (gs) shoot himself in the foot.
  3390  			 * qc has already complained.
  3391  			 *
  3392  			if(v < 0 || v > 31)
  3393  				ctxt->diag("illegal shift %ld\n%v", v, p);
  3394  		*/
  3395  		if v < 0 {
  3396  			v = 0
  3397  		} else if v > 32 {
  3398  			v = 32
  3399  		}
  3400  		var mask [2]uint8
  3401  		switch p.As {
  3402  		case AROTLW:
  3403  			mask[0], mask[1] = 0, 31
  3404  		case ASRW, ASRWCC:
  3405  			mask[0], mask[1] = uint8(v), 31
  3406  			v = 32 - v
  3407  		default:
  3408  			mask[0], mask[1] = 0, uint8(31-v)
  3409  		}
  3410  		o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(r), uint32(v), uint32(mask[0]), uint32(mask[1]))
  3411  		if p.As == ASLWCC || p.As == ASRWCC {
  3412  			o1 |= 1 // set the condition code
  3413  		}
  3414  
  3415  	case 58: /* logical $andcon,[s],a */
  3416  		v := c.regoff(&p.From)
  3417  
  3418  		r := int(p.Reg)
  3419  		if r == 0 {
  3420  			r = int(p.To.Reg)
  3421  		}
  3422  		o1 = LOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
  3423  
  3424  	case 60: /* tw to,a,b */
  3425  		r := int(c.regoff(&p.From) & 31)
  3426  
  3427  		o1 = AOP_RRR(c.oprrr(p.As), uint32(r), uint32(p.Reg), uint32(p.To.Reg))
  3428  
  3429  	case 61: /* tw to,a,$simm */
  3430  		r := int(c.regoff(&p.From) & 31)
  3431  
  3432  		v := c.regoff(&p.To)
  3433  		o1 = AOP_IRR(c.opirr(p.As), uint32(r), uint32(p.Reg), uint32(v))
  3434  
  3435  	case 62: /* clrlslwi $sh,s,$mask,a */
  3436  		v := c.regoff(&p.From)
  3437  		n := c.regoff(p.GetFrom3())
  3438  		// This is an extended mnemonic described in the ISA C.8.2
  3439  		// clrlslwi ra,rs,b,n -> rlwinm ra,rs,n,b-n,31-n
  3440  		// It maps onto rlwinm which is directly generated here.
  3441  		if n > v || v >= 32 {
  3442  			c.ctxt.Diag("Invalid n or b for CLRLSLWI: %x %x\n%v", v, n, p)
  3443  		}
  3444  
  3445  		o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.Reg), uint32(n), uint32(v-n), uint32(31-n))
  3446  
  3447  	case 63: /* rlwimi/rlwnm/rlwinm [$sh,b],s,[$mask or mb,me],a*/
  3448  		var mb, me uint32
  3449  		if len(p.RestArgs) == 1 { // Mask needs decomposed into mb and me.
  3450  			var valid bool
  3451  			// Note, optab rules ensure $mask is a 32b constant.
  3452  			mb, me, valid = decodeMask32(uint32(p.RestArgs[0].Addr.Offset))
  3453  			if !valid {
  3454  				c.ctxt.Diag("cannot generate mask #%x\n%v", uint64(p.RestArgs[0].Addr.Offset), p)
  3455  			}
  3456  		} else { // Otherwise, mask is already passed as mb and me in RestArgs.
  3457  			mb, me = uint32(p.RestArgs[0].Addr.Offset), uint32(p.RestArgs[1].Addr.Offset)
  3458  		}
  3459  		if p.From.Type == obj.TYPE_CONST {
  3460  			o1 = OP_RLW(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(p.From.Offset), mb, me)
  3461  		} else {
  3462  			o1 = OP_RLW(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(p.From.Reg), mb, me)
  3463  		}
  3464  
  3465  	case 64: /* mtfsf fr[, $m] {,fpcsr} */
  3466  		var v int32
  3467  		if p.From3Type() != obj.TYPE_NONE {
  3468  			v = c.regoff(p.GetFrom3()) & 255
  3469  		} else {
  3470  			v = 255
  3471  		}
  3472  		o1 = OP_MTFSF | uint32(v)<<17 | uint32(p.From.Reg)<<11
  3473  
  3474  	case 65: /* MOVFL $imm,FPSCR(n) => mtfsfi crfd,imm */
  3475  		if p.To.Reg == 0 {
  3476  			c.ctxt.Diag("must specify FPSCR(n)\n%v", p)
  3477  		}
  3478  		o1 = OP_MTFSFI | (uint32(p.To.Reg)&15)<<23 | (uint32(c.regoff(&p.From))&31)<<12
  3479  
  3480  	case 66: /* mov spr,r1; mov r1,spr */
  3481  		var r int
  3482  		var v int32
  3483  		if REG_R0 <= p.From.Reg && p.From.Reg <= REG_R31 {
  3484  			r = int(p.From.Reg)
  3485  			v = int32(p.To.Reg)
  3486  			o1 = OPVCC(31, 467, 0, 0) /* mtspr */
  3487  		} else {
  3488  			r = int(p.To.Reg)
  3489  			v = int32(p.From.Reg)
  3490  			o1 = OPVCC(31, 339, 0, 0) /* mfspr */
  3491  		}
  3492  
  3493  		o1 = AOP_RRR(o1, uint32(r), 0, 0) | (uint32(v)&0x1f)<<16 | ((uint32(v)>>5)&0x1f)<<11
  3494  
  3495  	case 67: /* mcrf crfD,crfS */
  3496  		if p.From.Reg == REG_CR || p.To.Reg == REG_CR {
  3497  			c.ctxt.Diag("CR argument must be a conditional register field (CR0-CR7)\n%v", p)
  3498  		}
  3499  		o1 = AOP_RRR(OP_MCRF, ((uint32(p.To.Reg) & 7) << 2), ((uint32(p.From.Reg) & 7) << 2), 0)
  3500  
  3501  	case 68: /* mfcr rD; mfocrf CRM,rD */
  3502  		o1 = AOP_RRR(OP_MFCR, uint32(p.To.Reg), 0, 0) /*  form, whole register */
  3503  		if p.From.Reg != REG_CR {
  3504  			v := uint32(1) << uint(7-(p.From.Reg&7)) /* CR(n) */
  3505  			o1 |= 1<<20 | v<<12                      /* new form, mfocrf */
  3506  		}
  3507  
  3508  	case 69: /* mtcrf CRM,rS, mtocrf CRx,rS */
  3509  		var v uint32
  3510  		if p.To.Reg == REG_CR {
  3511  			v = 0xff
  3512  		} else if p.To.Offset != 0 { // MOVFL gpr, constant
  3513  			v = uint32(p.To.Offset)
  3514  		} else { // p.To.Reg == REG_CRx
  3515  			v = 1 << uint(7-(p.To.Reg&7))
  3516  		}
  3517  		// Use mtocrf form if only one CR field moved.
  3518  		if bits.OnesCount32(v) == 1 {
  3519  			v |= 1 << 8
  3520  		}
  3521  
  3522  		o1 = AOP_RRR(OP_MTCRF, uint32(p.From.Reg), 0, 0) | uint32(v)<<12
  3523  
  3524  	case 70: /* cmp* r,r,cr or cmp*i r,i,cr or fcmp f,f,cr or cmpeqb r,r */
  3525  		r := uint32(p.Reg&7) << 2
  3526  		if p.To.Type == obj.TYPE_CONST {
  3527  			o1 = AOP_IRR(c.opirr(p.As), r, uint32(p.From.Reg), uint32(uint16(p.To.Offset)))
  3528  		} else {
  3529  			o1 = AOP_RRR(c.oprrr(p.As), r, uint32(p.From.Reg), uint32(p.To.Reg))
  3530  		}
  3531  
  3532  	case 72: /* slbmte (Rb+Rs -> slb[Rb]) -> Rs, Rb */
  3533  		o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), 0, uint32(p.To.Reg))
  3534  
  3535  	case 73: /* mcrfs crfD,crfS */
  3536  		if p.From.Type != obj.TYPE_REG || p.From.Reg != REG_FPSCR || p.To.Type != obj.TYPE_REG || p.To.Reg < REG_CR0 || REG_CR7 < p.To.Reg {
  3537  			c.ctxt.Diag("illegal FPSCR/CR field number\n%v", p)
  3538  		}
  3539  		o1 = AOP_RRR(OP_MCRFS, ((uint32(p.To.Reg) & 7) << 2), ((0 & 7) << 2), 0)
  3540  
  3541  	case 77: /* syscall $scon, syscall Rx */
  3542  		if p.From.Type == obj.TYPE_CONST {
  3543  			if p.From.Offset > BIG || p.From.Offset < -BIG {
  3544  				c.ctxt.Diag("illegal syscall, sysnum too large: %v", p)
  3545  			}
  3546  			o1 = AOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(p.From.Offset))
  3547  		} else if p.From.Type == obj.TYPE_REG {
  3548  			o1 = LOP_RRR(OP_OR, REGZERO, uint32(p.From.Reg), uint32(p.From.Reg))
  3549  		} else {
  3550  			c.ctxt.Diag("illegal syscall: %v", p)
  3551  			o1 = 0x7fe00008 // trap always
  3552  		}
  3553  
  3554  		o2 = c.oprrr(p.As)
  3555  		o3 = AOP_RRR(c.oprrr(AXOR), REGZERO, REGZERO, REGZERO) // XOR R0, R0
  3556  
  3557  	case 78: /* undef */
  3558  		o1 = 0 /* "An instruction consisting entirely of binary 0s is guaranteed
  3559  		   always to be an illegal instruction."  */
  3560  
  3561  	/* relocation operations */
  3562  	case 74:
  3563  		v := c.vregoff(&p.To)
  3564  		// Offsets in DS form stores must be a multiple of 4
  3565  		inst := c.opstore(p.As)
  3566  
  3567  		// Can't reuse base for store instructions.
  3568  		var rel obj.Reloc
  3569  		o1, o2, rel = c.symbolAccess(p.To.Sym, v, p.From.Reg, inst, false)
  3570  
  3571  		// Rewrite as a prefixed store if supported.
  3572  		if o.ispfx {
  3573  			o1, o2 = pfxstore(p.As, p.From.Reg, REG_R0, PFX_R_PCREL)
  3574  			rel.Type = objabi.R_ADDRPOWER_PCREL34
  3575  		} else if c.opform(inst) == DS_FORM && v&0x3 != 0 {
  3576  			log.Fatalf("invalid offset for DS form load/store %v", p)
  3577  		}
  3578  		c.cursym.AddRel(c.ctxt, rel)
  3579  
  3580  	case 75: // 32 bit offset symbol loads (got/toc/addr)
  3581  		v := p.From.Offset
  3582  
  3583  		// Offsets in DS form loads must be a multiple of 4
  3584  		inst := c.opload(p.As)
  3585  		var rel obj.Reloc
  3586  		switch p.From.Name {
  3587  		case obj.NAME_GOTREF, obj.NAME_TOCREF:
  3588  			if v != 0 {
  3589  				c.ctxt.Diag("invalid offset for GOT/TOC access %v", p)
  3590  			}
  3591  			o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0)
  3592  			o2 = AOP_IRR(inst, uint32(p.To.Reg), uint32(p.To.Reg), 0)
  3593  			rel.Off = int32(c.pc)
  3594  			rel.Siz = 8
  3595  			rel.Sym = p.From.Sym
  3596  			switch p.From.Name {
  3597  			case obj.NAME_GOTREF:
  3598  				rel.Type = objabi.R_ADDRPOWER_GOT
  3599  			case obj.NAME_TOCREF:
  3600  				rel.Type = objabi.R_ADDRPOWER_TOCREL_DS
  3601  			}
  3602  		default:
  3603  			reuseBaseReg := o.a6 == C_REG
  3604  			// Reuse To.Reg as base register if it is a GPR.
  3605  			o1, o2, rel = c.symbolAccess(p.From.Sym, v, p.To.Reg, inst, reuseBaseReg)
  3606  		}
  3607  
  3608  		// Convert to prefixed forms if supported.
  3609  		if o.ispfx {
  3610  			switch rel.Type {
  3611  			case objabi.R_ADDRPOWER, objabi.R_ADDRPOWER_DS,
  3612  				objabi.R_ADDRPOWER_TOCREL, objabi.R_ADDRPOWER_TOCREL_DS:
  3613  				o1, o2 = pfxload(p.As, p.To.Reg, REG_R0, PFX_R_PCREL)
  3614  				rel.Type = objabi.R_ADDRPOWER_PCREL34
  3615  			case objabi.R_POWER_TLS_IE:
  3616  				o1, o2 = pfxload(p.As, p.To.Reg, REG_R0, PFX_R_PCREL)
  3617  				rel.Type = objabi.R_POWER_TLS_IE_PCREL34
  3618  			case objabi.R_ADDRPOWER_GOT:
  3619  				o1, o2 = pfxload(p.As, p.To.Reg, REG_R0, PFX_R_PCREL)
  3620  				rel.Type = objabi.R_ADDRPOWER_GOT_PCREL34
  3621  			default:
  3622  				// We've failed to convert a TOC-relative relocation to a PC-relative one.
  3623  				log.Fatalf("Unable convert TOC-relative relocation %v to PC-relative", rel.Type)
  3624  			}
  3625  		} else if c.opform(inst) == DS_FORM && v&0x3 != 0 {
  3626  			log.Fatalf("invalid offset for DS form load/store %v", p)
  3627  		}
  3628  		c.cursym.AddRel(c.ctxt, rel)
  3629  
  3630  		o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0)
  3631  
  3632  	case 79:
  3633  		if p.From.Offset != 0 {
  3634  			c.ctxt.Diag("invalid offset against tls var %v", p)
  3635  		}
  3636  		var typ objabi.RelocType
  3637  		if !o.ispfx {
  3638  			o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R13, 0)
  3639  			o2 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), uint32(p.To.Reg), 0)
  3640  			typ = objabi.R_POWER_TLS_LE
  3641  		} else {
  3642  			o1, o2 = pfxadd(p.To.Reg, REG_R13, PFX_R_ABS, 0)
  3643  			typ = objabi.R_POWER_TLS_LE_TPREL34
  3644  		}
  3645  		c.cursym.AddRel(c.ctxt, obj.Reloc{
  3646  			Type: typ,
  3647  			Off:  int32(c.pc),
  3648  			Siz:  8,
  3649  			Sym:  p.From.Sym,
  3650  		})
  3651  
  3652  	case 80:
  3653  		if p.From.Offset != 0 {
  3654  			c.ctxt.Diag("invalid offset against tls var %v", p)
  3655  		}
  3656  		typ := objabi.R_POWER_TLS_IE
  3657  		if !o.ispfx {
  3658  			o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0)
  3659  			o2 = AOP_IRR(c.opload(AMOVD), uint32(p.To.Reg), uint32(p.To.Reg), 0)
  3660  		} else {
  3661  			o1, o2 = pfxload(p.As, p.To.Reg, REG_R0, PFX_R_PCREL)
  3662  			typ = objabi.R_POWER_TLS_IE_PCREL34
  3663  		}
  3664  		c.cursym.AddRel(c.ctxt, obj.Reloc{
  3665  			Type: typ,
  3666  			Off:  int32(c.pc),
  3667  			Siz:  8,
  3668  			Sym:  p.From.Sym,
  3669  		})
  3670  		o3 = AOP_RRR(OP_ADD, uint32(p.To.Reg), uint32(p.To.Reg), REG_R13)
  3671  		c.cursym.AddRel(c.ctxt, obj.Reloc{
  3672  			Type: objabi.R_POWER_TLS,
  3673  			Off:  int32(c.pc) + 8,
  3674  			Siz:  4,
  3675  			Sym:  p.From.Sym,
  3676  		})
  3677  
  3678  	case 82: /* vector instructions, VX-form and VC-form */
  3679  		if p.From.Type == obj.TYPE_REG {
  3680  			/* reg reg none OR reg reg reg */
  3681  			/* 3-register operand order: VRA, VRB, VRT */
  3682  			/* 2-register operand order: VRA, VRT */
  3683  			o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg))
  3684  		} else if p.From3Type() == obj.TYPE_CONST {
  3685  			/* imm imm reg reg */
  3686  			/* operand order: SIX, VRA, ST, VRT */
  3687  			six := int(c.regoff(&p.From))
  3688  			st := int(c.regoff(p.GetFrom3()))
  3689  			o1 = AOP_IIRR(c.opiirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(st), uint32(six))
  3690  		} else if p.From3Type() == obj.TYPE_NONE && p.Reg != 0 {
  3691  			/* imm reg reg */
  3692  			/* operand order: UIM, VRB, VRT */
  3693  			uim := int(c.regoff(&p.From))
  3694  			o1 = AOP_VIRR(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(uim))
  3695  		} else {
  3696  			/* imm reg */
  3697  			/* operand order: SIM, VRT */
  3698  			sim := int(c.regoff(&p.From))
  3699  			o1 = AOP_IR(c.opirr(p.As), uint32(p.To.Reg), uint32(sim))
  3700  		}
  3701  
  3702  	case 83: /* vector instructions, VA-form */
  3703  		if p.From.Type == obj.TYPE_REG {
  3704  			/* reg reg reg reg */
  3705  			/* 4-register operand order: VRA, VRB, VRC, VRT */
  3706  			o1 = AOP_RRRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg))
  3707  		} else if p.From.Type == obj.TYPE_CONST {
  3708  			/* imm reg reg reg */
  3709  			/* operand order: SHB, VRA, VRB, VRT */
  3710  			shb := int(c.regoff(&p.From))
  3711  			o1 = AOP_IRRR(c.opirrr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), uint32(shb))
  3712  		}
  3713  
  3714  	case 84: // ISEL BC,RA,RB,RT -> isel rt,ra,rb,bc
  3715  		bc := c.vregoff(&p.From)
  3716  		if o.a1 == C_CRBIT {
  3717  			// CR bit is encoded as a register, not a constant.
  3718  			bc = int64(p.From.Reg)
  3719  		}
  3720  
  3721  		// rt = To.Reg, ra = p.Reg, rb = p.From3.Reg
  3722  		o1 = AOP_ISEL(OP_ISEL, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), uint32(bc))
  3723  
  3724  	case 85: /* vector instructions, VX-form */
  3725  		/* reg none reg */
  3726  		/* 2-register operand order: VRB, VRT */
  3727  		o1 = AOP_RR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg))
  3728  
  3729  	case 86: /* VSX indexed store, XX1-form */
  3730  		/* reg reg reg */
  3731  		/* 3-register operand order: XT, (RB)(RA*1) */
  3732  		o1 = AOP_XX1(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg))
  3733  
  3734  	case 87: /* VSX indexed load, XX1-form */
  3735  		/* reg reg reg */
  3736  		/* 3-register operand order: (RB)(RA*1), XT */
  3737  		o1 = AOP_XX1(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg))
  3738  
  3739  	case 88: /* VSX mfvsr* instructions, XX1-form XS,RA */
  3740  		o1 = AOP_XX1(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg))
  3741  
  3742  	case 89: /* VSX instructions, XX2-form */
  3743  		/* reg none reg OR reg imm reg */
  3744  		/* 2-register operand order: XB, XT or XB, UIM, XT*/
  3745  		uim := int(c.regoff(p.GetFrom3()))
  3746  		o1 = AOP_XX2(c.oprrr(p.As), uint32(p.To.Reg), uint32(uim), uint32(p.From.Reg))
  3747  
  3748  	case 90: /* VSX instructions, XX3-form */
  3749  		if p.From3Type() == obj.TYPE_NONE {
  3750  			/* reg reg reg */
  3751  			/* 3-register operand order: XA, XB, XT */
  3752  			o1 = AOP_XX3(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg))
  3753  		} else if p.From3Type() == obj.TYPE_CONST {
  3754  			/* reg reg reg imm */
  3755  			/* operand order: XA, XB, DM, XT */
  3756  			dm := int(c.regoff(p.GetFrom3()))
  3757  			o1 = AOP_XX3I(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(dm))
  3758  		}
  3759  
  3760  	case 91: /* VSX instructions, XX4-form */
  3761  		/* reg reg reg reg */
  3762  		/* 3-register operand order: XA, XB, XC, XT */
  3763  		o1 = AOP_XX4(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg))
  3764  
  3765  	case 92: /* X-form instructions, 3-operands */
  3766  		if p.To.Type == obj.TYPE_CONST {
  3767  			/* imm reg reg */
  3768  			xf := int32(p.From.Reg)
  3769  			if REG_F0 <= xf && xf <= REG_F31 {
  3770  				/* operand order: FRA, FRB, BF */
  3771  				bf := int(c.regoff(&p.To)) << 2
  3772  				o1 = AOP_RRR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg), uint32(p.Reg))
  3773  			} else {
  3774  				/* operand order: RA, RB, L */
  3775  				l := int(c.regoff(&p.To))
  3776  				o1 = AOP_RRR(c.opirr(p.As), uint32(l), uint32(p.From.Reg), uint32(p.Reg))
  3777  			}
  3778  		} else if p.From3Type() == obj.TYPE_CONST {
  3779  			/* reg reg imm */
  3780  			/* operand order: RB, L, RA */
  3781  			l := int(c.regoff(p.GetFrom3()))
  3782  			o1 = AOP_RRR(c.opirr(p.As), uint32(l), uint32(p.To.Reg), uint32(p.From.Reg))
  3783  		} else if p.To.Type == obj.TYPE_REG {
  3784  			cr := int32(p.To.Reg)
  3785  			if REG_CR0 <= cr && cr <= REG_CR7 {
  3786  				/* cr reg reg */
  3787  				/* operand order: RA, RB, BF */
  3788  				bf := (int(p.To.Reg) & 7) << 2
  3789  				o1 = AOP_RRR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg), uint32(p.Reg))
  3790  			} else if p.From.Type == obj.TYPE_CONST {
  3791  				/* reg imm */
  3792  				/* operand order: L, RT */
  3793  				l := int(c.regoff(&p.From))
  3794  				o1 = AOP_RRR(c.opirr(p.As), uint32(p.To.Reg), uint32(l), uint32(p.Reg))
  3795  			} else {
  3796  				switch p.As {
  3797  				case ACOPY, APASTECC:
  3798  					o1 = AOP_RRR(c.opirr(p.As), uint32(1), uint32(p.From.Reg), uint32(p.To.Reg))
  3799  				default:
  3800  					/* reg reg reg */
  3801  					/* operand order: RS, RB, RA */
  3802  					o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg))
  3803  				}
  3804  			}
  3805  		}
  3806  
  3807  	case 93: /* X-form instructions, 2-operands */
  3808  		if p.To.Type == obj.TYPE_CONST {
  3809  			/* imm reg */
  3810  			/* operand order: FRB, BF */
  3811  			bf := int(c.regoff(&p.To)) << 2
  3812  			o1 = AOP_RR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg))
  3813  		} else if p.Reg == 0 {
  3814  			/* popcnt* r,r, X-form */
  3815  			/* operand order: RS, RA */
  3816  			o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg))
  3817  		}
  3818  
  3819  	case 94: /* Z23-form instructions, 4-operands */
  3820  		/* reg reg reg imm */
  3821  		/* operand order: RA, RB, CY, RT */
  3822  		cy := int(c.regoff(p.GetFrom3()))
  3823  		o1 = AOP_Z23I(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(cy))
  3824  
  3825  	case 96: /* VSX load, DQ-form */
  3826  		/* reg imm reg */
  3827  		/* operand order: (RA)(DQ), XT */
  3828  		dq := int16(c.regoff(&p.From))
  3829  		if (dq & 15) != 0 {
  3830  			c.ctxt.Diag("invalid offset for DQ form load/store %v", dq)
  3831  		}
  3832  		o1 = AOP_DQ(c.opload(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(dq))
  3833  
  3834  	case 97: /* VSX store, DQ-form */
  3835  		/* reg imm reg */
  3836  		/* operand order: XT, (RA)(DQ) */
  3837  		dq := int16(c.regoff(&p.To))
  3838  		if (dq & 15) != 0 {
  3839  			c.ctxt.Diag("invalid offset for DQ form load/store %v", dq)
  3840  		}
  3841  		o1 = AOP_DQ(c.opstore(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(dq))
  3842  	case 98: /* VSX indexed load or load with length (also left-justified), x-form */
  3843  		/* vsreg, reg, reg */
  3844  		o1 = AOP_XX1(c.opload(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg))
  3845  	case 99: /* VSX store with length (also left-justified) x-form */
  3846  		/* reg, reg, vsreg */
  3847  		o1 = AOP_XX1(c.opstore(p.As), uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg))
  3848  	case 100: /* VSX X-form XXSPLTIB */
  3849  		if p.From.Type == obj.TYPE_CONST {
  3850  			/* imm reg */
  3851  			uim := int(c.regoff(&p.From))
  3852  			/* imm reg */
  3853  			/* Use AOP_XX1 form with 0 for one of the registers. */
  3854  			o1 = AOP_XX1(c.oprrr(p.As), uint32(p.To.Reg), uint32(0), uint32(uim))
  3855  		} else {
  3856  			c.ctxt.Diag("invalid ops for %v", p.As)
  3857  		}
  3858  	case 101:
  3859  		o1 = AOP_XX2(c.oprrr(p.As), uint32(p.To.Reg), uint32(0), uint32(p.From.Reg))
  3860  
  3861  	case 104: /* VSX mtvsr* instructions, XX1-form RA,RB,XT */
  3862  		o1 = AOP_XX1(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg))
  3863  
  3864  	case 106: /* MOVD spr, soreg */
  3865  		v := int32(p.From.Reg)
  3866  		o1 = OPVCC(31, 339, 0, 0) /* mfspr */
  3867  		o1 = AOP_RRR(o1, uint32(REGTMP), 0, 0) | (uint32(v)&0x1f)<<16 | ((uint32(v)>>5)&0x1f)<<11
  3868  		so := c.regoff(&p.To)
  3869  		o2 = AOP_IRR(c.opstore(AMOVD), uint32(REGTMP), uint32(p.To.Reg), uint32(so))
  3870  		if so&0x3 != 0 {
  3871  			log.Fatalf("invalid offset for DS form load/store %v", p)
  3872  		}
  3873  		if p.To.Reg == REGTMP {
  3874  			log.Fatalf("SPR move to memory will clobber R31 %v", p)
  3875  		}
  3876  
  3877  	case 107: /* MOVD soreg, spr */
  3878  		v := int32(p.From.Reg)
  3879  		so := c.regoff(&p.From)
  3880  		o1 = AOP_IRR(c.opload(AMOVD), uint32(REGTMP), uint32(v), uint32(so))
  3881  		o2 = OPVCC(31, 467, 0, 0) /* mtspr */
  3882  		v = int32(p.To.Reg)
  3883  		o2 = AOP_RRR(o2, uint32(REGTMP), 0, 0) | (uint32(v)&0x1f)<<16 | ((uint32(v)>>5)&0x1f)<<11
  3884  		if so&0x3 != 0 {
  3885  			log.Fatalf("invalid offset for DS form load/store %v", p)
  3886  		}
  3887  
  3888  	case 108: /* mov r, xoreg ==> stwx rx,ry */
  3889  		r := int(p.To.Reg)
  3890  		o1 = AOP_RRR(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(r))
  3891  
  3892  	case 109: /* mov xoreg, r ==> lbzx/lhzx/lwzx rx,ry, lbzx rx,ry + extsb r,r */
  3893  		r := int(p.From.Reg)
  3894  
  3895  		o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(r))
  3896  		// Sign extend MOVB operations. This is ignored for other cases (o.size == 4).
  3897  		o2 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0)
  3898  
  3899  	case 110: /* SETB creg, rt */
  3900  		bfa := uint32(p.From.Reg) << 2
  3901  		rt := uint32(p.To.Reg)
  3902  		o1 = LOP_RRR(OP_SETB, bfa, rt, 0)
  3903  	}
  3904  
  3905  	out[0] = o1
  3906  	out[1] = o2
  3907  	out[2] = o3
  3908  	out[3] = o4
  3909  	out[4] = o5
  3910  }
  3911  
  3912  func (c *ctxt9) vregoff(a *obj.Addr) int64 {
  3913  	c.instoffset = 0
  3914  	if a != nil {
  3915  		c.aclass(a)
  3916  	}
  3917  	return c.instoffset
  3918  }
  3919  
  3920  func (c *ctxt9) regoff(a *obj.Addr) int32 {
  3921  	return int32(c.vregoff(a))
  3922  }
  3923  
  3924  func (c *ctxt9) oprrr(a obj.As) uint32 {
  3925  	switch a {
  3926  	case AADD:
  3927  		return OPVCC(31, 266, 0, 0)
  3928  	case AADDCC:
  3929  		return OPVCC(31, 266, 0, 1)
  3930  	case AADDV:
  3931  		return OPVCC(31, 266, 1, 0)
  3932  	case AADDVCC:
  3933  		return OPVCC(31, 266, 1, 1)
  3934  	case AADDC:
  3935  		return OPVCC(31, 10, 0, 0)
  3936  	case AADDCCC:
  3937  		return OPVCC(31, 10, 0, 1)
  3938  	case AADDCV:
  3939  		return OPVCC(31, 10, 1, 0)
  3940  	case AADDCVCC:
  3941  		return OPVCC(31, 10, 1, 1)
  3942  	case AADDE:
  3943  		return OPVCC(31, 138, 0, 0)
  3944  	case AADDECC:
  3945  		return OPVCC(31, 138, 0, 1)
  3946  	case AADDEV:
  3947  		return OPVCC(31, 138, 1, 0)
  3948  	case AADDEVCC:
  3949  		return OPVCC(31, 138, 1, 1)
  3950  	case AADDME:
  3951  		return OPVCC(31, 234, 0, 0)
  3952  	case AADDMECC:
  3953  		return OPVCC(31, 234, 0, 1)
  3954  	case AADDMEV:
  3955  		return OPVCC(31, 234, 1, 0)
  3956  	case AADDMEVCC:
  3957  		return OPVCC(31, 234, 1, 1)
  3958  	case AADDZE:
  3959  		return OPVCC(31, 202, 0, 0)
  3960  	case AADDZECC:
  3961  		return OPVCC(31, 202, 0, 1)
  3962  	case AADDZEV:
  3963  		return OPVCC(31, 202, 1, 0)
  3964  	case AADDZEVCC:
  3965  		return OPVCC(31, 202, 1, 1)
  3966  	case AADDEX:
  3967  		return OPVCC(31, 170, 0, 0) /* addex - v3.0b */
  3968  
  3969  	case AAND:
  3970  		return OPVCC(31, 28, 0, 0)
  3971  	case AANDCC:
  3972  		return OPVCC(31, 28, 0, 1)
  3973  	case AANDN:
  3974  		return OPVCC(31, 60, 0, 0)
  3975  	case AANDNCC:
  3976  		return OPVCC(31, 60, 0, 1)
  3977  
  3978  	case ACMP:
  3979  		return OPVCC(31, 0, 0, 0) | 1<<21 /* L=1 */
  3980  	case ACMPU:
  3981  		return OPVCC(31, 32, 0, 0) | 1<<21
  3982  	case ACMPW:
  3983  		return OPVCC(31, 0, 0, 0) /* L=0 */
  3984  	case ACMPWU:
  3985  		return OPVCC(31, 32, 0, 0)
  3986  	case ACMPB:
  3987  		return OPVCC(31, 508, 0, 0) /* cmpb - v2.05 */
  3988  	case ACMPEQB:
  3989  		return OPVCC(31, 224, 0, 0) /* cmpeqb - v3.00 */
  3990  
  3991  	case ACNTLZW:
  3992  		return OPVCC(31, 26, 0, 0)
  3993  	case ACNTLZWCC:
  3994  		return OPVCC(31, 26, 0, 1)
  3995  	case ACNTLZD:
  3996  		return OPVCC(31, 58, 0, 0)
  3997  	case ACNTLZDCC:
  3998  		return OPVCC(31, 58, 0, 1)
  3999  
  4000  	case ACRAND:
  4001  		return OPVCC(19, 257, 0, 0)
  4002  	case ACRANDN:
  4003  		return OPVCC(19, 129, 0, 0)
  4004  	case ACREQV:
  4005  		return OPVCC(19, 289, 0, 0)
  4006  	case ACRNAND:
  4007  		return OPVCC(19, 225, 0, 0)
  4008  	case ACRNOR:
  4009  		return OPVCC(19, 33, 0, 0)
  4010  	case ACROR:
  4011  		return OPVCC(19, 449, 0, 0)
  4012  	case ACRORN:
  4013  		return OPVCC(19, 417, 0, 0)
  4014  	case ACRXOR:
  4015  		return OPVCC(19, 193, 0, 0)
  4016  
  4017  	case ADADD:
  4018  		return OPVCC(59, 2, 0, 0)
  4019  	case ADDIV:
  4020  		return OPVCC(59, 546, 0, 0)
  4021  	case ADMUL:
  4022  		return OPVCC(59, 34, 0, 0)
  4023  	case ADSUB:
  4024  		return OPVCC(59, 514, 0, 0)
  4025  	case ADADDQ:
  4026  		return OPVCC(63, 2, 0, 0)
  4027  	case ADDIVQ:
  4028  		return OPVCC(63, 546, 0, 0)
  4029  	case ADMULQ:
  4030  		return OPVCC(63, 34, 0, 0)
  4031  	case ADSUBQ:
  4032  		return OPVCC(63, 514, 0, 0)
  4033  	case ADCMPU:
  4034  		return OPVCC(59, 642, 0, 0)
  4035  	case ADCMPUQ:
  4036  		return OPVCC(63, 642, 0, 0)
  4037  	case ADCMPO:
  4038  		return OPVCC(59, 130, 0, 0)
  4039  	case ADCMPOQ:
  4040  		return OPVCC(63, 130, 0, 0)
  4041  
  4042  	case ADCBF:
  4043  		return OPVCC(31, 86, 0, 0)
  4044  	case ADCBI:
  4045  		return OPVCC(31, 470, 0, 0)
  4046  	case ADCBST:
  4047  		return OPVCC(31, 54, 0, 0)
  4048  	case ADCBT:
  4049  		return OPVCC(31, 278, 0, 0)
  4050  	case ADCBTST:
  4051  		return OPVCC(31, 246, 0, 0)
  4052  	case ADCBZ:
  4053  		return OPVCC(31, 1014, 0, 0)
  4054  
  4055  	case AMODUD:
  4056  		return OPVCC(31, 265, 0, 0) /* modud - v3.0 */
  4057  	case AMODUW:
  4058  		return OPVCC(31, 267, 0, 0) /* moduw - v3.0 */
  4059  	case AMODSD:
  4060  		return OPVCC(31, 777, 0, 0) /* modsd - v3.0 */
  4061  	case AMODSW:
  4062  		return OPVCC(31, 779, 0, 0) /* modsw - v3.0 */
  4063  
  4064  	case ADIVW, AREM:
  4065  		return OPVCC(31, 491, 0, 0)
  4066  
  4067  	case ADIVWCC:
  4068  		return OPVCC(31, 491, 0, 1)
  4069  
  4070  	case ADIVWV:
  4071  		return OPVCC(31, 491, 1, 0)
  4072  
  4073  	case ADIVWVCC:
  4074  		return OPVCC(31, 491, 1, 1)
  4075  
  4076  	case ADIVWU, AREMU:
  4077  		return OPVCC(31, 459, 0, 0)
  4078  
  4079  	case ADIVWUCC:
  4080  		return OPVCC(31, 459, 0, 1)
  4081  
  4082  	case ADIVWUV:
  4083  		return OPVCC(31, 459, 1, 0)
  4084  
  4085  	case ADIVWUVCC:
  4086  		return OPVCC(31, 459, 1, 1)
  4087  
  4088  	case ADIVD, AREMD:
  4089  		return OPVCC(31, 489, 0, 0)
  4090  
  4091  	case ADIVDCC:
  4092  		return OPVCC(31, 489, 0, 1)
  4093  
  4094  	case ADIVDE:
  4095  		return OPVCC(31, 425, 0, 0)
  4096  
  4097  	case ADIVDECC:
  4098  		return OPVCC(31, 425, 0, 1)
  4099  
  4100  	case ADIVDEU:
  4101  		return OPVCC(31, 393, 0, 0)
  4102  
  4103  	case ADIVDEUCC:
  4104  		return OPVCC(31, 393, 0, 1)
  4105  
  4106  	case ADIVDV:
  4107  		return OPVCC(31, 489, 1, 0)
  4108  
  4109  	case ADIVDVCC:
  4110  		return OPVCC(31, 489, 1, 1)
  4111  
  4112  	case ADIVDU, AREMDU:
  4113  		return OPVCC(31, 457, 0, 0)
  4114  
  4115  	case ADIVDUCC:
  4116  		return OPVCC(31, 457, 0, 1)
  4117  
  4118  	case ADIVDUV:
  4119  		return OPVCC(31, 457, 1, 0)
  4120  
  4121  	case ADIVDUVCC:
  4122  		return OPVCC(31, 457, 1, 1)
  4123  
  4124  	case AEIEIO:
  4125  		return OPVCC(31, 854, 0, 0)
  4126  
  4127  	case AEQV:
  4128  		return OPVCC(31, 284, 0, 0)
  4129  	case AEQVCC:
  4130  		return OPVCC(31, 284, 0, 1)
  4131  
  4132  	case AEXTSB:
  4133  		return OPVCC(31, 954, 0, 0)
  4134  	case AEXTSBCC:
  4135  		return OPVCC(31, 954, 0, 1)
  4136  	case AEXTSH:
  4137  		return OPVCC(31, 922, 0, 0)
  4138  	case AEXTSHCC:
  4139  		return OPVCC(31, 922, 0, 1)
  4140  	case AEXTSW:
  4141  		return OPVCC(31, 986, 0, 0)
  4142  	case AEXTSWCC:
  4143  		return OPVCC(31, 986, 0, 1)
  4144  
  4145  	case AFABS:
  4146  		return OPVCC(63, 264, 0, 0)
  4147  	case AFABSCC:
  4148  		return OPVCC(63, 264, 0, 1)
  4149  	case AFADD:
  4150  		return OPVCC(63, 21, 0, 0)
  4151  	case AFADDCC:
  4152  		return OPVCC(63, 21, 0, 1)
  4153  	case AFADDS:
  4154  		return OPVCC(59, 21, 0, 0)
  4155  	case AFADDSCC:
  4156  		return OPVCC(59, 21, 0, 1)
  4157  	case AFCMPO:
  4158  		return OPVCC(63, 32, 0, 0)
  4159  	case AFCMPU:
  4160  		return OPVCC(63, 0, 0, 0)
  4161  	case AFCFID:
  4162  		return OPVCC(63, 846, 0, 0)
  4163  	case AFCFIDCC:
  4164  		return OPVCC(63, 846, 0, 1)
  4165  	case AFCFIDU:
  4166  		return OPVCC(63, 974, 0, 0)
  4167  	case AFCFIDUCC:
  4168  		return OPVCC(63, 974, 0, 1)
  4169  	case AFCFIDS:
  4170  		return OPVCC(59, 846, 0, 0)
  4171  	case AFCFIDSCC:
  4172  		return OPVCC(59, 846, 0, 1)
  4173  	case AFCTIW:
  4174  		return OPVCC(63, 14, 0, 0)
  4175  	case AFCTIWCC:
  4176  		return OPVCC(63, 14, 0, 1)
  4177  	case AFCTIWZ:
  4178  		return OPVCC(63, 15, 0, 0)
  4179  	case AFCTIWZCC:
  4180  		return OPVCC(63, 15, 0, 1)
  4181  	case AFCTID:
  4182  		return OPVCC(63, 814, 0, 0)
  4183  	case AFCTIDCC:
  4184  		return OPVCC(63, 814, 0, 1)
  4185  	case AFCTIDZ:
  4186  		return OPVCC(63, 815, 0, 0)
  4187  	case AFCTIDZCC:
  4188  		return OPVCC(63, 815, 0, 1)
  4189  	case AFDIV:
  4190  		return OPVCC(63, 18, 0, 0)
  4191  	case AFDIVCC:
  4192  		return OPVCC(63, 18, 0, 1)
  4193  	case AFDIVS:
  4194  		return OPVCC(59, 18, 0, 0)
  4195  	case AFDIVSCC:
  4196  		return OPVCC(59, 18, 0, 1)
  4197  	case AFMADD:
  4198  		return OPVCC(63, 29, 0, 0)
  4199  	case AFMADDCC:
  4200  		return OPVCC(63, 29, 0, 1)
  4201  	case AFMADDS:
  4202  		return OPVCC(59, 29, 0, 0)
  4203  	case AFMADDSCC:
  4204  		return OPVCC(59, 29, 0, 1)
  4205  
  4206  	case AFMOVS, AFMOVD:
  4207  		return OPVCC(63, 72, 0, 0) /* load */
  4208  	case AFMOVDCC:
  4209  		return OPVCC(63, 72, 0, 1)
  4210  	case AFMSUB:
  4211  		return OPVCC(63, 28, 0, 0)
  4212  	case AFMSUBCC:
  4213  		return OPVCC(63, 28, 0, 1)
  4214  	case AFMSUBS:
  4215  		return OPVCC(59, 28, 0, 0)
  4216  	case AFMSUBSCC:
  4217  		return OPVCC(59, 28, 0, 1)
  4218  	case AFMUL:
  4219  		return OPVCC(63, 25, 0, 0)
  4220  	case AFMULCC:
  4221  		return OPVCC(63, 25, 0, 1)
  4222  	case AFMULS:
  4223  		return OPVCC(59, 25, 0, 0)
  4224  	case AFMULSCC:
  4225  		return OPVCC(59, 25, 0, 1)
  4226  	case AFNABS:
  4227  		return OPVCC(63, 136, 0, 0)
  4228  	case AFNABSCC:
  4229  		return OPVCC(63, 136, 0, 1)
  4230  	case AFNEG:
  4231  		return OPVCC(63, 40, 0, 0)
  4232  	case AFNEGCC:
  4233  		return OPVCC(63, 40, 0, 1)
  4234  	case AFNMADD:
  4235  		return OPVCC(63, 31, 0, 0)
  4236  	case AFNMADDCC:
  4237  		return OPVCC(63, 31, 0, 1)
  4238  	case AFNMADDS:
  4239  		return OPVCC(59, 31, 0, 0)
  4240  	case AFNMADDSCC:
  4241  		return OPVCC(59, 31, 0, 1)
  4242  	case AFNMSUB:
  4243  		return OPVCC(63, 30, 0, 0)
  4244  	case AFNMSUBCC:
  4245  		return OPVCC(63, 30, 0, 1)
  4246  	case AFNMSUBS:
  4247  		return OPVCC(59, 30, 0, 0)
  4248  	case AFNMSUBSCC:
  4249  		return OPVCC(59, 30, 0, 1)
  4250  	case AFCPSGN:
  4251  		return OPVCC(63, 8, 0, 0)
  4252  	case AFCPSGNCC:
  4253  		return OPVCC(63, 8, 0, 1)
  4254  	case AFRES:
  4255  		return OPVCC(59, 24, 0, 0)
  4256  	case AFRESCC:
  4257  		return OPVCC(59, 24, 0, 1)
  4258  	case AFRIM:
  4259  		return OPVCC(63, 488, 0, 0)
  4260  	case AFRIMCC:
  4261  		return OPVCC(63, 488, 0, 1)
  4262  	case AFRIP:
  4263  		return OPVCC(63, 456, 0, 0)
  4264  	case AFRIPCC:
  4265  		return OPVCC(63, 456, 0, 1)
  4266  	case AFRIZ:
  4267  		return OPVCC(63, 424, 0, 0)
  4268  	case AFRIZCC:
  4269  		return OPVCC(63, 424, 0, 1)
  4270  	case AFRIN:
  4271  		return OPVCC(63, 392, 0, 0)
  4272  	case AFRINCC:
  4273  		return OPVCC(63, 392, 0, 1)
  4274  	case AFRSP:
  4275  		return OPVCC(63, 12, 0, 0)
  4276  	case AFRSPCC:
  4277  		return OPVCC(63, 12, 0, 1)
  4278  	case AFRSQRTE:
  4279  		return OPVCC(63, 26, 0, 0)
  4280  	case AFRSQRTECC:
  4281  		return OPVCC(63, 26, 0, 1)
  4282  	case AFSEL:
  4283  		return OPVCC(63, 23, 0, 0)
  4284  	case AFSELCC:
  4285  		return OPVCC(63, 23, 0, 1)
  4286  	case AFSQRT:
  4287  		return OPVCC(63, 22, 0, 0)
  4288  	case AFSQRTCC:
  4289  		return OPVCC(63, 22, 0, 1)
  4290  	case AFSQRTS:
  4291  		return OPVCC(59, 22, 0, 0)
  4292  	case AFSQRTSCC:
  4293  		return OPVCC(59, 22, 0, 1)
  4294  	case AFSUB:
  4295  		return OPVCC(63, 20, 0, 0)
  4296  	case AFSUBCC:
  4297  		return OPVCC(63, 20, 0, 1)
  4298  	case AFSUBS:
  4299  		return OPVCC(59, 20, 0, 0)
  4300  	case AFSUBSCC:
  4301  		return OPVCC(59, 20, 0, 1)
  4302  
  4303  	case AICBI:
  4304  		return OPVCC(31, 982, 0, 0)
  4305  	case AISYNC:
  4306  		return OPVCC(19, 150, 0, 0)
  4307  
  4308  	case AMTFSB0:
  4309  		return OPVCC(63, 70, 0, 0)
  4310  	case AMTFSB0CC:
  4311  		return OPVCC(63, 70, 0, 1)
  4312  	case AMTFSB1:
  4313  		return OPVCC(63, 38, 0, 0)
  4314  	case AMTFSB1CC:
  4315  		return OPVCC(63, 38, 0, 1)
  4316  
  4317  	case AMULHW:
  4318  		return OPVCC(31, 75, 0, 0)
  4319  	case AMULHWCC:
  4320  		return OPVCC(31, 75, 0, 1)
  4321  	case AMULHWU:
  4322  		return OPVCC(31, 11, 0, 0)
  4323  	case AMULHWUCC:
  4324  		return OPVCC(31, 11, 0, 1)
  4325  	case AMULLW:
  4326  		return OPVCC(31, 235, 0, 0)
  4327  	case AMULLWCC:
  4328  		return OPVCC(31, 235, 0, 1)
  4329  	case AMULLWV:
  4330  		return OPVCC(31, 235, 1, 0)
  4331  	case AMULLWVCC:
  4332  		return OPVCC(31, 235, 1, 1)
  4333  
  4334  	case AMULHD:
  4335  		return OPVCC(31, 73, 0, 0)
  4336  	case AMULHDCC:
  4337  		return OPVCC(31, 73, 0, 1)
  4338  	case AMULHDU:
  4339  		return OPVCC(31, 9, 0, 0)
  4340  	case AMULHDUCC:
  4341  		return OPVCC(31, 9, 0, 1)
  4342  	case AMULLD:
  4343  		return OPVCC(31, 233, 0, 0)
  4344  	case AMULLDCC:
  4345  		return OPVCC(31, 233, 0, 1)
  4346  	case AMULLDV:
  4347  		return OPVCC(31, 233, 1, 0)
  4348  	case AMULLDVCC:
  4349  		return OPVCC(31, 233, 1, 1)
  4350  
  4351  	case ANAND:
  4352  		return OPVCC(31, 476, 0, 0)
  4353  	case ANANDCC:
  4354  		return OPVCC(31, 476, 0, 1)
  4355  	case ANEG:
  4356  		return OPVCC(31, 104, 0, 0)
  4357  	case ANEGCC:
  4358  		return OPVCC(31, 104, 0, 1)
  4359  	case ANEGV:
  4360  		return OPVCC(31, 104, 1, 0)
  4361  	case ANEGVCC:
  4362  		return OPVCC(31, 104, 1, 1)
  4363  	case ANOR:
  4364  		return OPVCC(31, 124, 0, 0)
  4365  	case ANORCC:
  4366  		return OPVCC(31, 124, 0, 1)
  4367  	case AOR:
  4368  		return OPVCC(31, 444, 0, 0)
  4369  	case AORCC:
  4370  		return OPVCC(31, 444, 0, 1)
  4371  	case AORN:
  4372  		return OPVCC(31, 412, 0, 0)
  4373  	case AORNCC:
  4374  		return OPVCC(31, 412, 0, 1)
  4375  
  4376  	case APOPCNTD:
  4377  		return OPVCC(31, 506, 0, 0) /* popcntd - v2.06 */
  4378  	case APOPCNTW:
  4379  		return OPVCC(31, 378, 0, 0) /* popcntw - v2.06 */
  4380  	case APOPCNTB:
  4381  		return OPVCC(31, 122, 0, 0) /* popcntb - v2.02 */
  4382  	case ACNTTZW:
  4383  		return OPVCC(31, 538, 0, 0) /* cnttzw - v3.00 */
  4384  	case ACNTTZWCC:
  4385  		return OPVCC(31, 538, 0, 1) /* cnttzw. - v3.00 */
  4386  	case ACNTTZD:
  4387  		return OPVCC(31, 570, 0, 0) /* cnttzd - v3.00 */
  4388  	case ACNTTZDCC:
  4389  		return OPVCC(31, 570, 0, 1) /* cnttzd. - v3.00 */
  4390  
  4391  	case ARFI:
  4392  		return OPVCC(19, 50, 0, 0)
  4393  	case ARFCI:
  4394  		return OPVCC(19, 51, 0, 0)
  4395  	case ARFID:
  4396  		return OPVCC(19, 18, 0, 0)
  4397  	case AHRFID:
  4398  		return OPVCC(19, 274, 0, 0)
  4399  
  4400  	case ARLWNM:
  4401  		return OPVCC(23, 0, 0, 0)
  4402  	case ARLWNMCC:
  4403  		return OPVCC(23, 0, 0, 1)
  4404  
  4405  	case ARLDCL:
  4406  		return OPVCC(30, 8, 0, 0)
  4407  	case ARLDCLCC:
  4408  		return OPVCC(30, 0, 0, 1)
  4409  
  4410  	case ARLDCR:
  4411  		return OPVCC(30, 9, 0, 0)
  4412  	case ARLDCRCC:
  4413  		return OPVCC(30, 9, 0, 1)
  4414  
  4415  	case ARLDICL:
  4416  		return OPVCC(30, 0, 0, 0)
  4417  	case ARLDICLCC:
  4418  		return OPVCC(30, 0, 0, 1)
  4419  	case ARLDICR:
  4420  		return OPMD(30, 1, 0) // rldicr
  4421  	case ARLDICRCC:
  4422  		return OPMD(30, 1, 1) // rldicr.
  4423  
  4424  	case ARLDIC:
  4425  		return OPMD(30, 2, 0) // rldic
  4426  	case ARLDICCC:
  4427  		return OPMD(30, 2, 1) // rldic.
  4428  
  4429  	case ASYSCALL:
  4430  		return OPVCC(17, 1, 0, 0)
  4431  
  4432  	case ASLW:
  4433  		return OPVCC(31, 24, 0, 0)
  4434  	case ASLWCC:
  4435  		return OPVCC(31, 24, 0, 1)
  4436  	case ASLD:
  4437  		return OPVCC(31, 27, 0, 0)
  4438  	case ASLDCC:
  4439  		return OPVCC(31, 27, 0, 1)
  4440  
  4441  	case ASRAW:
  4442  		return OPVCC(31, 792, 0, 0)
  4443  	case ASRAWCC:
  4444  		return OPVCC(31, 792, 0, 1)
  4445  	case ASRAD:
  4446  		return OPVCC(31, 794, 0, 0)
  4447  	case ASRADCC:
  4448  		return OPVCC(31, 794, 0, 1)
  4449  
  4450  	case AEXTSWSLI:
  4451  		return OPVCC(31, 445, 0, 0)
  4452  	case AEXTSWSLICC:
  4453  		return OPVCC(31, 445, 0, 1)
  4454  
  4455  	case ASRW:
  4456  		return OPVCC(31, 536, 0, 0)
  4457  	case ASRWCC:
  4458  		return OPVCC(31, 536, 0, 1)
  4459  	case ASRD:
  4460  		return OPVCC(31, 539, 0, 0)
  4461  	case ASRDCC:
  4462  		return OPVCC(31, 539, 0, 1)
  4463  
  4464  	case ASUB:
  4465  		return OPVCC(31, 40, 0, 0)
  4466  	case ASUBCC:
  4467  		return OPVCC(31, 40, 0, 1)
  4468  	case ASUBV:
  4469  		return OPVCC(31, 40, 1, 0)
  4470  	case ASUBVCC:
  4471  		return OPVCC(31, 40, 1, 1)
  4472  	case ASUBC:
  4473  		return OPVCC(31, 8, 0, 0)
  4474  	case ASUBCCC:
  4475  		return OPVCC(31, 8, 0, 1)
  4476  	case ASUBCV:
  4477  		return OPVCC(31, 8, 1, 0)
  4478  	case ASUBCVCC:
  4479  		return OPVCC(31, 8, 1, 1)
  4480  	case ASUBE:
  4481  		return OPVCC(31, 136, 0, 0)
  4482  	case ASUBECC:
  4483  		return OPVCC(31, 136, 0, 1)
  4484  	case ASUBEV:
  4485  		return OPVCC(31, 136, 1, 0)
  4486  	case ASUBEVCC:
  4487  		return OPVCC(31, 136, 1, 1)
  4488  	case ASUBME:
  4489  		return OPVCC(31, 232, 0, 0)
  4490  	case ASUBMECC:
  4491  		return OPVCC(31, 232, 0, 1)
  4492  	case ASUBMEV:
  4493  		return OPVCC(31, 232, 1, 0)
  4494  	case ASUBMEVCC:
  4495  		return OPVCC(31, 232, 1, 1)
  4496  	case ASUBZE:
  4497  		return OPVCC(31, 200, 0, 0)
  4498  	case ASUBZECC:
  4499  		return OPVCC(31, 200, 0, 1)
  4500  	case ASUBZEV:
  4501  		return OPVCC(31, 200, 1, 0)
  4502  	case ASUBZEVCC:
  4503  		return OPVCC(31, 200, 1, 1)
  4504  
  4505  	case ASYNC:
  4506  		return OPVCC(31, 598, 0, 0)
  4507  	case ALWSYNC:
  4508  		return OPVCC(31, 598, 0, 0) | 1<<21
  4509  
  4510  	case APTESYNC:
  4511  		return OPVCC(31, 598, 0, 0) | 2<<21
  4512  
  4513  	case ATLBIE:
  4514  		return OPVCC(31, 306, 0, 0)
  4515  	case ATLBIEL:
  4516  		return OPVCC(31, 274, 0, 0)
  4517  	case ATLBSYNC:
  4518  		return OPVCC(31, 566, 0, 0)
  4519  	case ASLBIA:
  4520  		return OPVCC(31, 498, 0, 0)
  4521  	case ASLBIE:
  4522  		return OPVCC(31, 434, 0, 0)
  4523  	case ASLBMFEE:
  4524  		return OPVCC(31, 915, 0, 0)
  4525  	case ASLBMFEV:
  4526  		return OPVCC(31, 851, 0, 0)
  4527  	case ASLBMTE:
  4528  		return OPVCC(31, 402, 0, 0)
  4529  
  4530  	case ATW:
  4531  		return OPVCC(31, 4, 0, 0)
  4532  	case ATD:
  4533  		return OPVCC(31, 68, 0, 0)
  4534  
  4535  	/* Vector (VMX/Altivec) instructions */
  4536  	/* ISA 2.03 enables these for PPC970. For POWERx processors, these */
  4537  	/* are enabled starting at POWER6 (ISA 2.05). */
  4538  	case AVAND:
  4539  		return OPVX(4, 1028, 0, 0) /* vand - v2.03 */
  4540  	case AVANDC:
  4541  		return OPVX(4, 1092, 0, 0) /* vandc - v2.03 */
  4542  	case AVNAND:
  4543  		return OPVX(4, 1412, 0, 0) /* vnand - v2.07 */
  4544  
  4545  	case AVOR:
  4546  		return OPVX(4, 1156, 0, 0) /* vor - v2.03 */
  4547  	case AVORC:
  4548  		return OPVX(4, 1348, 0, 0) /* vorc - v2.07 */
  4549  	case AVNOR:
  4550  		return OPVX(4, 1284, 0, 0) /* vnor - v2.03 */
  4551  	case AVXOR:
  4552  		return OPVX(4, 1220, 0, 0) /* vxor - v2.03 */
  4553  	case AVEQV:
  4554  		return OPVX(4, 1668, 0, 0) /* veqv - v2.07 */
  4555  
  4556  	case AVADDUBM:
  4557  		return OPVX(4, 0, 0, 0) /* vaddubm - v2.03 */
  4558  	case AVADDUHM:
  4559  		return OPVX(4, 64, 0, 0) /* vadduhm - v2.03 */
  4560  	case AVADDUWM:
  4561  		return OPVX(4, 128, 0, 0) /* vadduwm - v2.03 */
  4562  	case AVADDUDM:
  4563  		return OPVX(4, 192, 0, 0) /* vaddudm - v2.07 */
  4564  	case AVADDUQM:
  4565  		return OPVX(4, 256, 0, 0) /* vadduqm - v2.07 */
  4566  
  4567  	case AVADDCUQ:
  4568  		return OPVX(4, 320, 0, 0) /* vaddcuq - v2.07 */
  4569  	case AVADDCUW:
  4570  		return OPVX(4, 384, 0, 0) /* vaddcuw - v2.03 */
  4571  
  4572  	case AVADDUBS:
  4573  		return OPVX(4, 512, 0, 0) /* vaddubs - v2.03 */
  4574  	case AVADDUHS:
  4575  		return OPVX(4, 576, 0, 0) /* vadduhs - v2.03 */
  4576  	case AVADDUWS:
  4577  		return OPVX(4, 640, 0, 0) /* vadduws - v2.03 */
  4578  
  4579  	case AVADDSBS:
  4580  		return OPVX(4, 768, 0, 0) /* vaddsbs - v2.03 */
  4581  	case AVADDSHS:
  4582  		return OPVX(4, 832, 0, 0) /* vaddshs - v2.03 */
  4583  	case AVADDSWS:
  4584  		return OPVX(4, 896, 0, 0) /* vaddsws - v2.03 */
  4585  
  4586  	case AVADDEUQM:
  4587  		return OPVX(4, 60, 0, 0) /* vaddeuqm - v2.07 */
  4588  	case AVADDECUQ:
  4589  		return OPVX(4, 61, 0, 0) /* vaddecuq - v2.07 */
  4590  
  4591  	case AVMULESB:
  4592  		return OPVX(4, 776, 0, 0) /* vmulesb - v2.03 */
  4593  	case AVMULOSB:
  4594  		return OPVX(4, 264, 0, 0) /* vmulosb - v2.03 */
  4595  	case AVMULEUB:
  4596  		return OPVX(4, 520, 0, 0) /* vmuleub - v2.03 */
  4597  	case AVMULOUB:
  4598  		return OPVX(4, 8, 0, 0) /* vmuloub - v2.03 */
  4599  	case AVMULESH:
  4600  		return OPVX(4, 840, 0, 0) /* vmulesh - v2.03 */
  4601  	case AVMULOSH:
  4602  		return OPVX(4, 328, 0, 0) /* vmulosh - v2.03 */
  4603  	case AVMULEUH:
  4604  		return OPVX(4, 584, 0, 0) /* vmuleuh - v2.03 */
  4605  	case AVMULOUH:
  4606  		return OPVX(4, 72, 0, 0) /* vmulouh - v2.03 */
  4607  	case AVMULESW:
  4608  		return OPVX(4, 904, 0, 0) /* vmulesw - v2.07 */
  4609  	case AVMULOSW:
  4610  		return OPVX(4, 392, 0, 0) /* vmulosw - v2.07 */
  4611  	case AVMULEUW:
  4612  		return OPVX(4, 648, 0, 0) /* vmuleuw - v2.07 */
  4613  	case AVMULOUW:
  4614  		return OPVX(4, 136, 0, 0) /* vmulouw - v2.07 */
  4615  	case AVMULUWM:
  4616  		return OPVX(4, 137, 0, 0) /* vmuluwm - v2.07 */
  4617  
  4618  	case AVPMSUMB:
  4619  		return OPVX(4, 1032, 0, 0) /* vpmsumb - v2.07 */
  4620  	case AVPMSUMH:
  4621  		return OPVX(4, 1096, 0, 0) /* vpmsumh - v2.07 */
  4622  	case AVPMSUMW:
  4623  		return OPVX(4, 1160, 0, 0) /* vpmsumw - v2.07 */
  4624  	case AVPMSUMD:
  4625  		return OPVX(4, 1224, 0, 0) /* vpmsumd - v2.07 */
  4626  
  4627  	case AVMSUMUDM:
  4628  		return OPVX(4, 35, 0, 0) /* vmsumudm - v3.00b */
  4629  
  4630  	case AVSUBUBM:
  4631  		return OPVX(4, 1024, 0, 0) /* vsububm - v2.03 */
  4632  	case AVSUBUHM:
  4633  		return OPVX(4, 1088, 0, 0) /* vsubuhm - v2.03 */
  4634  	case AVSUBUWM:
  4635  		return OPVX(4, 1152, 0, 0) /* vsubuwm - v2.03 */
  4636  	case AVSUBUDM:
  4637  		return OPVX(4, 1216, 0, 0) /* vsubudm - v2.07 */
  4638  	case AVSUBUQM:
  4639  		return OPVX(4, 1280, 0, 0) /* vsubuqm - v2.07 */
  4640  
  4641  	case AVSUBCUQ:
  4642  		return OPVX(4, 1344, 0, 0) /* vsubcuq - v2.07 */
  4643  	case AVSUBCUW:
  4644  		return OPVX(4, 1408, 0, 0) /* vsubcuw - v2.03 */
  4645  
  4646  	case AVSUBUBS:
  4647  		return OPVX(4, 1536, 0, 0) /* vsububs - v2.03 */
  4648  	case AVSUBUHS:
  4649  		return OPVX(4, 1600, 0, 0) /* vsubuhs - v2.03 */
  4650  	case AVSUBUWS:
  4651  		return OPVX(4, 1664, 0, 0) /* vsubuws - v2.03 */
  4652  
  4653  	case AVSUBSBS:
  4654  		return OPVX(4, 1792, 0, 0) /* vsubsbs - v2.03 */
  4655  	case AVSUBSHS:
  4656  		return OPVX(4, 1856, 0, 0) /* vsubshs - v2.03 */
  4657  	case AVSUBSWS:
  4658  		return OPVX(4, 1920, 0, 0) /* vsubsws - v2.03 */
  4659  
  4660  	case AVSUBEUQM:
  4661  		return OPVX(4, 62, 0, 0) /* vsubeuqm - v2.07 */
  4662  	case AVSUBECUQ:
  4663  		return OPVX(4, 63, 0, 0) /* vsubecuq - v2.07 */
  4664  
  4665  	case AVRLB:
  4666  		return OPVX(4, 4, 0, 0) /* vrlb - v2.03 */
  4667  	case AVRLH:
  4668  		return OPVX(4, 68, 0, 0) /* vrlh - v2.03 */
  4669  	case AVRLW:
  4670  		return OPVX(4, 132, 0, 0) /* vrlw - v2.03 */
  4671  	case AVRLD:
  4672  		return OPVX(4, 196, 0, 0) /* vrld - v2.07 */
  4673  
  4674  	case AVMRGOW:
  4675  		return OPVX(4, 1676, 0, 0) /* vmrgow - v2.07 */
  4676  	case AVMRGEW:
  4677  		return OPVX(4, 1932, 0, 0) /* vmrgew - v2.07 */
  4678  
  4679  	case AVSLB:
  4680  		return OPVX(4, 260, 0, 0) /* vslh - v2.03 */
  4681  	case AVSLH:
  4682  		return OPVX(4, 324, 0, 0) /* vslh - v2.03 */
  4683  	case AVSLW:
  4684  		return OPVX(4, 388, 0, 0) /* vslw - v2.03 */
  4685  	case AVSL:
  4686  		return OPVX(4, 452, 0, 0) /* vsl - v2.03 */
  4687  	case AVSLO:
  4688  		return OPVX(4, 1036, 0, 0) /* vsl - v2.03 */
  4689  	case AVSRB:
  4690  		return OPVX(4, 516, 0, 0) /* vsrb - v2.03 */
  4691  	case AVSRH:
  4692  		return OPVX(4, 580, 0, 0) /* vsrh - v2.03 */
  4693  	case AVSRW:
  4694  		return OPVX(4, 644, 0, 0) /* vsrw - v2.03 */
  4695  	case AVSR:
  4696  		return OPVX(4, 708, 0, 0) /* vsr - v2.03 */
  4697  	case AVSRO:
  4698  		return OPVX(4, 1100, 0, 0) /* vsro - v2.03 */
  4699  	case AVSLD:
  4700  		return OPVX(4, 1476, 0, 0) /* vsld - v2.07 */
  4701  	case AVSRD:
  4702  		return OPVX(4, 1732, 0, 0) /* vsrd - v2.07 */
  4703  
  4704  	case AVSRAB:
  4705  		return OPVX(4, 772, 0, 0) /* vsrab - v2.03 */
  4706  	case AVSRAH:
  4707  		return OPVX(4, 836, 0, 0) /* vsrah - v2.03 */
  4708  	case AVSRAW:
  4709  		return OPVX(4, 900, 0, 0) /* vsraw - v2.03 */
  4710  	case AVSRAD:
  4711  		return OPVX(4, 964, 0, 0) /* vsrad - v2.07 */
  4712  
  4713  	case AVBPERMQ:
  4714  		return OPVC(4, 1356, 0, 0) /* vbpermq - v2.07 */
  4715  	case AVBPERMD:
  4716  		return OPVC(4, 1484, 0, 0) /* vbpermd - v3.00 */
  4717  
  4718  	case AVCLZB:
  4719  		return OPVX(4, 1794, 0, 0) /* vclzb - v2.07 */
  4720  	case AVCLZH:
  4721  		return OPVX(4, 1858, 0, 0) /* vclzh - v2.07 */
  4722  	case AVCLZW:
  4723  		return OPVX(4, 1922, 0, 0) /* vclzw - v2.07 */
  4724  	case AVCLZD:
  4725  		return OPVX(4, 1986, 0, 0) /* vclzd - v2.07 */
  4726  
  4727  	case AVCLZLSBB:
  4728  		return OPVX(4, 1538, 0, 0) /* vclzlsbb - v3.0 */
  4729  	case AVCTZLSBB:
  4730  		return OPVX(4, 1538, 0, 0) | 1<<16 /* vctzlsbb - v3.0 */
  4731  
  4732  	case AVPOPCNTB:
  4733  		return OPVX(4, 1795, 0, 0) /* vpopcntb - v2.07 */
  4734  	case AVPOPCNTH:
  4735  		return OPVX(4, 1859, 0, 0) /* vpopcnth - v2.07 */
  4736  	case AVPOPCNTW:
  4737  		return OPVX(4, 1923, 0, 0) /* vpopcntw - v2.07 */
  4738  	case AVPOPCNTD:
  4739  		return OPVX(4, 1987, 0, 0) /* vpopcntd - v2.07 */
  4740  
  4741  	case AVCMPEQUB:
  4742  		return OPVC(4, 6, 0, 0) /* vcmpequb - v2.03 */
  4743  	case AVCMPEQUBCC:
  4744  		return OPVC(4, 6, 0, 1) /* vcmpequb. - v2.03 */
  4745  	case AVCMPEQUH:
  4746  		return OPVC(4, 70, 0, 0) /* vcmpequh - v2.03 */
  4747  	case AVCMPEQUHCC:
  4748  		return OPVC(4, 70, 0, 1) /* vcmpequh. - v2.03 */
  4749  	case AVCMPEQUW:
  4750  		return OPVC(4, 134, 0, 0) /* vcmpequw - v2.03 */
  4751  	case AVCMPEQUWCC:
  4752  		return OPVC(4, 134, 0, 1) /* vcmpequw. - v2.03 */
  4753  	case AVCMPEQUD:
  4754  		return OPVC(4, 199, 0, 0) /* vcmpequd - v2.07 */
  4755  	case AVCMPEQUDCC:
  4756  		return OPVC(4, 199, 0, 1) /* vcmpequd. - v2.07 */
  4757  
  4758  	case AVCMPGTUB:
  4759  		return OPVC(4, 518, 0, 0) /* vcmpgtub - v2.03 */
  4760  	case AVCMPGTUBCC:
  4761  		return OPVC(4, 518, 0, 1) /* vcmpgtub. - v2.03 */
  4762  	case AVCMPGTUH:
  4763  		return OPVC(4, 582, 0, 0) /* vcmpgtuh - v2.03 */
  4764  	case AVCMPGTUHCC:
  4765  		return OPVC(4, 582, 0, 1) /* vcmpgtuh. - v2.03 */
  4766  	case AVCMPGTUW:
  4767  		return OPVC(4, 646, 0, 0) /* vcmpgtuw - v2.03 */
  4768  	case AVCMPGTUWCC:
  4769  		return OPVC(4, 646, 0, 1) /* vcmpgtuw. - v2.03 */
  4770  	case AVCMPGTUD:
  4771  		return OPVC(4, 711, 0, 0) /* vcmpgtud - v2.07 */
  4772  	case AVCMPGTUDCC:
  4773  		return OPVC(4, 711, 0, 1) /* vcmpgtud. v2.07 */
  4774  	case AVCMPGTSB:
  4775  		return OPVC(4, 774, 0, 0) /* vcmpgtsb - v2.03 */
  4776  	case AVCMPGTSBCC:
  4777  		return OPVC(4, 774, 0, 1) /* vcmpgtsb. - v2.03 */
  4778  	case AVCMPGTSH:
  4779  		return OPVC(4, 838, 0, 0) /* vcmpgtsh - v2.03 */
  4780  	case AVCMPGTSHCC:
  4781  		return OPVC(4, 838, 0, 1) /* vcmpgtsh. - v2.03 */
  4782  	case AVCMPGTSW:
  4783  		return OPVC(4, 902, 0, 0) /* vcmpgtsw - v2.03 */
  4784  	case AVCMPGTSWCC:
  4785  		return OPVC(4, 902, 0, 1) /* vcmpgtsw. - v2.03 */
  4786  	case AVCMPGTSD:
  4787  		return OPVC(4, 967, 0, 0) /* vcmpgtsd - v2.07 */
  4788  	case AVCMPGTSDCC:
  4789  		return OPVC(4, 967, 0, 1) /* vcmpgtsd. - v2.07 */
  4790  
  4791  	case AVCMPNEZB:
  4792  		return OPVC(4, 263, 0, 0) /* vcmpnezb - v3.00 */
  4793  	case AVCMPNEZBCC:
  4794  		return OPVC(4, 263, 0, 1) /* vcmpnezb. - v3.00 */
  4795  	case AVCMPNEB:
  4796  		return OPVC(4, 7, 0, 0) /* vcmpneb - v3.00 */
  4797  	case AVCMPNEBCC:
  4798  		return OPVC(4, 7, 0, 1) /* vcmpneb. - v3.00 */
  4799  	case AVCMPNEH:
  4800  		return OPVC(4, 71, 0, 0) /* vcmpneh - v3.00 */
  4801  	case AVCMPNEHCC:
  4802  		return OPVC(4, 71, 0, 1) /* vcmpneh. - v3.00 */
  4803  	case AVCMPNEW:
  4804  		return OPVC(4, 135, 0, 0) /* vcmpnew - v3.00 */
  4805  	case AVCMPNEWCC:
  4806  		return OPVC(4, 135, 0, 1) /* vcmpnew. - v3.00 */
  4807  
  4808  	case AVPERM:
  4809  		return OPVX(4, 43, 0, 0) /* vperm - v2.03 */
  4810  	case AVPERMXOR:
  4811  		return OPVX(4, 45, 0, 0) /* vpermxor - v2.03 */
  4812  	case AVPERMR:
  4813  		return OPVX(4, 59, 0, 0) /* vpermr - v3.0 */
  4814  
  4815  	case AVSEL:
  4816  		return OPVX(4, 42, 0, 0) /* vsel - v2.03 */
  4817  
  4818  	case AVCIPHER:
  4819  		return OPVX(4, 1288, 0, 0) /* vcipher - v2.07 */
  4820  	case AVCIPHERLAST:
  4821  		return OPVX(4, 1289, 0, 0) /* vcipherlast - v2.07 */
  4822  	case AVNCIPHER:
  4823  		return OPVX(4, 1352, 0, 0) /* vncipher - v2.07 */
  4824  	case AVNCIPHERLAST:
  4825  		return OPVX(4, 1353, 0, 0) /* vncipherlast - v2.07 */
  4826  	case AVSBOX:
  4827  		return OPVX(4, 1480, 0, 0) /* vsbox - v2.07 */
  4828  	/* End of vector instructions */
  4829  
  4830  	/* Vector scalar (VSX) instructions */
  4831  	/* ISA 2.06 enables these for POWER7. */
  4832  	case AMFVSRD, AMFVRD, AMFFPRD:
  4833  		return OPVXX1(31, 51, 0) /* mfvsrd - v2.07 */
  4834  	case AMFVSRWZ:
  4835  		return OPVXX1(31, 115, 0) /* mfvsrwz - v2.07 */
  4836  	case AMFVSRLD:
  4837  		return OPVXX1(31, 307, 0) /* mfvsrld - v3.00 */
  4838  
  4839  	case AMTVSRD, AMTFPRD, AMTVRD:
  4840  		return OPVXX1(31, 179, 0) /* mtvsrd - v2.07 */
  4841  	case AMTVSRWA:
  4842  		return OPVXX1(31, 211, 0) /* mtvsrwa - v2.07 */
  4843  	case AMTVSRWZ:
  4844  		return OPVXX1(31, 243, 0) /* mtvsrwz - v2.07 */
  4845  	case AMTVSRDD:
  4846  		return OPVXX1(31, 435, 0) /* mtvsrdd - v3.00 */
  4847  	case AMTVSRWS:
  4848  		return OPVXX1(31, 403, 0) /* mtvsrws - v3.00 */
  4849  
  4850  	case AXXLAND:
  4851  		return OPVXX3(60, 130, 0) /* xxland - v2.06 */
  4852  	case AXXLANDC:
  4853  		return OPVXX3(60, 138, 0) /* xxlandc - v2.06 */
  4854  	case AXXLEQV:
  4855  		return OPVXX3(60, 186, 0) /* xxleqv - v2.07 */
  4856  	case AXXLNAND:
  4857  		return OPVXX3(60, 178, 0) /* xxlnand - v2.07 */
  4858  
  4859  	case AXXLORC:
  4860  		return OPVXX3(60, 170, 0) /* xxlorc - v2.07 */
  4861  	case AXXLNOR:
  4862  		return OPVXX3(60, 162, 0) /* xxlnor - v2.06 */
  4863  	case AXXLOR, AXXLORQ:
  4864  		return OPVXX3(60, 146, 0) /* xxlor - v2.06 */
  4865  	case AXXLXOR:
  4866  		return OPVXX3(60, 154, 0) /* xxlxor - v2.06 */
  4867  	case AXSMINJDP:
  4868  		return OPVXX3(60, 152, 0) /* xsminjdp - v3.0 */
  4869  	case AXSMAXJDP:
  4870  		return OPVXX3(60, 144, 0) /* xsmaxjdp - v3.0 */
  4871  
  4872  	case AXXSEL:
  4873  		return OPVXX4(60, 3, 0) /* xxsel - v2.06 */
  4874  
  4875  	case AXXMRGHW:
  4876  		return OPVXX3(60, 18, 0) /* xxmrghw - v2.06 */
  4877  	case AXXMRGLW:
  4878  		return OPVXX3(60, 50, 0) /* xxmrglw - v2.06 */
  4879  
  4880  	case AXXSPLTW:
  4881  		return OPVXX2(60, 164, 0) /* xxspltw - v2.06 */
  4882  
  4883  	case AXXSPLTIB:
  4884  		return OPVCC(60, 360, 0, 0) /* xxspltib - v3.0 */
  4885  
  4886  	case AXXPERM:
  4887  		return OPVXX3(60, 26, 0) /* xxperm - v2.06 */
  4888  	case AXXPERMDI:
  4889  		return OPVXX3(60, 10, 0) /* xxpermdi - v2.06 */
  4890  
  4891  	case AXXSLDWI:
  4892  		return OPVXX3(60, 2, 0) /* xxsldwi - v2.06 */
  4893  
  4894  	case AXXBRQ:
  4895  		return OPVXX2VA(60, 475, 31) /* xxbrq - v3.0 */
  4896  	case AXXBRD:
  4897  		return OPVXX2VA(60, 475, 23) /* xxbrd - v3.0 */
  4898  	case AXXBRW:
  4899  		return OPVXX2VA(60, 475, 15) /* xxbrw - v3.0 */
  4900  	case AXXBRH:
  4901  		return OPVXX2VA(60, 475, 7) /* xxbrh - v3.0 */
  4902  
  4903  	case AXSCVDPSP:
  4904  		return OPVXX2(60, 265, 0) /* xscvdpsp - v2.06 */
  4905  	case AXSCVSPDP:
  4906  		return OPVXX2(60, 329, 0) /* xscvspdp - v2.06 */
  4907  	case AXSCVDPSPN:
  4908  		return OPVXX2(60, 267, 0) /* xscvdpspn - v2.07 */
  4909  	case AXSCVSPDPN:
  4910  		return OPVXX2(60, 331, 0) /* xscvspdpn - v2.07 */
  4911  
  4912  	case AXVCVDPSP:
  4913  		return OPVXX2(60, 393, 0) /* xvcvdpsp - v2.06 */
  4914  	case AXVCVSPDP:
  4915  		return OPVXX2(60, 457, 0) /* xvcvspdp - v2.06 */
  4916  
  4917  	case AXSCVDPSXDS:
  4918  		return OPVXX2(60, 344, 0) /* xscvdpsxds - v2.06 */
  4919  	case AXSCVDPSXWS:
  4920  		return OPVXX2(60, 88, 0) /* xscvdpsxws - v2.06 */
  4921  	case AXSCVDPUXDS:
  4922  		return OPVXX2(60, 328, 0) /* xscvdpuxds - v2.06 */
  4923  	case AXSCVDPUXWS:
  4924  		return OPVXX2(60, 72, 0) /* xscvdpuxws - v2.06 */
  4925  
  4926  	case AXSCVSXDDP:
  4927  		return OPVXX2(60, 376, 0) /* xscvsxddp - v2.06 */
  4928  	case AXSCVUXDDP:
  4929  		return OPVXX2(60, 360, 0) /* xscvuxddp - v2.06 */
  4930  	case AXSCVSXDSP:
  4931  		return OPVXX2(60, 312, 0) /* xscvsxdsp - v2.06 */
  4932  	case AXSCVUXDSP:
  4933  		return OPVXX2(60, 296, 0) /* xscvuxdsp - v2.06 */
  4934  
  4935  	case AXVCVDPSXDS:
  4936  		return OPVXX2(60, 472, 0) /* xvcvdpsxds - v2.06 */
  4937  	case AXVCVDPSXWS:
  4938  		return OPVXX2(60, 216, 0) /* xvcvdpsxws - v2.06 */
  4939  	case AXVCVDPUXDS:
  4940  		return OPVXX2(60, 456, 0) /* xvcvdpuxds - v2.06 */
  4941  	case AXVCVDPUXWS:
  4942  		return OPVXX2(60, 200, 0) /* xvcvdpuxws - v2.06 */
  4943  	case AXVCVSPSXDS:
  4944  		return OPVXX2(60, 408, 0) /* xvcvspsxds - v2.07 */
  4945  	case AXVCVSPSXWS:
  4946  		return OPVXX2(60, 152, 0) /* xvcvspsxws - v2.07 */
  4947  	case AXVCVSPUXDS:
  4948  		return OPVXX2(60, 392, 0) /* xvcvspuxds - v2.07 */
  4949  	case AXVCVSPUXWS:
  4950  		return OPVXX2(60, 136, 0) /* xvcvspuxws - v2.07 */
  4951  
  4952  	case AXVCVSXDDP:
  4953  		return OPVXX2(60, 504, 0) /* xvcvsxddp - v2.06 */
  4954  	case AXVCVSXWDP:
  4955  		return OPVXX2(60, 248, 0) /* xvcvsxwdp - v2.06 */
  4956  	case AXVCVUXDDP:
  4957  		return OPVXX2(60, 488, 0) /* xvcvuxddp - v2.06 */
  4958  	case AXVCVUXWDP:
  4959  		return OPVXX2(60, 232, 0) /* xvcvuxwdp - v2.06 */
  4960  	case AXVCVSXDSP:
  4961  		return OPVXX2(60, 440, 0) /* xvcvsxdsp - v2.06 */
  4962  	case AXVCVSXWSP:
  4963  		return OPVXX2(60, 184, 0) /* xvcvsxwsp - v2.06 */
  4964  	case AXVCVUXDSP:
  4965  		return OPVXX2(60, 424, 0) /* xvcvuxdsp - v2.06 */
  4966  	case AXVCVUXWSP:
  4967  		return OPVXX2(60, 168, 0) /* xvcvuxwsp - v2.06 */
  4968  	/* End of VSX instructions */
  4969  
  4970  	case AMADDHD:
  4971  		return OPVX(4, 48, 0, 0) /* maddhd - v3.00 */
  4972  	case AMADDHDU:
  4973  		return OPVX(4, 49, 0, 0) /* maddhdu - v3.00 */
  4974  	case AMADDLD:
  4975  		return OPVX(4, 51, 0, 0) /* maddld - v3.00 */
  4976  
  4977  	case AXOR:
  4978  		return OPVCC(31, 316, 0, 0)
  4979  	case AXORCC:
  4980  		return OPVCC(31, 316, 0, 1)
  4981  	}
  4982  
  4983  	c.ctxt.Diag("bad r/r, r/r/r or r/r/r/r opcode %v", a)
  4984  	return 0
  4985  }
  4986  
  4987  func (c *ctxt9) opirrr(a obj.As) uint32 {
  4988  	switch a {
  4989  	/* Vector (VMX/Altivec) instructions */
  4990  	/* ISA 2.03 enables these for PPC970. For POWERx processors, these */
  4991  	/* are enabled starting at POWER6 (ISA 2.05). */
  4992  	case AVSLDOI:
  4993  		return OPVX(4, 44, 0, 0) /* vsldoi - v2.03 */
  4994  	}
  4995  
  4996  	c.ctxt.Diag("bad i/r/r/r opcode %v", a)
  4997  	return 0
  4998  }
  4999  
  5000  func (c *ctxt9) opiirr(a obj.As) uint32 {
  5001  	switch a {
  5002  	/* Vector (VMX/Altivec) instructions */
  5003  	/* ISA 2.07 enables these for POWER8 and beyond. */
  5004  	case AVSHASIGMAW:
  5005  		return OPVX(4, 1666, 0, 0) /* vshasigmaw - v2.07 */
  5006  	case AVSHASIGMAD:
  5007  		return OPVX(4, 1730, 0, 0) /* vshasigmad - v2.07 */
  5008  	}
  5009  
  5010  	c.ctxt.Diag("bad i/i/r/r opcode %v", a)
  5011  	return 0
  5012  }
  5013  
  5014  func (c *ctxt9) opirr(a obj.As) uint32 {
  5015  	switch a {
  5016  	case AADD:
  5017  		return OPVCC(14, 0, 0, 0)
  5018  	case AADDC:
  5019  		return OPVCC(12, 0, 0, 0)
  5020  	case AADDCCC:
  5021  		return OPVCC(13, 0, 0, 0)
  5022  	case AADDIS:
  5023  		return OPVCC(15, 0, 0, 0) /* ADDIS */
  5024  
  5025  	case AANDCC:
  5026  		return OPVCC(28, 0, 0, 0)
  5027  	case AANDISCC:
  5028  		return OPVCC(29, 0, 0, 0) /* ANDIS. */
  5029  
  5030  	case ABR:
  5031  		return OPVCC(18, 0, 0, 0)
  5032  	case ABL:
  5033  		return OPVCC(18, 0, 0, 0) | 1
  5034  	case obj.ADUFFZERO:
  5035  		return OPVCC(18, 0, 0, 0) | 1
  5036  	case obj.ADUFFCOPY:
  5037  		return OPVCC(18, 0, 0, 0) | 1
  5038  	case ABC:
  5039  		return OPVCC(16, 0, 0, 0)
  5040  	case ABCL:
  5041  		return OPVCC(16, 0, 0, 0) | 1
  5042  
  5043  	case ABEQ:
  5044  		return AOP_RRR(16<<26, BO_BCR, BI_EQ, 0)
  5045  	case ABGE:
  5046  		return AOP_RRR(16<<26, BO_NOTBCR, BI_LT, 0)
  5047  	case ABGT:
  5048  		return AOP_RRR(16<<26, BO_BCR, BI_GT, 0)
  5049  	case ABLE:
  5050  		return AOP_RRR(16<<26, BO_NOTBCR, BI_GT, 0)
  5051  	case ABLT:
  5052  		return AOP_RRR(16<<26, BO_BCR, BI_LT, 0)
  5053  	case ABNE:
  5054  		return AOP_RRR(16<<26, BO_NOTBCR, BI_EQ, 0)
  5055  	case ABVC:
  5056  		return AOP_RRR(16<<26, BO_NOTBCR, BI_FU, 0)
  5057  	case ABVS:
  5058  		return AOP_RRR(16<<26, BO_BCR, BI_FU, 0)
  5059  	case ABDZ:
  5060  		return AOP_RRR(16<<26, BO_NOTBCTR, 0, 0)
  5061  	case ABDNZ:
  5062  		return AOP_RRR(16<<26, BO_BCTR, 0, 0)
  5063  
  5064  	case ACMP:
  5065  		return OPVCC(11, 0, 0, 0) | 1<<21 /* L=1 */
  5066  	case ACMPU:
  5067  		return OPVCC(10, 0, 0, 0) | 1<<21
  5068  	case ACMPW:
  5069  		return OPVCC(11, 0, 0, 0) /* L=0 */
  5070  	case ACMPWU:
  5071  		return OPVCC(10, 0, 0, 0)
  5072  	case ACMPEQB:
  5073  		return OPVCC(31, 224, 0, 0) /* cmpeqb - v3.00 */
  5074  
  5075  	case ALSW:
  5076  		return OPVCC(31, 597, 0, 0)
  5077  
  5078  	case ACOPY:
  5079  		return OPVCC(31, 774, 0, 0) /* copy - v3.00 */
  5080  	case APASTECC:
  5081  		return OPVCC(31, 902, 0, 1) /* paste. - v3.00 */
  5082  	case ADARN:
  5083  		return OPVCC(31, 755, 0, 0) /* darn - v3.00 */
  5084  
  5085  	case AMULLW, AMULLD:
  5086  		return OPVCC(7, 0, 0, 0) /* mulli works with MULLW or MULLD */
  5087  
  5088  	case AOR:
  5089  		return OPVCC(24, 0, 0, 0)
  5090  	case AORIS:
  5091  		return OPVCC(25, 0, 0, 0) /* ORIS */
  5092  
  5093  	case ARLWMI:
  5094  		return OPVCC(20, 0, 0, 0) /* rlwimi */
  5095  	case ARLWMICC:
  5096  		return OPVCC(20, 0, 0, 1)
  5097  	case ARLDMI:
  5098  		return OPMD(30, 3, 0) /* rldimi */
  5099  	case ARLDMICC:
  5100  		return OPMD(30, 3, 1) /* rldimi. */
  5101  	case ARLDIMI:
  5102  		return OPMD(30, 3, 0) /* rldimi */
  5103  	case ARLDIMICC:
  5104  		return OPMD(30, 3, 1) /* rldimi. */
  5105  	case ARLWNM:
  5106  		return OPVCC(21, 0, 0, 0) /* rlwinm */
  5107  	case ARLWNMCC:
  5108  		return OPVCC(21, 0, 0, 1)
  5109  
  5110  	case ARLDCL:
  5111  		return OPMD(30, 0, 0) /* rldicl */
  5112  	case ARLDCLCC:
  5113  		return OPMD(30, 0, 1) /* rldicl. */
  5114  	case ARLDCR:
  5115  		return OPMD(30, 1, 0) /* rldicr */
  5116  	case ARLDCRCC:
  5117  		return OPMD(30, 1, 1) /* rldicr. */
  5118  	case ARLDC:
  5119  		return OPMD(30, 2, 0) /* rldic */
  5120  	case ARLDCCC:
  5121  		return OPMD(30, 2, 1) /* rldic. */
  5122  
  5123  	case ASRAW:
  5124  		return OPVCC(31, 824, 0, 0)
  5125  	case ASRAWCC:
  5126  		return OPVCC(31, 824, 0, 1)
  5127  	case ASRAD:
  5128  		return OPVCC(31, (413 << 1), 0, 0)
  5129  	case ASRADCC:
  5130  		return OPVCC(31, (413 << 1), 0, 1)
  5131  	case AEXTSWSLI:
  5132  		return OPVCC(31, 445, 0, 0)
  5133  	case AEXTSWSLICC:
  5134  		return OPVCC(31, 445, 0, 1)
  5135  
  5136  	case ASTSW:
  5137  		return OPVCC(31, 725, 0, 0)
  5138  
  5139  	case ASUBC:
  5140  		return OPVCC(8, 0, 0, 0)
  5141  
  5142  	case ATW:
  5143  		return OPVCC(3, 0, 0, 0)
  5144  	case ATD:
  5145  		return OPVCC(2, 0, 0, 0)
  5146  
  5147  	/* Vector (VMX/Altivec) instructions */
  5148  	/* ISA 2.03 enables these for PPC970. For POWERx processors, these */
  5149  	/* are enabled starting at POWER6 (ISA 2.05). */
  5150  	case AVSPLTB:
  5151  		return OPVX(4, 524, 0, 0) /* vspltb - v2.03 */
  5152  	case AVSPLTH:
  5153  		return OPVX(4, 588, 0, 0) /* vsplth - v2.03 */
  5154  	case AVSPLTW:
  5155  		return OPVX(4, 652, 0, 0) /* vspltw - v2.03 */
  5156  
  5157  	case AVSPLTISB:
  5158  		return OPVX(4, 780, 0, 0) /* vspltisb - v2.03 */
  5159  	case AVSPLTISH:
  5160  		return OPVX(4, 844, 0, 0) /* vspltish - v2.03 */
  5161  	case AVSPLTISW:
  5162  		return OPVX(4, 908, 0, 0) /* vspltisw - v2.03 */
  5163  	/* End of vector instructions */
  5164  
  5165  	case AFTDIV:
  5166  		return OPVCC(63, 128, 0, 0) /* ftdiv - v2.06 */
  5167  	case AFTSQRT:
  5168  		return OPVCC(63, 160, 0, 0) /* ftsqrt - v2.06 */
  5169  
  5170  	case AXOR:
  5171  		return OPVCC(26, 0, 0, 0) /* XORIL */
  5172  	case AXORIS:
  5173  		return OPVCC(27, 0, 0, 0) /* XORIS */
  5174  	}
  5175  
  5176  	c.ctxt.Diag("bad opcode i/r or i/r/r %v", a)
  5177  	return 0
  5178  }
  5179  
  5180  /*
  5181   * load o(a),d
  5182   */
  5183  func (c *ctxt9) opload(a obj.As) uint32 {
  5184  	switch a {
  5185  	case AMOVD:
  5186  		return OPVCC(58, 0, 0, 0) /* ld */
  5187  	case AMOVDU:
  5188  		return OPVCC(58, 0, 0, 1) /* ldu */
  5189  	case AMOVWZ:
  5190  		return OPVCC(32, 0, 0, 0) /* lwz */
  5191  	case AMOVWZU:
  5192  		return OPVCC(33, 0, 0, 0) /* lwzu */
  5193  	case AMOVW:
  5194  		return OPVCC(58, 0, 0, 0) | 1<<1 /* lwa */
  5195  	case ALXV:
  5196  		return OPDQ(61, 1, 0) /* lxv - ISA v3.0 */
  5197  	case ALXVL:
  5198  		return OPVXX1(31, 269, 0) /* lxvl - ISA v3.0 */
  5199  	case ALXVLL:
  5200  		return OPVXX1(31, 301, 0) /* lxvll - ISA v3.0 */
  5201  	case ALXVX:
  5202  		return OPVXX1(31, 268, 0) /* lxvx - ISA v3.0 */
  5203  
  5204  		/* no AMOVWU */
  5205  	case AMOVB, AMOVBZ:
  5206  		return OPVCC(34, 0, 0, 0)
  5207  		/* load */
  5208  
  5209  	case AMOVBU, AMOVBZU:
  5210  		return OPVCC(35, 0, 0, 0)
  5211  	case AFMOVD:
  5212  		return OPVCC(50, 0, 0, 0)
  5213  	case AFMOVDU:
  5214  		return OPVCC(51, 0, 0, 0)
  5215  	case AFMOVS:
  5216  		return OPVCC(48, 0, 0, 0)
  5217  	case AFMOVSU:
  5218  		return OPVCC(49, 0, 0, 0)
  5219  	case AMOVH:
  5220  		return OPVCC(42, 0, 0, 0)
  5221  	case AMOVHU:
  5222  		return OPVCC(43, 0, 0, 0)
  5223  	case AMOVHZ:
  5224  		return OPVCC(40, 0, 0, 0)
  5225  	case AMOVHZU:
  5226  		return OPVCC(41, 0, 0, 0)
  5227  	case AMOVMW:
  5228  		return OPVCC(46, 0, 0, 0) /* lmw */
  5229  	}
  5230  
  5231  	c.ctxt.Diag("bad load opcode %v", a)
  5232  	return 0
  5233  }
  5234  
  5235  /*
  5236   * indexed load a(b),d
  5237   */
  5238  func (c *ctxt9) oploadx(a obj.As) uint32 {
  5239  	switch a {
  5240  	case AMOVWZ:
  5241  		return OPVCC(31, 23, 0, 0) /* lwzx */
  5242  	case AMOVWZU:
  5243  		return OPVCC(31, 55, 0, 0) /* lwzux */
  5244  	case AMOVW:
  5245  		return OPVCC(31, 341, 0, 0) /* lwax */
  5246  	case AMOVWU:
  5247  		return OPVCC(31, 373, 0, 0) /* lwaux */
  5248  
  5249  	case AMOVB, AMOVBZ:
  5250  		return OPVCC(31, 87, 0, 0) /* lbzx */
  5251  
  5252  	case AMOVBU, AMOVBZU:
  5253  		return OPVCC(31, 119, 0, 0) /* lbzux */
  5254  	case AFMOVD:
  5255  		return OPVCC(31, 599, 0, 0) /* lfdx */
  5256  	case AFMOVDU:
  5257  		return OPVCC(31, 631, 0, 0) /*  lfdux */
  5258  	case AFMOVS:
  5259  		return OPVCC(31, 535, 0, 0) /* lfsx */
  5260  	case AFMOVSU:
  5261  		return OPVCC(31, 567, 0, 0) /* lfsux */
  5262  	case AFMOVSX:
  5263  		return OPVCC(31, 855, 0, 0) /* lfiwax - power6, isa 2.05 */
  5264  	case AFMOVSZ:
  5265  		return OPVCC(31, 887, 0, 0) /* lfiwzx - power7, isa 2.06 */
  5266  	case AMOVH:
  5267  		return OPVCC(31, 343, 0, 0) /* lhax */
  5268  	case AMOVHU:
  5269  		return OPVCC(31, 375, 0, 0) /* lhaux */
  5270  	case AMOVHBR:
  5271  		return OPVCC(31, 790, 0, 0) /* lhbrx */
  5272  	case AMOVWBR:
  5273  		return OPVCC(31, 534, 0, 0) /* lwbrx */
  5274  	case AMOVDBR:
  5275  		return OPVCC(31, 532, 0, 0) /* ldbrx */
  5276  	case AMOVHZ:
  5277  		return OPVCC(31, 279, 0, 0) /* lhzx */
  5278  	case AMOVHZU:
  5279  		return OPVCC(31, 311, 0, 0) /* lhzux */
  5280  	case ALBAR:
  5281  		return OPVCC(31, 52, 0, 0) /* lbarx */
  5282  	case ALHAR:
  5283  		return OPVCC(31, 116, 0, 0) /* lharx */
  5284  	case ALWAR:
  5285  		return OPVCC(31, 20, 0, 0) /* lwarx */
  5286  	case ALDAR:
  5287  		return OPVCC(31, 84, 0, 0) /* ldarx */
  5288  	case ALSW:
  5289  		return OPVCC(31, 533, 0, 0) /* lswx */
  5290  	case AMOVD:
  5291  		return OPVCC(31, 21, 0, 0) /* ldx */
  5292  	case AMOVDU:
  5293  		return OPVCC(31, 53, 0, 0) /* ldux */
  5294  
  5295  	/* Vector (VMX/Altivec) instructions */
  5296  	case ALVEBX:
  5297  		return OPVCC(31, 7, 0, 0) /* lvebx - v2.03 */
  5298  	case ALVEHX:
  5299  		return OPVCC(31, 39, 0, 0) /* lvehx - v2.03 */
  5300  	case ALVEWX:
  5301  		return OPVCC(31, 71, 0, 0) /* lvewx - v2.03 */
  5302  	case ALVX:
  5303  		return OPVCC(31, 103, 0, 0) /* lvx - v2.03 */
  5304  	case ALVXL:
  5305  		return OPVCC(31, 359, 0, 0) /* lvxl - v2.03 */
  5306  	case ALVSL:
  5307  		return OPVCC(31, 6, 0, 0) /* lvsl - v2.03 */
  5308  	case ALVSR:
  5309  		return OPVCC(31, 38, 0, 0) /* lvsr - v2.03 */
  5310  		/* End of vector instructions */
  5311  
  5312  	/* Vector scalar (VSX) instructions */
  5313  	case ALXVX:
  5314  		return OPVXX1(31, 268, 0) /* lxvx - ISA v3.0 */
  5315  	case ALXVD2X:
  5316  		return OPVXX1(31, 844, 0) /* lxvd2x - v2.06 */
  5317  	case ALXVW4X:
  5318  		return OPVXX1(31, 780, 0) /* lxvw4x - v2.06 */
  5319  	case ALXVH8X:
  5320  		return OPVXX1(31, 812, 0) /* lxvh8x - v3.00 */
  5321  	case ALXVB16X:
  5322  		return OPVXX1(31, 876, 0) /* lxvb16x - v3.00 */
  5323  	case ALXVDSX:
  5324  		return OPVXX1(31, 332, 0) /* lxvdsx - v2.06 */
  5325  	case ALXSDX:
  5326  		return OPVXX1(31, 588, 0) /* lxsdx - v2.06 */
  5327  	case ALXSIWAX:
  5328  		return OPVXX1(31, 76, 0) /* lxsiwax - v2.07 */
  5329  	case ALXSIWZX:
  5330  		return OPVXX1(31, 12, 0) /* lxsiwzx - v2.07 */
  5331  	}
  5332  
  5333  	c.ctxt.Diag("bad loadx opcode %v", a)
  5334  	return 0
  5335  }
  5336  
  5337  /*
  5338   * store s,o(d)
  5339   */
  5340  func (c *ctxt9) opstore(a obj.As) uint32 {
  5341  	switch a {
  5342  	case AMOVB, AMOVBZ:
  5343  		return OPVCC(38, 0, 0, 0) /* stb */
  5344  
  5345  	case AMOVBU, AMOVBZU:
  5346  		return OPVCC(39, 0, 0, 0) /* stbu */
  5347  	case AFMOVD:
  5348  		return OPVCC(54, 0, 0, 0) /* stfd */
  5349  	case AFMOVDU:
  5350  		return OPVCC(55, 0, 0, 0) /* stfdu */
  5351  	case AFMOVS:
  5352  		return OPVCC(52, 0, 0, 0) /* stfs */
  5353  	case AFMOVSU:
  5354  		return OPVCC(53, 0, 0, 0) /* stfsu */
  5355  
  5356  	case AMOVHZ, AMOVH:
  5357  		return OPVCC(44, 0, 0, 0) /* sth */
  5358  
  5359  	case AMOVHZU, AMOVHU:
  5360  		return OPVCC(45, 0, 0, 0) /* sthu */
  5361  	case AMOVMW:
  5362  		return OPVCC(47, 0, 0, 0) /* stmw */
  5363  	case ASTSW:
  5364  		return OPVCC(31, 725, 0, 0) /* stswi */
  5365  
  5366  	case AMOVWZ, AMOVW:
  5367  		return OPVCC(36, 0, 0, 0) /* stw */
  5368  
  5369  	case AMOVWZU, AMOVWU:
  5370  		return OPVCC(37, 0, 0, 0) /* stwu */
  5371  	case AMOVD:
  5372  		return OPVCC(62, 0, 0, 0) /* std */
  5373  	case AMOVDU:
  5374  		return OPVCC(62, 0, 0, 1) /* stdu */
  5375  	case ASTXV:
  5376  		return OPDQ(61, 5, 0) /* stxv ISA 3.0 */
  5377  	case ASTXVL:
  5378  		return OPVXX1(31, 397, 0) /* stxvl ISA 3.0 */
  5379  	case ASTXVLL:
  5380  		return OPVXX1(31, 429, 0) /* stxvll ISA 3.0 */
  5381  	case ASTXVX:
  5382  		return OPVXX1(31, 396, 0) /* stxvx - ISA v3.0 */
  5383  
  5384  	}
  5385  
  5386  	c.ctxt.Diag("unknown store opcode %v", a)
  5387  	return 0
  5388  }
  5389  
  5390  /*
  5391   * indexed store s,a(b)
  5392   */
  5393  func (c *ctxt9) opstorex(a obj.As) uint32 {
  5394  	switch a {
  5395  	case AMOVB, AMOVBZ:
  5396  		return OPVCC(31, 215, 0, 0) /* stbx */
  5397  
  5398  	case AMOVBU, AMOVBZU:
  5399  		return OPVCC(31, 247, 0, 0) /* stbux */
  5400  	case AFMOVD:
  5401  		return OPVCC(31, 727, 0, 0) /* stfdx */
  5402  	case AFMOVDU:
  5403  		return OPVCC(31, 759, 0, 0) /* stfdux */
  5404  	case AFMOVS:
  5405  		return OPVCC(31, 663, 0, 0) /* stfsx */
  5406  	case AFMOVSU:
  5407  		return OPVCC(31, 695, 0, 0) /* stfsux */
  5408  	case AFMOVSX:
  5409  		return OPVCC(31, 983, 0, 0) /* stfiwx */
  5410  
  5411  	case AMOVHZ, AMOVH:
  5412  		return OPVCC(31, 407, 0, 0) /* sthx */
  5413  	case AMOVHBR:
  5414  		return OPVCC(31, 918, 0, 0) /* sthbrx */
  5415  
  5416  	case AMOVHZU, AMOVHU:
  5417  		return OPVCC(31, 439, 0, 0) /* sthux */
  5418  
  5419  	case AMOVWZ, AMOVW:
  5420  		return OPVCC(31, 151, 0, 0) /* stwx */
  5421  
  5422  	case AMOVWZU, AMOVWU:
  5423  		return OPVCC(31, 183, 0, 0) /* stwux */
  5424  	case ASTSW:
  5425  		return OPVCC(31, 661, 0, 0) /* stswx */
  5426  	case AMOVWBR:
  5427  		return OPVCC(31, 662, 0, 0) /* stwbrx */
  5428  	case AMOVDBR:
  5429  		return OPVCC(31, 660, 0, 0) /* stdbrx */
  5430  	case ASTBCCC:
  5431  		return OPVCC(31, 694, 0, 1) /* stbcx. */
  5432  	case ASTHCCC:
  5433  		return OPVCC(31, 726, 0, 1) /* sthcx. */
  5434  	case ASTWCCC:
  5435  		return OPVCC(31, 150, 0, 1) /* stwcx. */
  5436  	case ASTDCCC:
  5437  		return OPVCC(31, 214, 0, 1) /* stwdx. */
  5438  	case AMOVD:
  5439  		return OPVCC(31, 149, 0, 0) /* stdx */
  5440  	case AMOVDU:
  5441  		return OPVCC(31, 181, 0, 0) /* stdux */
  5442  
  5443  	/* Vector (VMX/Altivec) instructions */
  5444  	case ASTVEBX:
  5445  		return OPVCC(31, 135, 0, 0) /* stvebx - v2.03 */
  5446  	case ASTVEHX:
  5447  		return OPVCC(31, 167, 0, 0) /* stvehx - v2.03 */
  5448  	case ASTVEWX:
  5449  		return OPVCC(31, 199, 0, 0) /* stvewx - v2.03 */
  5450  	case ASTVX:
  5451  		return OPVCC(31, 231, 0, 0) /* stvx - v2.03 */
  5452  	case ASTVXL:
  5453  		return OPVCC(31, 487, 0, 0) /* stvxl - v2.03 */
  5454  		/* End of vector instructions */
  5455  
  5456  	/* Vector scalar (VSX) instructions */
  5457  	case ASTXVX:
  5458  		return OPVXX1(31, 396, 0) /* stxvx - v3.0 */
  5459  	case ASTXVD2X:
  5460  		return OPVXX1(31, 972, 0) /* stxvd2x - v2.06 */
  5461  	case ASTXVW4X:
  5462  		return OPVXX1(31, 908, 0) /* stxvw4x - v2.06 */
  5463  	case ASTXVH8X:
  5464  		return OPVXX1(31, 940, 0) /* stxvh8x - v3.0 */
  5465  	case ASTXVB16X:
  5466  		return OPVXX1(31, 1004, 0) /* stxvb16x - v3.0 */
  5467  
  5468  	case ASTXSDX:
  5469  		return OPVXX1(31, 716, 0) /* stxsdx - v2.06 */
  5470  
  5471  	case ASTXSIWX:
  5472  		return OPVXX1(31, 140, 0) /* stxsiwx - v2.07 */
  5473  
  5474  		/* End of vector scalar instructions */
  5475  
  5476  	}
  5477  
  5478  	c.ctxt.Diag("unknown storex opcode %v", a)
  5479  	return 0
  5480  }
  5481  

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