1
2
3
4
5 package loong64
6
7 import (
8 "cmd/internal/obj"
9 "cmd/internal/objabi"
10 "fmt"
11 "log"
12 "math/bits"
13 "slices"
14 )
15
16
17
18
19 type ctxt0 struct {
20 ctxt *obj.Link
21 newprog obj.ProgAlloc
22 cursym *obj.LSym
23 autosize int32
24 instoffset int64
25 pc int64
26 }
27
28
29
30 const (
31 FuncAlign = 4
32 loopAlign = 16
33 )
34
35 type Optab struct {
36 as obj.As
37 from1 uint8
38 reg uint8
39 from3 uint8
40 to1 uint8
41 to2 uint8
42 type_ int8
43 size int8
44 param int16
45 flag uint8
46 }
47
48 const (
49 NOTUSETMP = 1 << iota
50
51
52
53 branchLoopHead
54 )
55
56 var optab = []Optab{
57 {obj.ATEXT, C_ADDR, C_NONE, C_NONE, C_TEXTSIZE, C_NONE, 0, 0, 0, 0},
58
59 {AMOVW, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 1, 4, 0, 0},
60 {AMOVV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 1, 4, 0, 0},
61 {AMOVB, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 12, 4, 0, 0},
62 {AMOVBU, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 12, 4, 0, 0},
63 {AMOVWU, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 12, 4, 0, 0},
64
65 {ASUB, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
66 {ASUBV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
67 {AADD, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
68 {AADDV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
69 {AAND, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
70 {ASUB, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
71 {ASUBV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
72 {AADD, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
73 {AADDV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
74 {AAND, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
75 {ANEGW, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
76 {ANEGV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
77 {AMASKEQZ, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
78 {ASLL, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
79 {ASLL, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
80 {ASLLV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
81 {ASLLV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
82 {AMUL, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
83 {AMUL, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
84 {AMULV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
85 {AMULV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
86 {AADDF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 2, 4, 0, 0},
87 {AADDF, C_FREG, C_FREG, C_NONE, C_FREG, C_NONE, 2, 4, 0, 0},
88 {ACMPEQF, C_FREG, C_FREG, C_NONE, C_FCCREG, C_NONE, 2, 4, 0, 0},
89
90 {AVSEQB, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
91 {AXVSEQB, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
92 {AVSEQB, C_S5CON, C_VREG, C_NONE, C_VREG, C_NONE, 22, 4, 0, 0},
93 {AXVSEQB, C_S5CON, C_XREG, C_NONE, C_XREG, C_NONE, 22, 4, 0, 0},
94 {AVANDV, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
95 {AVANDV, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
96 {AXVANDV, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
97 {AXVANDV, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
98 {AVANDB, C_U8CON, C_VREG, C_NONE, C_VREG, C_NONE, 23, 4, 0, 0},
99 {AVANDB, C_U8CON, C_NONE, C_NONE, C_VREG, C_NONE, 23, 4, 0, 0},
100 {AXVANDB, C_U8CON, C_XREG, C_NONE, C_XREG, C_NONE, 23, 4, 0, 0},
101 {AXVANDB, C_U8CON, C_NONE, C_NONE, C_XREG, C_NONE, 23, 4, 0, 0},
102
103 {AVADDB, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
104 {AVADDB, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
105 {AXVADDB, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
106 {AXVADDB, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
107
108 {AVSLLB, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
109 {AVSLLB, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
110 {AXVSLLB, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
111 {AXVSLLB, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
112 {AVSLLB, C_U3CON, C_VREG, C_NONE, C_VREG, C_NONE, 13, 4, 0, 0},
113 {AXVSLLB, C_U3CON, C_XREG, C_NONE, C_XREG, C_NONE, 13, 4, 0, 0},
114 {AVSLLB, C_U3CON, C_NONE, C_NONE, C_VREG, C_NONE, 13, 4, 0, 0},
115 {AXVSLLB, C_U3CON, C_NONE, C_NONE, C_XREG, C_NONE, 13, 4, 0, 0},
116
117 {AVSLLH, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
118 {AVSLLH, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
119 {AXVSLLH, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
120 {AXVSLLH, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
121 {AVSLLH, C_U4CON, C_VREG, C_NONE, C_VREG, C_NONE, 14, 4, 0, 0},
122 {AXVSLLH, C_U4CON, C_XREG, C_NONE, C_XREG, C_NONE, 14, 4, 0, 0},
123 {AVSLLH, C_U4CON, C_NONE, C_NONE, C_VREG, C_NONE, 14, 4, 0, 0},
124 {AXVSLLH, C_U4CON, C_NONE, C_NONE, C_XREG, C_NONE, 14, 4, 0, 0},
125
126 {AVSLLW, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
127 {AVSLLW, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
128 {AXVSLLW, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
129 {AXVSLLW, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
130 {AVSLLW, C_U5CON, C_VREG, C_NONE, C_VREG, C_NONE, 31, 4, 0, 0},
131 {AXVSLLW, C_U5CON, C_XREG, C_NONE, C_XREG, C_NONE, 31, 4, 0, 0},
132 {AVSLLW, C_U5CON, C_NONE, C_NONE, C_VREG, C_NONE, 31, 4, 0, 0},
133 {AXVSLLW, C_U5CON, C_NONE, C_NONE, C_XREG, C_NONE, 31, 4, 0, 0},
134
135 {AVSLLV, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
136 {AVSLLV, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
137 {AXVSLLV, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
138 {AXVSLLV, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
139 {AVSLLV, C_U6CON, C_VREG, C_NONE, C_VREG, C_NONE, 32, 4, 0, 0},
140 {AXVSLLV, C_U6CON, C_XREG, C_NONE, C_XREG, C_NONE, 32, 4, 0, 0},
141 {AVSLLV, C_U6CON, C_NONE, C_NONE, C_VREG, C_NONE, 32, 4, 0, 0},
142 {AXVSLLV, C_U6CON, C_NONE, C_NONE, C_XREG, C_NONE, 32, 4, 0, 0},
143
144 {ACLOW, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 9, 4, 0, 0},
145 {AABSF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0},
146 {AMOVVF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0},
147 {AMOVF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0},
148 {AMOVD, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0},
149 {AVPCNTB, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 9, 4, 0, 0},
150 {AXVPCNTB, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 9, 4, 0, 0},
151 {AVSETEQV, C_VREG, C_NONE, C_NONE, C_FCCREG, C_NONE, 9, 4, 0, 0},
152 {AXVSETEQV, C_XREG, C_NONE, C_NONE, C_FCCREG, C_NONE, 9, 4, 0, 0},
153
154 {AFMADDF, C_FREG, C_FREG, C_NONE, C_FREG, C_NONE, 37, 4, 0, 0},
155 {AFMADDF, C_FREG, C_FREG, C_FREG, C_FREG, C_NONE, 37, 4, 0, 0},
156
157 {AFSEL, C_FCCREG, C_FREG, C_FREG, C_FREG, C_NONE, 33, 4, 0, 0},
158 {AFSEL, C_FCCREG, C_FREG, C_NONE, C_FREG, C_NONE, 33, 4, 0, 0},
159
160 {AMOVW, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
161 {AMOVWU, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
162 {AMOVV, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
163 {AMOVB, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
164 {AMOVBU, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
165 {AMOVW, C_REG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0},
166 {AMOVWU, C_REG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0},
167 {AMOVV, C_REG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0},
168 {AMOVB, C_REG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0},
169 {AMOVBU, C_REG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0},
170 {AVMOVQ, C_VREG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0},
171 {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0},
172 {AVMOVQ, C_VREG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGZERO, 0},
173 {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGZERO, 0},
174 {ASC, C_REG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0},
175 {ASCV, C_REG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0},
176
177 {AMOVW, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0},
178 {AMOVWU, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0},
179 {AMOVV, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0},
180 {AMOVB, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0},
181 {AMOVBU, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0},
182 {AMOVW, C_SOREG, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
183 {AMOVWU, C_SOREG, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
184 {AMOVV, C_SOREG, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
185 {AMOVB, C_SOREG, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
186 {AMOVBU, C_SOREG, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
187 {AVMOVQ, C_SOREG, C_NONE, C_NONE, C_VREG, C_NONE, 8, 4, REGZERO, 0},
188 {AXVMOVQ, C_SOREG, C_NONE, C_NONE, C_XREG, C_NONE, 8, 4, REGZERO, 0},
189 {AVMOVQ, C_SAUTO, C_NONE, C_NONE, C_VREG, C_NONE, 8, 4, REGZERO, 0},
190 {AXVMOVQ, C_SAUTO, C_NONE, C_NONE, C_XREG, C_NONE, 8, 4, REGZERO, 0},
191 {ALL, C_SOREG, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
192 {ALLV, C_SOREG, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
193
194 {AMOVW, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0},
195 {AMOVWU, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0},
196 {AMOVV, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0},
197 {AMOVB, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0},
198 {AMOVBU, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0},
199 {AMOVW, C_REG, C_NONE, C_NONE, C_LOREG, C_NONE, 35, 12, REGZERO, 0},
200 {AMOVWU, C_REG, C_NONE, C_NONE, C_LOREG, C_NONE, 35, 12, REGZERO, 0},
201 {AMOVV, C_REG, C_NONE, C_NONE, C_LOREG, C_NONE, 35, 12, REGZERO, 0},
202 {AMOVB, C_REG, C_NONE, C_NONE, C_LOREG, C_NONE, 35, 12, REGZERO, 0},
203 {AMOVBU, C_REG, C_NONE, C_NONE, C_LOREG, C_NONE, 35, 12, REGZERO, 0},
204 {ASC, C_REG, C_NONE, C_NONE, C_LOREG, C_NONE, 35, 12, REGZERO, 0},
205 {AMOVW, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
206 {AMOVWU, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
207 {AMOVV, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
208 {AMOVB, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
209 {AMOVBU, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
210 {AMOVW, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0},
211 {AMOVWU, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0},
212 {AMOVV, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0},
213 {AMOVB, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0},
214 {AMOVBU, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0},
215
216 {AMOVW, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0},
217 {AMOVWU, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0},
218 {AMOVV, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0},
219 {AMOVB, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0},
220 {AMOVBU, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0},
221 {AMOVW, C_LOREG, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0},
222 {AMOVWU, C_LOREG, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0},
223 {AMOVV, C_LOREG, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0},
224 {AMOVB, C_LOREG, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0},
225 {AMOVBU, C_LOREG, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0},
226 {AMOVW, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0},
227 {AMOVWU, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0},
228 {AMOVV, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0},
229 {AMOVB, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0},
230 {AMOVBU, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0},
231 {AMOVW, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0},
232 {AMOVWU, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0},
233 {AMOVV, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0},
234 {AMOVB, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0},
235 {AMOVBU, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0},
236
237 {AMOVW, C_SACON, C_NONE, C_NONE, C_REG, C_NONE, 3, 4, REGSP, 0},
238 {AMOVV, C_SACON, C_NONE, C_NONE, C_REG, C_NONE, 3, 4, REGSP, 0},
239 {AMOVW, C_EXTADDR, C_NONE, C_NONE, C_REG, C_NONE, 52, 8, 0, NOTUSETMP},
240 {AMOVV, C_EXTADDR, C_NONE, C_NONE, C_REG, C_NONE, 52, 8, 0, NOTUSETMP},
241
242 {AMOVW, C_LACON, C_NONE, C_NONE, C_REG, C_NONE, 27, 12, REGSP, 0},
243 {AMOVV, C_LACON, C_NONE, C_NONE, C_REG, C_NONE, 27, 12, REGSP, 0},
244 {AMOVW, C_12CON, C_NONE, C_NONE, C_REG, C_NONE, 3, 4, REGZERO, 0},
245 {AMOVV, C_12CON, C_NONE, C_NONE, C_REG, C_NONE, 3, 4, REGZERO, 0},
246
247 {AMOVW, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 25, 4, 0, 0},
248 {AMOVV, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 25, 4, 0, 0},
249 {AMOVW, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 19, 8, 0, NOTUSETMP},
250 {AMOVV, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 19, 8, 0, NOTUSETMP},
251 {AMOVV, C_DCON12_0, C_NONE, C_NONE, C_REG, C_NONE, 67, 4, 0, NOTUSETMP},
252 {AMOVV, C_DCON12_20S, C_NONE, C_NONE, C_REG, C_NONE, 68, 8, 0, NOTUSETMP},
253 {AMOVV, C_DCON32_12S, C_NONE, C_NONE, C_REG, C_NONE, 69, 12, 0, NOTUSETMP},
254 {AMOVV, C_DCON, C_NONE, C_NONE, C_REG, C_NONE, 59, 16, 0, NOTUSETMP},
255
256 {AADD, C_US12CON, C_REG, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
257 {AADD, C_US12CON, C_NONE, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
258 {AADD, C_U12CON, C_REG, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
259 {AADD, C_U12CON, C_NONE, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
260
261 {AADDV, C_US12CON, C_REG, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
262 {AADDV, C_US12CON, C_NONE, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
263 {AADDV, C_U12CON, C_REG, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
264 {AADDV, C_U12CON, C_NONE, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
265
266 {AAND, C_UU12CON, C_REG, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
267 {AAND, C_UU12CON, C_NONE, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
268 {AAND, C_S12CON, C_REG, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
269 {AAND, C_S12CON, C_NONE, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
270
271 {AADD, C_32CON20_0, C_REG, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
272 {AADD, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
273 {AADDV, C_32CON20_0, C_REG, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
274 {AADDV, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
275 {AAND, C_32CON20_0, C_REG, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
276 {AAND, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
277
278 {AADD, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
279 {AADDV, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
280 {AAND, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
281 {AADD, C_32CON, C_REG, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
282 {AADDV, C_32CON, C_REG, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
283 {AAND, C_32CON, C_REG, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
284
285 {AADDV, C_DCON, C_NONE, C_NONE, C_REG, C_NONE, 60, 20, 0, 0},
286 {AADDV, C_DCON, C_REG, C_NONE, C_REG, C_NONE, 60, 20, 0, 0},
287 {AAND, C_DCON, C_NONE, C_NONE, C_REG, C_NONE, 60, 20, 0, 0},
288 {AAND, C_DCON, C_REG, C_NONE, C_REG, C_NONE, 60, 20, 0, 0},
289 {AADDV, C_DCON12_0, C_NONE, C_NONE, C_REG, C_NONE, 70, 8, 0, 0},
290 {AADDV, C_DCON12_0, C_REG, C_NONE, C_REG, C_NONE, 70, 8, 0, 0},
291 {AAND, C_DCON12_0, C_NONE, C_NONE, C_REG, C_NONE, 70, 8, 0, 0},
292 {AAND, C_DCON12_0, C_REG, C_NONE, C_REG, C_NONE, 70, 8, 0, 0},
293 {AADDV, C_DCON12_20S, C_NONE, C_NONE, C_REG, C_NONE, 71, 12, 0, 0},
294 {AADDV, C_DCON12_20S, C_REG, C_NONE, C_REG, C_NONE, 71, 12, 0, 0},
295 {AAND, C_DCON12_20S, C_NONE, C_NONE, C_REG, C_NONE, 71, 12, 0, 0},
296 {AAND, C_DCON12_20S, C_REG, C_NONE, C_REG, C_NONE, 71, 12, 0, 0},
297 {AADDV, C_DCON32_12S, C_NONE, C_NONE, C_REG, C_NONE, 72, 16, 0, 0},
298 {AADDV, C_DCON32_12S, C_REG, C_NONE, C_REG, C_NONE, 72, 16, 0, 0},
299 {AAND, C_DCON32_12S, C_NONE, C_NONE, C_REG, C_NONE, 72, 16, 0, 0},
300 {AAND, C_DCON32_12S, C_REG, C_NONE, C_REG, C_NONE, 72, 16, 0, 0},
301
302 {ASLL, C_U5CON, C_REG, C_NONE, C_REG, C_NONE, 16, 4, 0, 0},
303 {ASLL, C_U5CON, C_NONE, C_NONE, C_REG, C_NONE, 16, 4, 0, 0},
304
305 {ASLLV, C_U6CON, C_REG, C_NONE, C_REG, C_NONE, 16, 4, 0, 0},
306 {ASLLV, C_U6CON, C_NONE, C_NONE, C_REG, C_NONE, 16, 4, 0, 0},
307
308 {ABSTRPICKW, C_U6CON, C_REG, C_U6CON, C_REG, C_NONE, 17, 4, 0, 0},
309 {ABSTRPICKW, C_U6CON, C_REG, C_ZCON, C_REG, C_NONE, 17, 4, 0, 0},
310 {ABSTRPICKW, C_ZCON, C_REG, C_ZCON, C_REG, C_NONE, 17, 4, 0, 0},
311
312 {ASYSCALL, C_NONE, C_NONE, C_NONE, C_NONE, C_NONE, 5, 4, 0, 0},
313 {ASYSCALL, C_U15CON, C_NONE, C_NONE, C_NONE, C_NONE, 5, 4, 0, 0},
314
315 {ABEQ, C_REG, C_REG, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0},
316 {ABEQ, C_REG, C_NONE, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0},
317 {ABLEZ, C_REG, C_NONE, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0},
318 {ABFPT, C_NONE, C_NONE, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0},
319 {ABFPT, C_FCCREG, C_NONE, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0},
320
321 {AJMP, C_NONE, C_NONE, C_NONE, C_BRAN, C_NONE, 11, 4, 0, 0},
322 {AJAL, C_NONE, C_NONE, C_NONE, C_BRAN, C_NONE, 11, 4, 0, 0},
323
324 {AJMP, C_NONE, C_NONE, C_NONE, C_ZOREG, C_NONE, 18, 4, REGZERO, 0},
325 {AJAL, C_NONE, C_NONE, C_NONE, C_ZOREG, C_NONE, 18, 4, REGLINK, 0},
326
327 {AMOVF, C_SAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 28, 4, REGSP, 0},
328 {AMOVD, C_SAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 28, 4, REGSP, 0},
329 {AMOVF, C_SOREG, C_NONE, C_NONE, C_FREG, C_NONE, 28, 4, REGZERO, 0},
330 {AMOVD, C_SOREG, C_NONE, C_NONE, C_FREG, C_NONE, 28, 4, REGZERO, 0},
331
332 {AMOVF, C_LAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 28, 12, REGSP, 0},
333 {AMOVD, C_LAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 28, 12, REGSP, 0},
334 {AMOVF, C_LOREG, C_NONE, C_NONE, C_FREG, C_NONE, 28, 12, REGZERO, 0},
335 {AMOVD, C_LOREG, C_NONE, C_NONE, C_FREG, C_NONE, 28, 12, REGZERO, 0},
336 {AMOVF, C_ADDR, C_NONE, C_NONE, C_FREG, C_NONE, 51, 8, 0, 0},
337 {AMOVD, C_ADDR, C_NONE, C_NONE, C_FREG, C_NONE, 51, 8, 0, 0},
338
339 {AMOVF, C_FREG, C_NONE, C_NONE, C_SAUTO, C_NONE, 29, 4, REGSP, 0},
340 {AMOVD, C_FREG, C_NONE, C_NONE, C_SAUTO, C_NONE, 29, 4, REGSP, 0},
341 {AMOVF, C_FREG, C_NONE, C_NONE, C_SOREG, C_NONE, 29, 4, REGZERO, 0},
342 {AMOVD, C_FREG, C_NONE, C_NONE, C_SOREG, C_NONE, 29, 4, REGZERO, 0},
343
344 {AMOVF, C_FREG, C_NONE, C_NONE, C_LAUTO, C_NONE, 29, 12, REGSP, 0},
345 {AMOVD, C_FREG, C_NONE, C_NONE, C_LAUTO, C_NONE, 29, 12, REGSP, 0},
346 {AMOVF, C_FREG, C_NONE, C_NONE, C_LOREG, C_NONE, 29, 12, REGZERO, 0},
347 {AMOVD, C_FREG, C_NONE, C_NONE, C_LOREG, C_NONE, 29, 12, REGZERO, 0},
348 {AMOVF, C_FREG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
349 {AMOVD, C_FREG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
350
351 {AMOVW, C_REG, C_NONE, C_NONE, C_FREG, C_NONE, 30, 4, 0, 0},
352 {AMOVV, C_REG, C_NONE, C_NONE, C_FREG, C_NONE, 30, 4, 0, 0},
353 {AMOVW, C_FREG, C_NONE, C_NONE, C_REG, C_NONE, 30, 4, 0, 0},
354 {AMOVV, C_FREG, C_NONE, C_NONE, C_REG, C_NONE, 30, 4, 0, 0},
355 {AMOVV, C_FCCREG, C_NONE, C_NONE, C_REG, C_NONE, 30, 4, 0, 0},
356 {AMOVV, C_FCSRREG, C_NONE, C_NONE, C_REG, C_NONE, 30, 4, 0, 0},
357 {AMOVV, C_REG, C_NONE, C_NONE, C_FCCREG, C_NONE, 30, 4, 0, 0},
358 {AMOVV, C_REG, C_NONE, C_NONE, C_FCSRREG, C_NONE, 30, 4, 0, 0},
359 {AMOVV, C_FREG, C_NONE, C_NONE, C_FCCREG, C_NONE, 30, 4, 0, 0},
360 {AMOVV, C_FCCREG, C_NONE, C_NONE, C_FREG, C_NONE, 30, 4, 0, 0},
361
362 {AMOVW, C_12CON, C_NONE, C_NONE, C_FREG, C_NONE, 34, 8, 0, 0},
363
364 {AMOVB, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0},
365 {AMOVW, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0},
366 {AMOVV, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0},
367 {AMOVBU, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0},
368 {AMOVWU, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0},
369
370 {AMOVB, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0},
371 {AMOVW, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0},
372 {AMOVV, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0},
373 {AMOVBU, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0},
374 {AMOVWU, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0},
375
376 {AWORD, C_32CON, C_NONE, C_NONE, C_NONE, C_NONE, 38, 4, 0, 0},
377 {AWORD, C_DCON, C_NONE, C_NONE, C_NONE, C_NONE, 61, 4, 0, 0},
378
379 {AMOVV, C_GOTADDR, C_NONE, C_NONE, C_REG, C_NONE, 65, 8, 0, 0},
380
381 {ATEQ, C_US12CON, C_REG, C_NONE, C_REG, C_NONE, 15, 8, 0, 0},
382 {ATEQ, C_US12CON, C_NONE, C_NONE, C_REG, C_NONE, 15, 8, 0, 0},
383
384 {ARDTIMELW, C_NONE, C_NONE, C_NONE, C_REG, C_REG, 62, 4, 0, 0},
385 {AAMSWAPW, C_REG, C_NONE, C_NONE, C_ZOREG, C_REG, 66, 4, 0, 0},
386 {ANOOP, C_NONE, C_NONE, C_NONE, C_NONE, C_NONE, 49, 4, 0, 0},
387
388
389 {AMOVB, C_REG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
390 {AMOVW, C_REG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
391 {AMOVV, C_REG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
392 {AMOVF, C_FREG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
393 {AMOVD, C_FREG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
394 {AVMOVQ, C_VREG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
395 {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
396
397
398 {AMOVB, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0},
399 {AMOVBU, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0},
400 {AMOVW, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0},
401 {AMOVWU, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0},
402 {AMOVV, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0},
403 {AMOVF, C_ROFF, C_NONE, C_NONE, C_FREG, C_NONE, 21, 4, 0, 0},
404 {AMOVD, C_ROFF, C_NONE, C_NONE, C_FREG, C_NONE, 21, 4, 0, 0},
405 {AVMOVQ, C_ROFF, C_NONE, C_NONE, C_VREG, C_NONE, 21, 4, 0, 0},
406 {AXVMOVQ, C_ROFF, C_NONE, C_NONE, C_XREG, C_NONE, 21, 4, 0, 0},
407
408 {AVMOVQ, C_REG, C_NONE, C_NONE, C_ELEM, C_NONE, 39, 4, 0, 0},
409 {AVMOVQ, C_ELEM, C_NONE, C_NONE, C_REG, C_NONE, 40, 4, 0, 0},
410 {AXVMOVQ, C_REG, C_NONE, C_NONE, C_ELEM, C_NONE, 39, 4, 0, 0},
411 {AXVMOVQ, C_ELEM, C_NONE, C_NONE, C_REG, C_NONE, 40, 4, 0, 0},
412
413 {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_ELEM, C_NONE, 43, 4, 0, 0},
414 {AXVMOVQ, C_ELEM, C_NONE, C_NONE, C_XREG, C_NONE, 44, 4, 0, 0},
415
416 {AVMOVQ, C_REG, C_NONE, C_NONE, C_ARNG, C_NONE, 41, 4, 0, 0},
417 {AXVMOVQ, C_REG, C_NONE, C_NONE, C_ARNG, C_NONE, 41, 4, 0, 0},
418 {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_ARNG, C_NONE, 42, 4, 0, 0},
419
420 {AVMOVQ, C_ELEM, C_NONE, C_NONE, C_ARNG, C_NONE, 45, 4, 0, 0},
421
422 {AVMOVQ, C_SOREG, C_NONE, C_NONE, C_ARNG, C_NONE, 46, 4, 0, 0},
423 {AXVMOVQ, C_SOREG, C_NONE, C_NONE, C_ARNG, C_NONE, 46, 4, 0, 0},
424
425 {APRELD, C_SOREG, C_U5CON, C_NONE, C_NONE, C_NONE, 47, 4, 0, 0},
426 {APRELDX, C_SOREG, C_DCON, C_U5CON, C_NONE, C_NONE, 48, 20, 0, 0},
427
428 {AALSLV, C_U3CON, C_REG, C_REG, C_REG, C_NONE, 64, 4, 0, 0},
429
430 {obj.APCALIGN, C_U12CON, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
431 {obj.APCDATA, C_32CON, C_NONE, C_NONE, C_32CON, C_NONE, 0, 0, 0, 0},
432 {obj.APCDATA, C_DCON, C_NONE, C_NONE, C_DCON, C_NONE, 0, 0, 0, 0},
433 {obj.AFUNCDATA, C_U12CON, C_NONE, C_NONE, C_ADDR, C_NONE, 0, 0, 0, 0},
434 {obj.ANOP, C_NONE, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
435 {obj.ANOP, C_32CON, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
436 {obj.ANOP, C_DCON, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
437 {obj.ANOP, C_REG, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
438 {obj.ANOP, C_FREG, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
439 {obj.ADUFFZERO, C_NONE, C_NONE, C_NONE, C_BRAN, C_NONE, 11, 4, 0, 0},
440 {obj.ADUFFCOPY, C_NONE, C_NONE, C_NONE, C_BRAN, C_NONE, 11, 4, 0, 0},
441
442 {obj.AXXX, C_NONE, C_NONE, C_NONE, C_NONE, C_NONE, 0, 4, 0, 0},
443 }
444
445 var atomicInst = map[obj.As]uint32{
446 AAMSWAPB: 0x070B8 << 15,
447 AAMSWAPH: 0x070B9 << 15,
448 AAMSWAPW: 0x070C0 << 15,
449 AAMSWAPV: 0x070C1 << 15,
450 AAMCASB: 0x070B0 << 15,
451 AAMCASH: 0x070B1 << 15,
452 AAMCASW: 0x070B2 << 15,
453 AAMCASV: 0x070B3 << 15,
454 AAMADDW: 0x070C2 << 15,
455 AAMADDV: 0x070C3 << 15,
456 AAMANDW: 0x070C4 << 15,
457 AAMANDV: 0x070C5 << 15,
458 AAMORW: 0x070C6 << 15,
459 AAMORV: 0x070C7 << 15,
460 AAMXORW: 0x070C8 << 15,
461 AAMXORV: 0x070C9 << 15,
462 AAMMAXW: 0x070CA << 15,
463 AAMMAXV: 0x070CB << 15,
464 AAMMINW: 0x070CC << 15,
465 AAMMINV: 0x070CD << 15,
466 AAMMAXWU: 0x070CE << 15,
467 AAMMAXVU: 0x070CF << 15,
468 AAMMINWU: 0x070D0 << 15,
469 AAMMINVU: 0x070D1 << 15,
470 AAMSWAPDBB: 0x070BC << 15,
471 AAMSWAPDBH: 0x070BD << 15,
472 AAMSWAPDBW: 0x070D2 << 15,
473 AAMSWAPDBV: 0x070D3 << 15,
474 AAMCASDBB: 0x070B4 << 15,
475 AAMCASDBH: 0x070B5 << 15,
476 AAMCASDBW: 0x070B6 << 15,
477 AAMCASDBV: 0x070B7 << 15,
478 AAMADDDBW: 0x070D4 << 15,
479 AAMADDDBV: 0x070D5 << 15,
480 AAMANDDBW: 0x070D6 << 15,
481 AAMANDDBV: 0x070D7 << 15,
482 AAMORDBW: 0x070D8 << 15,
483 AAMORDBV: 0x070D9 << 15,
484 AAMXORDBW: 0x070DA << 15,
485 AAMXORDBV: 0x070DB << 15,
486 AAMMAXDBW: 0x070DC << 15,
487 AAMMAXDBV: 0x070DD << 15,
488 AAMMINDBW: 0x070DE << 15,
489 AAMMINDBV: 0x070DF << 15,
490 AAMMAXDBWU: 0x070E0 << 15,
491 AAMMAXDBVU: 0x070E1 << 15,
492 AAMMINDBWU: 0x070E2 << 15,
493 AAMMINDBVU: 0x070E3 << 15,
494 }
495
496 func IsAtomicInst(as obj.As) bool {
497 _, ok := atomicInst[as]
498
499 return ok
500 }
501
502
503
504 func pcAlignPadLength(ctxt *obj.Link, pc int64, alignedValue int64) int {
505 if !((alignedValue&(alignedValue-1) == 0) && 8 <= alignedValue && alignedValue <= 2048) {
506 ctxt.Diag("alignment value of an instruction must be a power of two and in the range [8, 2048], got %d\n", alignedValue)
507 }
508 return int(-pc & (alignedValue - 1))
509 }
510
511 var oprange [ALAST & obj.AMask][]Optab
512
513 var xcmp [C_NCLASS][C_NCLASS]bool
514
515 func span0(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) {
516 if ctxt.Retpoline {
517 ctxt.Diag("-spectre=ret not supported on loong64")
518 ctxt.Retpoline = false
519 }
520
521 p := cursym.Func().Text
522 if p == nil || p.Link == nil {
523 return
524 }
525
526 c := ctxt0{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset + ctxt.Arch.FixedFrameSize)}
527
528 if oprange[AOR&obj.AMask] == nil {
529 c.ctxt.Diag("loong64 ops not initialized, call loong64.buildop first")
530 }
531
532 pc := int64(0)
533 p.Pc = pc
534
535 var m int
536 var o *Optab
537 for p = p.Link; p != nil; p = p.Link {
538 p.Pc = pc
539 o = c.oplook(p)
540 m = int(o.size)
541 if m == 0 {
542 switch p.As {
543 case obj.APCALIGN:
544 alignedValue := p.From.Offset
545 m = pcAlignPadLength(ctxt, pc, alignedValue)
546
547 if int32(alignedValue) > cursym.Func().Align {
548 cursym.Func().Align = int32(alignedValue)
549 }
550 break
551 case obj.ANOP, obj.AFUNCDATA, obj.APCDATA:
552 continue
553 default:
554 c.ctxt.Diag("zero-width instruction\n%v", p)
555 }
556 }
557
558 pc += int64(m)
559 }
560
561 c.cursym.Size = pc
562
563
564
565 for p = c.cursym.Func().Text.Link; p != nil; p = p.Link {
566 if q := p.To.Target(); q != nil && q.Pc < p.Pc {
567 q.Mark |= branchLoopHead
568 }
569 }
570
571
572 for {
573 rescan := false
574 pc = 0
575 prev := c.cursym.Func().Text
576 for p = prev.Link; p != nil; prev, p = p, p.Link {
577 p.Pc = pc
578 o = c.oplook(p)
579
580
581
582
583
584
585
586 if p.Mark&branchLoopHead != 0 && pc&(loopAlign-1) != 0 &&
587 !(prev.As == obj.APCALIGN && prev.From.Offset >= loopAlign) {
588 q := c.newprog()
589 prev.Link = q
590 q.Link = p
591 q.Pc = pc
592 q.As = obj.APCALIGN
593 q.From.Type = obj.TYPE_CONST
594 q.From.Offset = loopAlign
595
596
597
598
599
600
601
602 pc += int64(pcAlignPadLength(ctxt, pc, loopAlign))
603 p.Pc = pc
604 rescan = true
605 }
606
607
608
609
610
611 if o.type_ == 6 && p.To.Target() != nil {
612 otxt := p.To.Target().Pc - pc
613
614
615
616
617
618 bound := int64(1 << (18 - 1))
619
620 switch p.As {
621 case ABFPT, ABFPF:
622 bound = int64(1 << (23 - 1))
623 }
624
625 if otxt < -bound || otxt >= bound {
626 q := c.newprog()
627 q.Link = p.Link
628 p.Link = q
629 q.As = AJMP
630 q.Pos = p.Pos
631 q.To.Type = obj.TYPE_BRANCH
632 q.To.SetTarget(p.To.Target())
633 p.To.SetTarget(q)
634 q = c.newprog()
635 q.Link = p.Link
636 p.Link = q
637 q.As = AJMP
638 q.Pos = p.Pos
639 q.To.Type = obj.TYPE_BRANCH
640 q.To.SetTarget(q.Link.Link)
641 rescan = true
642 }
643 }
644
645 m = int(o.size)
646 if m == 0 {
647 switch p.As {
648 case obj.APCALIGN:
649 alignedValue := p.From.Offset
650 m = pcAlignPadLength(ctxt, pc, alignedValue)
651 break
652 case obj.ANOP, obj.AFUNCDATA, obj.APCDATA:
653 continue
654 default:
655 c.ctxt.Diag("zero-width instruction\n%v", p)
656 }
657 }
658
659 pc += int64(m)
660 }
661
662 c.cursym.Size = pc
663
664 if !rescan {
665 break
666 }
667 }
668
669 pc += -pc & (FuncAlign - 1)
670 c.cursym.Size = pc
671
672
673
674 c.cursym.Grow(c.cursym.Size)
675
676 bp := c.cursym.P
677 var i int32
678 var out [5]uint32
679 for p := c.cursym.Func().Text.Link; p != nil; p = p.Link {
680 c.pc = p.Pc
681 o = c.oplook(p)
682 if int(o.size) > 4*len(out) {
683 log.Fatalf("out array in span0 is too small, need at least %d for %v", o.size/4, p)
684 }
685 if p.As == obj.APCALIGN {
686 alignedValue := p.From.Offset
687 v := pcAlignPadLength(c.ctxt, p.Pc, alignedValue)
688 for i = 0; i < int32(v/4); i++ {
689
690 c.ctxt.Arch.ByteOrder.PutUint32(bp, OP_12IRR(c.opirr(AAND), 0, 0, 0))
691 bp = bp[4:]
692 }
693 continue
694 }
695 c.asmout(p, o, out[:])
696 for i = 0; i < int32(o.size/4); i++ {
697 c.ctxt.Arch.ByteOrder.PutUint32(bp, out[i])
698 bp = bp[4:]
699 }
700 }
701
702
703
704
705
706 obj.MarkUnsafePoints(c.ctxt, c.cursym.Func().Text, c.newprog, c.isUnsafePoint, c.isRestartable)
707 }
708
709
710 func (c *ctxt0) isUnsafePoint(p *obj.Prog) bool {
711
712
713 return p.From.Reg == REGTMP || p.To.Reg == REGTMP || p.Reg == REGTMP
714 }
715
716
717
718 func (c *ctxt0) isRestartable(p *obj.Prog) bool {
719 if c.isUnsafePoint(p) {
720 return false
721 }
722
723
724
725
726
727
728
729 o := c.oplook(p)
730 return o.size > 4 && o.flag&NOTUSETMP == 0
731 }
732
733 func isint32(v int64) bool {
734 return int64(int32(v)) == v
735 }
736
737 func (c *ctxt0) aclass(a *obj.Addr) int {
738 switch a.Type {
739 case obj.TYPE_NONE:
740 return C_NONE
741
742 case obj.TYPE_REG:
743 return c.rclass(a.Reg)
744
745 case obj.TYPE_MEM:
746 switch a.Name {
747 case obj.NAME_EXTERN,
748 obj.NAME_STATIC:
749 if a.Sym == nil {
750 break
751 }
752 c.instoffset = a.Offset
753 if a.Sym.Type == objabi.STLSBSS {
754 if c.ctxt.Flag_shared {
755 return C_TLS_IE
756 } else {
757 return C_TLS_LE
758 }
759 }
760 return C_ADDR
761
762 case obj.NAME_AUTO:
763 if a.Reg == REGSP {
764
765
766 a.Reg = obj.REG_NONE
767 }
768 c.instoffset = int64(c.autosize) + a.Offset
769 if c.instoffset >= -BIG && c.instoffset < BIG {
770 return C_SAUTO
771 }
772 return C_LAUTO
773
774 case obj.NAME_PARAM:
775 if a.Reg == REGSP {
776
777
778 a.Reg = obj.REG_NONE
779 }
780 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize
781 if c.instoffset >= -BIG && c.instoffset < BIG {
782 return C_SAUTO
783 }
784 return C_LAUTO
785
786 case obj.NAME_NONE:
787 if a.Index != 0 {
788 if a.Offset != 0 {
789 return C_GOK
790 }
791
792 return C_ROFF
793 }
794
795 c.instoffset = a.Offset
796 if c.instoffset == 0 {
797 return C_ZOREG
798 }
799 if c.instoffset >= -BIG && c.instoffset < BIG {
800 return C_SOREG
801 }
802 return C_LOREG
803
804 case obj.NAME_GOTREF:
805 return C_GOTADDR
806 }
807
808 return C_GOK
809
810 case obj.TYPE_TEXTSIZE:
811 return C_TEXTSIZE
812
813 case obj.TYPE_CONST,
814 obj.TYPE_ADDR:
815 switch a.Name {
816 case obj.NAME_NONE:
817 c.instoffset = a.Offset
818 if a.Reg != 0 {
819 if -BIG <= c.instoffset && c.instoffset <= BIG {
820 return C_SACON
821 }
822 if isint32(c.instoffset) {
823 return C_LACON
824 }
825 return C_DACON
826 }
827
828 case obj.NAME_EXTERN,
829 obj.NAME_STATIC:
830 s := a.Sym
831 if s == nil {
832 return C_GOK
833 }
834
835 c.instoffset = a.Offset
836 if s.Type == objabi.STLSBSS {
837 c.ctxt.Diag("taking address of TLS variable is not supported")
838 }
839 return C_EXTADDR
840
841 case obj.NAME_AUTO:
842 if a.Reg == REGSP {
843
844
845 a.Reg = obj.REG_NONE
846 }
847 c.instoffset = int64(c.autosize) + a.Offset
848 if c.instoffset >= -BIG && c.instoffset < BIG {
849 return C_SACON
850 }
851 return C_LACON
852
853 case obj.NAME_PARAM:
854 if a.Reg == REGSP {
855
856
857 a.Reg = obj.REG_NONE
858 }
859 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize
860 if c.instoffset >= -BIG && c.instoffset < BIG {
861 return C_SACON
862 }
863 return C_LACON
864
865 default:
866 return C_GOK
867 }
868
869 if c.instoffset != int64(int32(c.instoffset)) {
870 return dconClass(c.instoffset)
871 }
872
873 if c.instoffset >= 0 {
874 sbits := bits.Len64(uint64(c.instoffset))
875 switch {
876 case sbits <= 8:
877 return C_ZCON + sbits
878 case sbits <= 12:
879 if c.instoffset <= 0x7ff {
880 return C_US12CON
881 }
882 return C_U12CON
883 case sbits <= 13:
884 if c.instoffset&0xfff == 0 {
885 return C_U13CON20_0
886 }
887 return C_U13CON
888 case sbits <= 15:
889 if c.instoffset&0xfff == 0 {
890 return C_U15CON20_0
891 }
892 return C_U15CON
893 }
894 } else {
895 sbits := bits.Len64(uint64(^c.instoffset))
896 switch {
897 case sbits < 5:
898 return C_S5CON
899 case sbits < 12:
900 return C_S12CON
901 case sbits < 13:
902 if c.instoffset&0xfff == 0 {
903 return C_S13CON20_0
904 }
905 return C_S13CON
906 }
907 }
908
909 if c.instoffset&0xfff == 0 {
910 return C_32CON20_0
911 }
912 return C_32CON
913
914 case obj.TYPE_BRANCH:
915 return C_BRAN
916 }
917
918 return C_GOK
919 }
920
921
922
923
924
925
926
927 const (
928 ALL1 = iota
929 ALL0
930 ST1
931 ST0
932 )
933
934
935
936 func mask(suf int8, len int8) (uint64, uint64) {
937 if len == 12 {
938 if suf == 0 {
939 return 0xfff, 0x800
940 } else {
941 return 0xfff0000000000000, 0x8000000000000000
942 }
943 } else {
944 if suf == 12 {
945 return 0xfffff000, 0x80000000
946 } else {
947 return 0xfffff00000000, 0x8000000000000
948 }
949 }
950 }
951
952
953
954
955
956 func bitField(val int64, suf int8, len int8) int8 {
957 mask1, mask2 := mask(suf, len)
958 if uint64(val)&mask1 == mask1 {
959 return ALL1
960 } else if uint64(val)&mask1 == 0x0 {
961 return ALL0
962 } else if uint64(val)&mask2 == mask2 {
963 return ST1
964 } else {
965 return ST0
966 }
967 }
968
969
970
971
972
973
974
975
976
977 func dconClass(offset int64) int {
978 tzb := bits.TrailingZeros64(uint64(offset))
979 hi12 := bitField(offset, 52, 12)
980 hi20 := bitField(offset, 32, 20)
981 lo20 := bitField(offset, 12, 20)
982 lo12 := bitField(offset, 0, 12)
983 if tzb >= 52 {
984 return C_DCON12_0
985 }
986 if tzb >= 32 {
987 if ((hi20 == ALL1 || hi20 == ST1) && hi12 == ALL1) || ((hi20 == ALL0 || hi20 == ST0) && hi12 == ALL0) {
988 return C_DCON20S_0
989 }
990 return C_DCON32_0
991 }
992 if tzb >= 12 {
993 if lo20 == ST1 || lo20 == ALL1 {
994 if hi20 == ALL1 {
995 return C_DCON12_20S
996 }
997 if (hi20 == ST1 && hi12 == ALL1) || ((hi20 == ST0 || hi20 == ALL0) && hi12 == ALL0) {
998 return C_DCON20S_20
999 }
1000 return C_DCON32_20
1001 }
1002 if hi20 == ALL0 {
1003 return C_DCON12_20S
1004 }
1005 if (hi20 == ST0 && hi12 == ALL0) || ((hi20 == ST1 || hi20 == ALL1) && hi12 == ALL1) {
1006 return C_DCON20S_20
1007 }
1008 return C_DCON32_20
1009 }
1010 if lo12 == ST1 || lo12 == ALL1 {
1011 if lo20 == ALL1 {
1012 if hi20 == ALL1 {
1013 return C_DCON12_12S
1014 }
1015 if (hi20 == ST1 && hi12 == ALL1) || ((hi20 == ST0 || hi20 == ALL0) && hi12 == ALL0) {
1016 return C_DCON20S_12S
1017 }
1018 return C_DCON32_12S
1019 }
1020 if lo20 == ST1 {
1021 if hi20 == ALL1 {
1022
1023 return C_DCON12_32S
1024 }
1025 if (hi20 == ST1 && hi12 == ALL1) || ((hi20 == ST0 || hi20 == ALL0) && hi12 == ALL0) {
1026 return C_DCON20S_32
1027 }
1028 return C_DCON
1029 }
1030 if lo20 == ALL0 {
1031 if hi20 == ALL0 {
1032 return C_DCON12_12U
1033 }
1034 if ((hi20 == ST1 || hi20 == ALL1) && hi12 == ALL1) || (hi20 == ST0 && hi12 == ALL0) {
1035 return C_DCON20S_12U
1036 }
1037 return C_DCON32_12U
1038 }
1039 if hi20 == ALL0 {
1040 return C_DCON12_32S
1041 }
1042 if ((hi20 == ST1 || hi20 == ALL1) && hi12 == ALL1) || (hi20 == ST0 && hi12 == ALL0) {
1043 return C_DCON20S_32
1044 }
1045 return C_DCON
1046 }
1047 if lo20 == ALL0 {
1048 if hi20 == ALL0 {
1049 return C_DCON12_12U
1050 }
1051 if ((hi20 == ST1 || hi20 == ALL1) && hi12 == ALL1) || (hi20 == ST0 && hi12 == ALL0) {
1052 return C_DCON20S_12U
1053 }
1054 return C_DCON32_12U
1055 }
1056 if lo20 == ST1 || lo20 == ALL1 {
1057 if hi20 == ALL1 {
1058 return C_DCON12_32S
1059 }
1060 if (hi20 == ST1 && hi12 == ALL1) || ((hi20 == ST0 || hi20 == ALL0) && hi12 == ALL0) {
1061 return C_DCON20S_32
1062 }
1063 return C_DCON
1064 }
1065 if hi20 == ALL0 {
1066 return C_DCON12_32S
1067 }
1068 if ((hi20 == ST1 || hi20 == ALL1) && hi12 == ALL1) || (hi20 == ST0 && hi12 == ALL0) {
1069 return C_DCON20S_32
1070 }
1071 return C_DCON
1072 }
1073
1074
1075
1076 func (c *ctxt0) rclass(r int16) int {
1077 switch {
1078 case REG_R0 <= r && r <= REG_R31:
1079 return C_REG
1080 case REG_F0 <= r && r <= REG_F31:
1081 return C_FREG
1082 case REG_FCC0 <= r && r <= REG_FCC7:
1083 return C_FCCREG
1084 case REG_FCSR0 <= r && r <= REG_FCSR3:
1085 return C_FCSRREG
1086 case REG_V0 <= r && r <= REG_V31:
1087 return C_VREG
1088 case REG_X0 <= r && r <= REG_X31:
1089 return C_XREG
1090 case r >= REG_ARNG && r < REG_ELEM:
1091 return C_ARNG
1092 case r >= REG_ELEM && r < REG_ELEM_END:
1093 return C_ELEM
1094 }
1095
1096 return C_GOK
1097 }
1098
1099 func oclass(a *obj.Addr) int {
1100 return int(a.Class) - 1
1101 }
1102
1103 func prasm(p *obj.Prog) {
1104 fmt.Printf("%v\n", p)
1105 }
1106
1107 func (c *ctxt0) oplook(p *obj.Prog) *Optab {
1108 if oprange[AOR&obj.AMask] == nil {
1109 c.ctxt.Diag("loong64 ops not initialized, call loong64.buildop first")
1110 }
1111
1112 restArgsIndex := 0
1113 restArgsLen := len(p.RestArgs)
1114 if restArgsLen > 2 {
1115 c.ctxt.Diag("too many RestArgs: got %v, maximum is 2\n", restArgsLen)
1116 return nil
1117 }
1118
1119 restArgsv := [2]int{C_NONE + 1, C_NONE + 1}
1120 for i, ap := range p.RestArgs {
1121 restArgsv[i] = int(ap.Addr.Class)
1122 if restArgsv[i] == 0 {
1123 restArgsv[i] = c.aclass(&ap.Addr) + 1
1124 ap.Addr.Class = int8(restArgsv[i])
1125 }
1126 }
1127
1128 a1 := int(p.Optab)
1129 if a1 != 0 {
1130 return &optab[a1-1]
1131 }
1132
1133
1134 a1 = int(p.From.Class)
1135 if a1 == 0 {
1136 a1 = c.aclass(&p.From) + 1
1137 p.From.Class = int8(a1)
1138 }
1139 a1--
1140
1141
1142 a4 := int(p.To.Class)
1143 if a4 == 0 {
1144 a4 = c.aclass(&p.To) + 1
1145 p.To.Class = int8(a4)
1146 }
1147 a4--
1148
1149
1150 a2 := C_NONE
1151 if p.Reg != 0 {
1152 a2 = c.rclass(p.Reg)
1153 } else if restArgsLen > 0 {
1154 a2 = restArgsv[restArgsIndex] - 1
1155 restArgsIndex++
1156 }
1157
1158
1159 a5 := C_NONE
1160 if p.RegTo2 != 0 {
1161 a5 = C_REG
1162 }
1163
1164
1165 a3 := C_NONE
1166 if restArgsLen > 0 && restArgsIndex < restArgsLen {
1167 a3 = restArgsv[restArgsIndex] - 1
1168 restArgsIndex++
1169 }
1170
1171 ops := oprange[p.As&obj.AMask]
1172 c1 := &xcmp[a1]
1173 c2 := &xcmp[a2]
1174 c3 := &xcmp[a3]
1175 c4 := &xcmp[a4]
1176 c5 := &xcmp[a5]
1177 for i := range ops {
1178 op := &ops[i]
1179 if c1[op.from1] && c2[op.reg] && c3[op.from3] && c4[op.to1] && c5[op.to2] {
1180 p.Optab = uint16(cap(optab) - cap(ops) + i + 1)
1181 return op
1182 }
1183 }
1184
1185 c.ctxt.Diag("illegal combination %v %v %v %v %v %v", p.As, DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4), DRconv(a5))
1186 prasm(p)
1187
1188 return &Optab{obj.AUNDEF, C_NONE, C_NONE, C_NONE, C_NONE, C_NONE, 49, 4, 0, 0}
1189 }
1190
1191 func cmp(a int, b int) bool {
1192 if a == b {
1193 return true
1194 }
1195 switch a {
1196 case C_DCON:
1197 return cmp(C_32CON, b) || cmp(C_DCON12_20S, b) || cmp(C_DCON32_12S, b) || b == C_DCON12_0
1198 case C_32CON:
1199 return cmp(C_32CON20_0, b) || cmp(C_U15CON, b) || cmp(C_13CON, b) || cmp(C_12CON, b)
1200 case C_32CON20_0:
1201 return b == C_U15CON20_0 || b == C_U13CON20_0 || b == C_S13CON20_0 || b == C_ZCON
1202 case C_U15CON:
1203 return cmp(C_U12CON, b) || b == C_U15CON20_0 || b == C_U13CON20_0 || b == C_U13CON
1204 case C_13CON:
1205 return cmp(C_U13CON, b) || cmp(C_S13CON, b)
1206 case C_U13CON:
1207 return cmp(C_12CON, b) || b == C_U13CON20_0
1208 case C_S13CON:
1209 return cmp(C_12CON, b) || b == C_S13CON20_0
1210 case C_12CON:
1211 return cmp(C_U12CON, b) || cmp(C_S12CON, b)
1212 case C_UU12CON:
1213 return cmp(C_U12CON, b)
1214 case C_U12CON:
1215 return cmp(C_U8CON, b) || b == C_US12CON
1216 case C_U8CON:
1217 return cmp(C_U7CON, b)
1218 case C_U7CON:
1219 return cmp(C_U6CON, b)
1220 case C_U6CON:
1221 return cmp(C_U5CON, b)
1222 case C_U5CON:
1223 return cmp(C_U4CON, b)
1224 case C_U4CON:
1225 return cmp(C_U3CON, b)
1226 case C_U3CON:
1227 return cmp(C_U2CON, b)
1228 case C_U2CON:
1229 return cmp(C_U1CON, b)
1230 case C_U1CON:
1231 return cmp(C_ZCON, b)
1232 case C_US12CON:
1233 return cmp(C_S12CON, b)
1234 case C_S12CON:
1235 return cmp(C_S5CON, b) || cmp(C_U8CON, b) || b == C_US12CON
1236 case C_S5CON:
1237 return cmp(C_ZCON, b) || cmp(C_U4CON, b)
1238
1239 case C_DCON12_20S:
1240 if b == C_DCON20S_20 || b == C_DCON12_12S ||
1241 b == C_DCON20S_12S || b == C_DCON12_12U ||
1242 b == C_DCON20S_12U || b == C_DCON20S_0 {
1243 return true
1244 }
1245
1246 case C_DCON32_12S:
1247 if b == C_DCON32_20 || b == C_DCON12_32S ||
1248 b == C_DCON20S_32 || b == C_DCON32_12U ||
1249 b == C_DCON32_0 {
1250 return true
1251 }
1252
1253 case C_LACON:
1254 return b == C_SACON
1255
1256 case C_LAUTO:
1257 return b == C_SAUTO
1258
1259 case C_REG:
1260 return b == C_ZCON
1261
1262 case C_LOREG:
1263 return b == C_ZOREG || b == C_SOREG
1264
1265 case C_SOREG:
1266 return b == C_ZOREG
1267 }
1268
1269 return false
1270 }
1271
1272 func ocmp(p1, p2 Optab) int {
1273 if p1.as != p2.as {
1274 return int(p1.as) - int(p2.as)
1275 }
1276 if p1.from1 != p2.from1 {
1277 return int(p1.from1) - int(p2.from1)
1278 }
1279 if p1.reg != p2.reg {
1280 return int(p1.reg) - int(p2.reg)
1281 }
1282 if p1.to1 != p2.to1 {
1283 return int(p1.to1) - int(p2.to1)
1284 }
1285 return 0
1286 }
1287
1288 func opset(a, b0 obj.As) {
1289 oprange[a&obj.AMask] = oprange[b0]
1290 }
1291
1292 func buildop(ctxt *obj.Link) {
1293 if ctxt.DiagFunc == nil {
1294 ctxt.DiagFunc = func(format string, args ...interface{}) {
1295 log.Printf(format, args...)
1296 }
1297 }
1298
1299 if oprange[AOR&obj.AMask] != nil {
1300
1301
1302
1303 return
1304 }
1305
1306 var n int
1307
1308 for i := 0; i < C_NCLASS; i++ {
1309 for n = 0; n < C_NCLASS; n++ {
1310 if cmp(n, i) {
1311 xcmp[i][n] = true
1312 }
1313 }
1314 }
1315 for n = 0; optab[n].as != obj.AXXX; n++ {
1316 }
1317 slices.SortFunc(optab[:n], ocmp)
1318 for i := 0; i < n; i++ {
1319 r := optab[i].as
1320 r0 := r & obj.AMask
1321 start := i
1322 for optab[i].as == r {
1323 i++
1324 }
1325 oprange[r0] = optab[start:i]
1326 i--
1327
1328 switch r {
1329 default:
1330 ctxt.Diag("unknown op in build: %v", r)
1331 ctxt.DiagFlush()
1332 log.Fatalf("bad code")
1333
1334 case AABSF:
1335 opset(AMOVFD, r0)
1336 opset(AMOVDF, r0)
1337 opset(AMOVWF, r0)
1338 opset(AMOVFW, r0)
1339 opset(AMOVWD, r0)
1340 opset(AMOVDW, r0)
1341 opset(ANEGF, r0)
1342 opset(ANEGD, r0)
1343 opset(AABSD, r0)
1344 opset(ATRUNCDW, r0)
1345 opset(ATRUNCFW, r0)
1346 opset(ASQRTF, r0)
1347 opset(ASQRTD, r0)
1348 opset(AFCLASSF, r0)
1349 opset(AFCLASSD, r0)
1350 opset(AFLOGBF, r0)
1351 opset(AFLOGBD, r0)
1352
1353 case AMOVVF:
1354 opset(AMOVVD, r0)
1355 opset(AMOVFV, r0)
1356 opset(AMOVDV, r0)
1357 opset(ATRUNCDV, r0)
1358 opset(ATRUNCFV, r0)
1359 opset(AFFINTFW, r0)
1360 opset(AFFINTFV, r0)
1361 opset(AFFINTDW, r0)
1362 opset(AFFINTDV, r0)
1363 opset(AFTINTWF, r0)
1364 opset(AFTINTWD, r0)
1365 opset(AFTINTVF, r0)
1366 opset(AFTINTVD, r0)
1367 opset(AFTINTRPWF, r0)
1368 opset(AFTINTRPWD, r0)
1369 opset(AFTINTRPVF, r0)
1370 opset(AFTINTRPVD, r0)
1371 opset(AFTINTRMWF, r0)
1372 opset(AFTINTRMWD, r0)
1373 opset(AFTINTRMVF, r0)
1374 opset(AFTINTRMVD, r0)
1375 opset(AFTINTRZWF, r0)
1376 opset(AFTINTRZWD, r0)
1377 opset(AFTINTRZVF, r0)
1378 opset(AFTINTRZVD, r0)
1379 opset(AFTINTRNEWF, r0)
1380 opset(AFTINTRNEWD, r0)
1381 opset(AFTINTRNEVF, r0)
1382 opset(AFTINTRNEVD, r0)
1383
1384 case AADD:
1385 opset(ASGT, r0)
1386 opset(ASGTU, r0)
1387 opset(AADDU, r0)
1388
1389 case AADDV:
1390 opset(AADDVU, r0)
1391
1392 case AADDF:
1393 opset(ADIVF, r0)
1394 opset(ADIVD, r0)
1395 opset(AMULF, r0)
1396 opset(AMULD, r0)
1397 opset(ASUBF, r0)
1398 opset(ASUBD, r0)
1399 opset(AADDD, r0)
1400 opset(AFMINF, r0)
1401 opset(AFMIND, r0)
1402 opset(AFMAXF, r0)
1403 opset(AFMAXD, r0)
1404 opset(AFCOPYSGF, r0)
1405 opset(AFCOPYSGD, r0)
1406 opset(AFSCALEBF, r0)
1407 opset(AFSCALEBD, r0)
1408 opset(AFMAXAF, r0)
1409 opset(AFMAXAD, r0)
1410 opset(AFMINAF, r0)
1411 opset(AFMINAD, r0)
1412
1413 case AFMADDF:
1414 opset(AFMADDD, r0)
1415 opset(AFMSUBF, r0)
1416 opset(AFMSUBD, r0)
1417 opset(AFNMADDF, r0)
1418 opset(AFNMADDD, r0)
1419 opset(AFNMSUBF, r0)
1420 opset(AFNMSUBD, r0)
1421
1422 case AAND:
1423 opset(AOR, r0)
1424 opset(AXOR, r0)
1425 opset(AORN, r0)
1426 opset(AANDN, r0)
1427
1428 case ABEQ:
1429 opset(ABNE, r0)
1430 opset(ABLT, r0)
1431 opset(ABGE, r0)
1432 opset(ABGEU, r0)
1433 opset(ABLTU, r0)
1434
1435 case ABLEZ:
1436 opset(ABGEZ, r0)
1437 opset(ABLTZ, r0)
1438 opset(ABGTZ, r0)
1439
1440 case AMOVB:
1441 opset(AMOVH, r0)
1442
1443 case AMOVBU:
1444 opset(AMOVHU, r0)
1445
1446 case AMUL:
1447 opset(AMULU, r0)
1448 opset(AMULH, r0)
1449 opset(AMULHU, r0)
1450 opset(AREM, r0)
1451 opset(AREMU, r0)
1452 opset(ADIV, r0)
1453 opset(ADIVU, r0)
1454
1455 case AMULV:
1456 opset(AMULVU, r0)
1457 opset(AMULHV, r0)
1458 opset(AMULHVU, r0)
1459 opset(AREMV, r0)
1460 opset(AREMVU, r0)
1461 opset(ADIVV, r0)
1462 opset(ADIVVU, r0)
1463
1464 case ASLL:
1465 opset(ASRL, r0)
1466 opset(ASRA, r0)
1467 opset(AROTR, r0)
1468
1469 case ASLLV:
1470 opset(ASRAV, r0)
1471 opset(ASRLV, r0)
1472 opset(AROTRV, r0)
1473
1474 case ABSTRPICKW:
1475 opset(ABSTRPICKV, r0)
1476 opset(ABSTRINSW, r0)
1477 opset(ABSTRINSV, r0)
1478
1479 case ASUB:
1480 opset(ASUBU, r0)
1481 opset(ANOR, r0)
1482
1483 case ASUBV:
1484 opset(ASUBVU, r0)
1485
1486 case ASYSCALL:
1487 opset(ADBAR, r0)
1488 opset(ABREAK, r0)
1489
1490 case ACMPEQF:
1491 opset(ACMPGTF, r0)
1492 opset(ACMPGTD, r0)
1493 opset(ACMPGEF, r0)
1494 opset(ACMPGED, r0)
1495 opset(ACMPEQD, r0)
1496
1497 case ABFPT:
1498 opset(ABFPF, r0)
1499
1500 case AALSLV:
1501 opset(AALSLW, r0)
1502 opset(AALSLWU, r0)
1503
1504 case AMOVW,
1505 AMOVD,
1506 AMOVF,
1507 AMOVV,
1508 ARFE,
1509 AJAL,
1510 AJMP,
1511 AMOVWU,
1512 AVMOVQ,
1513 AXVMOVQ,
1514 ALL,
1515 ALLV,
1516 ASC,
1517 ASCV,
1518 ANEGW,
1519 ANEGV,
1520 AWORD,
1521 APRELD,
1522 APRELDX,
1523 AFSEL,
1524 obj.ANOP,
1525 obj.ATEXT,
1526 obj.AFUNCDATA,
1527 obj.APCALIGN,
1528 obj.APCDATA,
1529 obj.ADUFFZERO,
1530 obj.ADUFFCOPY:
1531 break
1532
1533 case ARDTIMELW:
1534 opset(ARDTIMEHW, r0)
1535 opset(ARDTIMED, r0)
1536
1537 case ACLOW:
1538 opset(ACLZW, r0)
1539 opset(ACTOW, r0)
1540 opset(ACTZW, r0)
1541 opset(ACLOV, r0)
1542 opset(ACLZV, r0)
1543 opset(ACTOV, r0)
1544 opset(ACTZV, r0)
1545 opset(AREVB2H, r0)
1546 opset(AREVB4H, r0)
1547 opset(AREVB2W, r0)
1548 opset(AREVBV, r0)
1549 opset(AREVH2W, r0)
1550 opset(AREVHV, r0)
1551 opset(ABITREV4B, r0)
1552 opset(ABITREV8B, r0)
1553 opset(ABITREVW, r0)
1554 opset(ABITREVV, r0)
1555 opset(AEXTWB, r0)
1556 opset(AEXTWH, r0)
1557 opset(ACPUCFG, r0)
1558
1559 case ATEQ:
1560 opset(ATNE, r0)
1561
1562 case AMASKEQZ:
1563 opset(AMASKNEZ, r0)
1564 opset(ACRCWBW, r0)
1565 opset(ACRCWHW, r0)
1566 opset(ACRCWWW, r0)
1567 opset(ACRCWVW, r0)
1568 opset(ACRCCWBW, r0)
1569 opset(ACRCCWHW, r0)
1570 opset(ACRCCWWW, r0)
1571 opset(ACRCCWVW, r0)
1572
1573 case ANOOP:
1574 opset(obj.AUNDEF, r0)
1575
1576 case AAMSWAPW:
1577 for i := range atomicInst {
1578 if i == AAMSWAPW {
1579 continue
1580 }
1581 opset(i, r0)
1582 }
1583
1584 case AVSEQB:
1585 opset(AVSEQH, r0)
1586 opset(AVSEQW, r0)
1587 opset(AVSEQV, r0)
1588 opset(AVILVLB, r0)
1589 opset(AVILVLH, r0)
1590 opset(AVILVLW, r0)
1591 opset(AVILVLV, r0)
1592 opset(AVILVHB, r0)
1593 opset(AVILVHH, r0)
1594 opset(AVILVHW, r0)
1595 opset(AVILVHV, r0)
1596 opset(AVMULB, r0)
1597 opset(AVMULH, r0)
1598 opset(AVMULW, r0)
1599 opset(AVMULV, r0)
1600 opset(AVMUHB, r0)
1601 opset(AVMUHH, r0)
1602 opset(AVMUHW, r0)
1603 opset(AVMUHV, r0)
1604 opset(AVMUHBU, r0)
1605 opset(AVMUHHU, r0)
1606 opset(AVMUHWU, r0)
1607 opset(AVMUHVU, r0)
1608 opset(AVDIVB, r0)
1609 opset(AVDIVH, r0)
1610 opset(AVDIVW, r0)
1611 opset(AVDIVV, r0)
1612 opset(AVMODB, r0)
1613 opset(AVMODH, r0)
1614 opset(AVMODW, r0)
1615 opset(AVMODV, r0)
1616 opset(AVDIVBU, r0)
1617 opset(AVDIVHU, r0)
1618 opset(AVDIVWU, r0)
1619 opset(AVDIVVU, r0)
1620 opset(AVMODBU, r0)
1621 opset(AVMODHU, r0)
1622 opset(AVMODWU, r0)
1623 opset(AVMODVU, r0)
1624 opset(AVMULWEVHB, r0)
1625 opset(AVMULWEVWH, r0)
1626 opset(AVMULWEVVW, r0)
1627 opset(AVMULWEVQV, r0)
1628 opset(AVMULWODHB, r0)
1629 opset(AVMULWODWH, r0)
1630 opset(AVMULWODVW, r0)
1631 opset(AVMULWODQV, r0)
1632 opset(AVMULWEVHBU, r0)
1633 opset(AVMULWEVWHU, r0)
1634 opset(AVMULWEVVWU, r0)
1635 opset(AVMULWEVQVU, r0)
1636 opset(AVMULWODHBU, r0)
1637 opset(AVMULWODWHU, r0)
1638 opset(AVMULWODVWU, r0)
1639 opset(AVMULWODQVU, r0)
1640 opset(AVMULWEVHBUB, r0)
1641 opset(AVMULWEVWHUH, r0)
1642 opset(AVMULWEVVWUW, r0)
1643 opset(AVMULWEVQVUV, r0)
1644 opset(AVMULWODHBUB, r0)
1645 opset(AVMULWODWHUH, r0)
1646 opset(AVMULWODVWUW, r0)
1647 opset(AVMULWODQVUV, r0)
1648 opset(AVADDF, r0)
1649 opset(AVADDD, r0)
1650 opset(AVSUBF, r0)
1651 opset(AVSUBD, r0)
1652 opset(AVMULF, r0)
1653 opset(AVMULD, r0)
1654 opset(AVDIVF, r0)
1655 opset(AVDIVD, r0)
1656
1657 case AXVSEQB:
1658 opset(AXVSEQH, r0)
1659 opset(AXVSEQW, r0)
1660 opset(AXVSEQV, r0)
1661 opset(AXVILVLB, r0)
1662 opset(AXVILVLH, r0)
1663 opset(AXVILVLW, r0)
1664 opset(AXVILVLV, r0)
1665 opset(AXVILVHB, r0)
1666 opset(AXVILVHH, r0)
1667 opset(AXVILVHW, r0)
1668 opset(AXVILVHV, r0)
1669 opset(AXVMULB, r0)
1670 opset(AXVMULH, r0)
1671 opset(AXVMULW, r0)
1672 opset(AXVMULV, r0)
1673 opset(AXVMUHB, r0)
1674 opset(AXVMUHH, r0)
1675 opset(AXVMUHW, r0)
1676 opset(AXVMUHV, r0)
1677 opset(AXVMUHBU, r0)
1678 opset(AXVMUHHU, r0)
1679 opset(AXVMUHWU, r0)
1680 opset(AXVMUHVU, r0)
1681 opset(AXVDIVB, r0)
1682 opset(AXVDIVH, r0)
1683 opset(AXVDIVW, r0)
1684 opset(AXVDIVV, r0)
1685 opset(AXVMODB, r0)
1686 opset(AXVMODH, r0)
1687 opset(AXVMODW, r0)
1688 opset(AXVMODV, r0)
1689 opset(AXVDIVBU, r0)
1690 opset(AXVDIVHU, r0)
1691 opset(AXVDIVWU, r0)
1692 opset(AXVDIVVU, r0)
1693 opset(AXVMODBU, r0)
1694 opset(AXVMODHU, r0)
1695 opset(AXVMODWU, r0)
1696 opset(AXVMODVU, r0)
1697 opset(AXVMULWEVHB, r0)
1698 opset(AXVMULWEVWH, r0)
1699 opset(AXVMULWEVVW, r0)
1700 opset(AXVMULWEVQV, r0)
1701 opset(AXVMULWODHB, r0)
1702 opset(AXVMULWODWH, r0)
1703 opset(AXVMULWODVW, r0)
1704 opset(AXVMULWODQV, r0)
1705 opset(AXVMULWEVHBU, r0)
1706 opset(AXVMULWEVWHU, r0)
1707 opset(AXVMULWEVVWU, r0)
1708 opset(AXVMULWEVQVU, r0)
1709 opset(AXVMULWODHBU, r0)
1710 opset(AXVMULWODWHU, r0)
1711 opset(AXVMULWODVWU, r0)
1712 opset(AXVMULWODQVU, r0)
1713 opset(AXVMULWEVHBUB, r0)
1714 opset(AXVMULWEVWHUH, r0)
1715 opset(AXVMULWEVVWUW, r0)
1716 opset(AXVMULWEVQVUV, r0)
1717 opset(AXVMULWODHBUB, r0)
1718 opset(AXVMULWODWHUH, r0)
1719 opset(AXVMULWODVWUW, r0)
1720 opset(AXVMULWODQVUV, r0)
1721 opset(AXVADDF, r0)
1722 opset(AXVADDD, r0)
1723 opset(AXVSUBF, r0)
1724 opset(AXVSUBD, r0)
1725 opset(AXVMULF, r0)
1726 opset(AXVMULD, r0)
1727 opset(AXVDIVF, r0)
1728 opset(AXVDIVD, r0)
1729
1730 case AVANDB:
1731 opset(AVORB, r0)
1732 opset(AVXORB, r0)
1733 opset(AVNORB, r0)
1734 opset(AVSHUF4IB, r0)
1735 opset(AVSHUF4IH, r0)
1736 opset(AVSHUF4IW, r0)
1737 opset(AVSHUF4IV, r0)
1738
1739 case AXVANDB:
1740 opset(AXVORB, r0)
1741 opset(AXVXORB, r0)
1742 opset(AXVNORB, r0)
1743 opset(AXVSHUF4IB, r0)
1744 opset(AXVSHUF4IH, r0)
1745 opset(AXVSHUF4IW, r0)
1746 opset(AXVSHUF4IV, r0)
1747
1748 case AVANDV:
1749 opset(AVORV, r0)
1750 opset(AVXORV, r0)
1751 opset(AVNORV, r0)
1752 opset(AVANDNV, r0)
1753 opset(AVORNV, r0)
1754
1755 case AXVANDV:
1756 opset(AXVORV, r0)
1757 opset(AXVXORV, r0)
1758 opset(AXVNORV, r0)
1759 opset(AXVANDNV, r0)
1760 opset(AXVORNV, r0)
1761
1762 case AVPCNTB:
1763 opset(AVPCNTH, r0)
1764 opset(AVPCNTW, r0)
1765 opset(AVPCNTV, r0)
1766 opset(AVFSQRTF, r0)
1767 opset(AVFSQRTD, r0)
1768 opset(AVFRECIPF, r0)
1769 opset(AVFRECIPD, r0)
1770 opset(AVFRSQRTF, r0)
1771 opset(AVFRSQRTD, r0)
1772 opset(AVNEGB, r0)
1773 opset(AVNEGH, r0)
1774 opset(AVNEGW, r0)
1775 opset(AVNEGV, r0)
1776 opset(AVFRINTRNEF, r0)
1777 opset(AVFRINTRNED, r0)
1778 opset(AVFRINTRZF, r0)
1779 opset(AVFRINTRZD, r0)
1780 opset(AVFRINTRPF, r0)
1781 opset(AVFRINTRPD, r0)
1782 opset(AVFRINTRMF, r0)
1783 opset(AVFRINTRMD, r0)
1784 opset(AVFRINTF, r0)
1785 opset(AVFRINTD, r0)
1786 opset(AVFCLASSF, r0)
1787 opset(AVFCLASSD, r0)
1788
1789 case AXVPCNTB:
1790 opset(AXVPCNTH, r0)
1791 opset(AXVPCNTW, r0)
1792 opset(AXVPCNTV, r0)
1793 opset(AXVFSQRTF, r0)
1794 opset(AXVFSQRTD, r0)
1795 opset(AXVFRECIPF, r0)
1796 opset(AXVFRECIPD, r0)
1797 opset(AXVFRSQRTF, r0)
1798 opset(AXVFRSQRTD, r0)
1799 opset(AXVNEGB, r0)
1800 opset(AXVNEGH, r0)
1801 opset(AXVNEGW, r0)
1802 opset(AXVNEGV, r0)
1803 opset(AXVFRINTRNEF, r0)
1804 opset(AXVFRINTRNED, r0)
1805 opset(AXVFRINTRZF, r0)
1806 opset(AXVFRINTRZD, r0)
1807 opset(AXVFRINTRPF, r0)
1808 opset(AXVFRINTRPD, r0)
1809 opset(AXVFRINTRMF, r0)
1810 opset(AXVFRINTRMD, r0)
1811 opset(AXVFRINTF, r0)
1812 opset(AXVFRINTD, r0)
1813 opset(AXVFCLASSF, r0)
1814 opset(AXVFCLASSD, r0)
1815
1816 case AVADDB:
1817 opset(AVADDH, r0)
1818 opset(AVADDW, r0)
1819 opset(AVADDV, r0)
1820 opset(AVADDQ, r0)
1821 opset(AVSUBB, r0)
1822 opset(AVSUBH, r0)
1823 opset(AVSUBW, r0)
1824 opset(AVSUBV, r0)
1825 opset(AVSUBQ, r0)
1826
1827 case AXVADDB:
1828 opset(AXVADDH, r0)
1829 opset(AXVADDW, r0)
1830 opset(AXVADDV, r0)
1831 opset(AXVADDQ, r0)
1832 opset(AXVSUBB, r0)
1833 opset(AXVSUBH, r0)
1834 opset(AXVSUBW, r0)
1835 opset(AXVSUBV, r0)
1836 opset(AXVSUBQ, r0)
1837
1838 case AVSLLB:
1839 opset(AVSRLB, r0)
1840 opset(AVSRAB, r0)
1841 opset(AVROTRB, r0)
1842 opset(AVBITCLRB, r0)
1843 opset(AVBITSETB, r0)
1844 opset(AVBITREVB, r0)
1845
1846 case AXVSLLB:
1847 opset(AXVSRLB, r0)
1848 opset(AXVSRAB, r0)
1849 opset(AXVROTRB, r0)
1850 opset(AXVBITCLRB, r0)
1851 opset(AXVBITSETB, r0)
1852 opset(AXVBITREVB, r0)
1853
1854 case AVSLLH:
1855 opset(AVSRLH, r0)
1856 opset(AVSRAH, r0)
1857 opset(AVROTRH, r0)
1858 opset(AVBITCLRH, r0)
1859 opset(AVBITSETH, r0)
1860 opset(AVBITREVH, r0)
1861
1862 case AXVSLLH:
1863 opset(AXVSRLH, r0)
1864 opset(AXVSRAH, r0)
1865 opset(AXVROTRH, r0)
1866 opset(AXVBITCLRH, r0)
1867 opset(AXVBITSETH, r0)
1868 opset(AXVBITREVH, r0)
1869
1870 case AVSLLW:
1871 opset(AVSRLW, r0)
1872 opset(AVSRAW, r0)
1873 opset(AVROTRW, r0)
1874 opset(AVADDBU, r0)
1875 opset(AVADDHU, r0)
1876 opset(AVADDWU, r0)
1877 opset(AVADDVU, r0)
1878 opset(AVSUBBU, r0)
1879 opset(AVSUBHU, r0)
1880 opset(AVSUBWU, r0)
1881 opset(AVSUBVU, r0)
1882 opset(AVBITCLRW, r0)
1883 opset(AVBITSETW, r0)
1884 opset(AVBITREVW, r0)
1885
1886 case AXVSLLW:
1887 opset(AXVSRLW, r0)
1888 opset(AXVSRAW, r0)
1889 opset(AXVROTRW, r0)
1890 opset(AXVADDBU, r0)
1891 opset(AXVADDHU, r0)
1892 opset(AXVADDWU, r0)
1893 opset(AXVADDVU, r0)
1894 opset(AXVSUBBU, r0)
1895 opset(AXVSUBHU, r0)
1896 opset(AXVSUBWU, r0)
1897 opset(AXVSUBVU, r0)
1898 opset(AXVBITCLRW, r0)
1899 opset(AXVBITSETW, r0)
1900 opset(AXVBITREVW, r0)
1901
1902 case AVSLLV:
1903 opset(AVSRLV, r0)
1904 opset(AVSRAV, r0)
1905 opset(AVROTRV, r0)
1906 opset(AVBITCLRV, r0)
1907 opset(AVBITSETV, r0)
1908 opset(AVBITREVV, r0)
1909
1910 case AXVSLLV:
1911 opset(AXVSRLV, r0)
1912 opset(AXVSRAV, r0)
1913 opset(AXVROTRV, r0)
1914 opset(AXVBITCLRV, r0)
1915 opset(AXVBITSETV, r0)
1916 opset(AXVBITREVV, r0)
1917
1918 case AVSETEQV:
1919 opset(AVSETNEV, r0)
1920 opset(AVSETANYEQB, r0)
1921 opset(AVSETANYEQH, r0)
1922 opset(AVSETANYEQW, r0)
1923 opset(AVSETANYEQV, r0)
1924 opset(AVSETALLNEB, r0)
1925 opset(AVSETALLNEH, r0)
1926 opset(AVSETALLNEW, r0)
1927 opset(AVSETALLNEV, r0)
1928
1929 case AXVSETEQV:
1930 opset(AXVSETNEV, r0)
1931 opset(AXVSETANYEQB, r0)
1932 opset(AXVSETANYEQH, r0)
1933 opset(AXVSETANYEQW, r0)
1934 opset(AXVSETANYEQV, r0)
1935 opset(AXVSETALLNEB, r0)
1936 opset(AXVSETALLNEH, r0)
1937 opset(AXVSETALLNEW, r0)
1938 opset(AXVSETALLNEV, r0)
1939
1940 }
1941 }
1942 }
1943
1944 func OP_RRRR(op uint32, r1 uint32, r2 uint32, r3 uint32, r4 uint32) uint32 {
1945 return op | (r1&0x1F)<<15 | (r2&0x1F)<<10 | (r3&0x1F)<<5 | (r4 & 0x1F)
1946 }
1947
1948
1949
1950
1951 func OP_RRR(op uint32, r1 uint32, r2 uint32, r3 uint32) uint32 {
1952 return op | (r1&0x1F)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
1953 }
1954
1955
1956
1957 func OP_RR(op uint32, r2 uint32, r3 uint32) uint32 {
1958 return op | (r2&0x1F)<<5 | (r3&0x1F)<<0
1959 }
1960
1961 func OP_2IRRR(op uint32, i uint32, r2 uint32, r3 uint32, r4 uint32) uint32 {
1962 return op | (i&0x3)<<15 | (r2&0x1F)<<10 | (r3&0x1F)<<5 | (r4&0x1F)<<0
1963 }
1964
1965 func OP_16IR_5I(op uint32, i uint32, r2 uint32) uint32 {
1966 return op | (i&0xFFFF)<<10 | (r2&0x1F)<<5 | ((i >> 16) & 0x1F)
1967 }
1968
1969 func OP_16IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
1970 return op | (i&0xFFFF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
1971 }
1972
1973 func OP_12IR_5I(op uint32, i1 uint32, r2 uint32, i2 uint32) uint32 {
1974 return op | (i1&0xFFF)<<10 | (r2&0x1F)<<5 | (i2&0x1F)<<0
1975 }
1976
1977 func OP_12IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
1978 return op | (i&0xFFF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
1979 }
1980
1981 func OP_8IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
1982 return op | (i&0xFF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
1983 }
1984
1985 func OP_6IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
1986 return op | (i&0x3F)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
1987 }
1988
1989 func OP_5IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
1990 return op | (i&0x1F)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
1991 }
1992
1993 func OP_4IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
1994 return op | (i&0xF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
1995 }
1996
1997 func OP_3IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
1998 return op | (i&0x7)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
1999 }
2000
2001 func OP_IR(op uint32, i uint32, r2 uint32) uint32 {
2002 return op | (i&0xFFFFF)<<5 | (r2&0x1F)<<0
2003 }
2004
2005 func OP_15I(op uint32, i uint32) uint32 {
2006 return op | (i&0x7FFF)<<0
2007 }
2008
2009
2010
2011
2012
2013 func OP_IRIR(op uint32, i1 uint32, r2 uint32, i3 uint32, r4 uint32) uint32 {
2014 return op | (i1 << 16) | (r2&0x1F)<<5 | (i3 << 10) | (r4&0x1F)<<0
2015 }
2016
2017
2018 func OP_B_BL(op uint32, i uint32) uint32 {
2019 return op | ((i & 0xFFFF) << 10) | ((i >> 16) & 0x3FF)
2020 }
2021
2022 func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) {
2023 o1 := uint32(0)
2024 o2 := uint32(0)
2025 o3 := uint32(0)
2026 o4 := uint32(0)
2027 o5 := uint32(0)
2028
2029 add := AADDU
2030 add = AADDVU
2031
2032 switch o.type_ {
2033 default:
2034 c.ctxt.Diag("unknown type %d %v", o.type_)
2035 prasm(p)
2036
2037 case 0:
2038 break
2039
2040 case 1:
2041 a := AOR
2042 if p.As == AMOVW {
2043 a = ASLL
2044 }
2045 o1 = OP_RRR(c.oprrr(a), uint32(REGZERO), uint32(p.From.Reg), uint32(p.To.Reg))
2046
2047 case 2:
2048 r := int(p.Reg)
2049 if p.As == ANEGW || p.As == ANEGV {
2050 r = REGZERO
2051 }
2052 if r == 0 {
2053 r = int(p.To.Reg)
2054 }
2055 o1 = OP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(r), uint32(p.To.Reg))
2056
2057 case 3:
2058 v := c.regoff(&p.From)
2059
2060 r := int(p.From.Reg)
2061 if r == 0 {
2062 r = int(o.param)
2063 }
2064 a := add
2065 if o.from1 == C_12CON && v > 0 {
2066 a = AOR
2067 }
2068
2069 o1 = OP_12IRR(c.opirr(a), uint32(v), uint32(r), uint32(p.To.Reg))
2070
2071 case 4:
2072 v := c.regoff(&p.From)
2073 r := int(p.Reg)
2074 if r == 0 {
2075 r = int(p.To.Reg)
2076 }
2077 o1 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2078
2079 case 5:
2080 v := c.regoff(&p.From)
2081 o1 = OP_15I(c.opi(p.As), uint32(v))
2082
2083 case 6:
2084 v := int32(0)
2085 if p.To.Target() != nil {
2086 v = int32(p.To.Target().Pc-p.Pc) >> 2
2087 }
2088 as, rd, rj, width := p.As, p.Reg, p.From.Reg, 16
2089 switch as {
2090 case ABGTZ, ABLEZ:
2091 rd, rj = rj, rd
2092 case ABFPT, ABFPF:
2093 width = 21
2094
2095
2096 if rj == 0 {
2097 rj = REG_FCC0
2098 }
2099 case ABEQ, ABNE:
2100 if rd == 0 || rd == REGZERO || rj == REGZERO {
2101
2102 width = 21
2103 as = -as
2104 if rj == 0 || rj == REGZERO {
2105 rj = rd
2106 }
2107 }
2108 }
2109 switch width {
2110 case 21:
2111 if (v<<11)>>11 != v {
2112 c.ctxt.Diag("21 bit-width, short branch too far\n%v", p)
2113 }
2114 o1 = OP_16IR_5I(c.opirr(as), uint32(v), uint32(rj))
2115 case 16:
2116 if (v<<16)>>16 != v {
2117 c.ctxt.Diag("16 bit-width, short branch too far\n%v", p)
2118 }
2119 o1 = OP_16IRR(c.opirr(as), uint32(v), uint32(rj), uint32(rd))
2120 default:
2121 c.ctxt.Diag("unexpected branch encoding\n%v", p)
2122 }
2123
2124 case 7:
2125 r := int(p.To.Reg)
2126 if r == 0 {
2127 r = int(o.param)
2128 }
2129 v := c.regoff(&p.To)
2130 o1 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.From.Reg))
2131
2132 case 8:
2133 r := int(p.From.Reg)
2134 if r == 0 {
2135 r = int(o.param)
2136 }
2137 v := c.regoff(&p.From)
2138 o1 = OP_12IRR(c.opirr(-p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2139
2140 case 9:
2141 o1 = OP_RR(c.oprr(p.As), uint32(p.From.Reg), uint32(p.To.Reg))
2142
2143 case 10:
2144 v := c.regoff(&p.From)
2145 a := AOR
2146 if v < 0 {
2147 a = AADDU
2148 }
2149 o1 = OP_12IRR(c.opirr(a), uint32(v), uint32(0), uint32(REGTMP))
2150 r := int(p.Reg)
2151 if r == 0 {
2152 r = int(p.To.Reg)
2153 }
2154 o2 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
2155
2156 case 11:
2157 v := int32(0)
2158 if p.To.Target() != nil {
2159 v = int32(p.To.Target().Pc-p.Pc) >> 2
2160 }
2161 o1 = OP_B_BL(c.opirr(p.As), uint32(v))
2162 if p.To.Sym != nil {
2163 c.cursym.AddRel(c.ctxt, obj.Reloc{
2164 Type: objabi.R_CALLLOONG64,
2165 Off: int32(c.pc),
2166 Siz: 4,
2167 Sym: p.To.Sym,
2168 Add: p.To.Offset,
2169 })
2170 }
2171
2172 case 12:
2173 switch p.As {
2174 case AMOVB:
2175 o1 = OP_RR(c.oprr(AEXTWB), uint32(p.From.Reg), uint32(p.To.Reg))
2176 case AMOVH:
2177 o1 = OP_RR(c.oprr(AEXTWH), uint32(p.From.Reg), uint32(p.To.Reg))
2178 case AMOVBU:
2179 o1 = OP_12IRR(c.opirr(AAND), uint32(0xff), uint32(p.From.Reg), uint32(p.To.Reg))
2180 case AMOVHU:
2181 o1 = OP_IRIR(c.opirir(ABSTRPICKV), 15, uint32(p.From.Reg), 0, uint32(p.To.Reg))
2182 case AMOVWU:
2183 o1 = OP_IRIR(c.opirir(ABSTRPICKV), 31, uint32(p.From.Reg), 0, uint32(p.To.Reg))
2184 default:
2185 c.ctxt.Diag("unexpected encoding\n%v", p)
2186 }
2187
2188 case 13:
2189 v := c.regoff(&p.From)
2190 r := int(p.Reg)
2191 if r == 0 {
2192 r = int(p.To.Reg)
2193 }
2194 o1 = OP_3IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2195
2196 case 14:
2197 v := c.regoff(&p.From)
2198 r := int(p.Reg)
2199 if r == 0 {
2200 r = int(p.To.Reg)
2201 }
2202 o1 = OP_4IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2203
2204 case 15:
2205 v := c.regoff(&p.From)
2206 r := int(p.Reg)
2207 if r == 0 {
2208 r = REGZERO
2209 }
2210
2218 if p.As == ATEQ {
2219 o1 = OP_16IRR(c.opirr(ABNE), uint32(2), uint32(r), uint32(p.To.Reg))
2220 } else {
2221 o1 = OP_16IRR(c.opirr(ABEQ), uint32(2), uint32(r), uint32(p.To.Reg))
2222 }
2223 o2 = OP_15I(c.opi(ABREAK), uint32(v))
2224
2225 case 16:
2226 v := c.regoff(&p.From)
2227 r := int(p.Reg)
2228 if r == 0 {
2229 r = int(p.To.Reg)
2230 }
2231
2232
2233 if v >= 32 && vshift(p.As) {
2234 o1 = OP_16IRR(c.opirr(p.As), uint32(v)&0x3f, uint32(r), uint32(p.To.Reg))
2235 } else {
2236 o1 = OP_16IRR(c.opirr(p.As), uint32(v)&0x1f, uint32(r), uint32(p.To.Reg))
2237 }
2238
2239 case 17:
2240 rd, rj := p.To.Reg, p.Reg
2241 if rj == obj.REG_NONE {
2242 rj = rd
2243 }
2244 msb, lsb := p.From.Offset, p.GetFrom3().Offset
2245
2246
2247 var b uint32
2248 if p.As == ABSTRPICKW || p.As == ABSTRINSW {
2249 b = 32
2250 } else {
2251 b = 64
2252 }
2253 if lsb < 0 || uint32(lsb) >= b || msb < 0 || uint32(msb) >= b || uint32(lsb) > uint32(msb) {
2254 c.ctxt.Diag("illegal bit number\n%v", p)
2255 }
2256
2257 o1 = OP_IRIR(c.opirir(p.As), uint32(msb), uint32(rj), uint32(lsb), uint32(rd))
2258
2259 case 18:
2260 r := int(p.Reg)
2261 if r == 0 {
2262 r = int(o.param)
2263 }
2264 o1 = OP_RRR(c.oprrr(p.As), uint32(0), uint32(p.To.Reg), uint32(r))
2265 if p.As == obj.ACALL {
2266 c.cursym.AddRel(c.ctxt, obj.Reloc{
2267 Type: objabi.R_CALLIND,
2268 Off: int32(c.pc),
2269 })
2270 }
2271
2272 case 19:
2273
2274
2275 v := c.regoff(&p.From)
2276 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
2277 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(p.To.Reg), uint32(p.To.Reg))
2278
2279 case 20:
2280 o1 = OP_RRR(c.oprrr(p.As), uint32(p.To.Index), uint32(p.To.Reg), uint32(p.From.Reg))
2281
2282 case 21:
2283 o1 = OP_RRR(c.oprrr(-p.As), uint32(p.From.Index), uint32(p.From.Reg), uint32(p.To.Reg))
2284
2285 case 22:
2286 v := c.regoff(&p.From)
2287 r := int(p.Reg)
2288 if r == 0 {
2289 r = int(p.To.Reg)
2290 }
2291
2292 o1 = OP_5IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2293
2294 case 23:
2295 v := c.regoff(&p.From)
2296 r := int(p.Reg)
2297 if r == 0 {
2298 r = int(p.To.Reg)
2299 }
2300
2301
2302 if p.As == AVSHUF4IV || p.As == AXVSHUF4IV {
2303 operand := uint32(v)
2304 c.checkoperand(p, operand, 15)
2305 }
2306
2307 o1 = OP_8IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2308
2309 case 24:
2310 v := c.regoff(&p.From)
2311 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
2312 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
2313 r := int(p.Reg)
2314 if r == 0 {
2315 r = int(p.To.Reg)
2316 }
2317 o3 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
2318
2319 case 25:
2320 v := c.regoff(&p.From)
2321 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
2322
2323 case 26:
2324 v := c.regoff(&p.From)
2325 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
2326 r := int(p.Reg)
2327 if r == 0 {
2328 r = int(p.To.Reg)
2329 }
2330 o2 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
2331
2332 case 27:
2333 v := c.regoff(&p.From)
2334 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
2335 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
2336 r := int(p.From.Reg)
2337 if r == 0 {
2338 r = int(o.param)
2339 }
2340 o3 = OP_RRR(c.oprrr(add), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
2341
2342 case 28:
2343 v := c.regoff(&p.From)
2344 r := int(p.From.Reg)
2345 if r == 0 {
2346 r = int(o.param)
2347 }
2348 switch o.size {
2349 case 12:
2350 o1 = OP_IR(c.opir(ALU12IW), uint32((v+1<<11)>>12), uint32(REGTMP))
2351 o2 = OP_RRR(c.oprrr(add), uint32(r), uint32(REGTMP), uint32(REGTMP))
2352 o3 = OP_12IRR(c.opirr(-p.As), uint32(v), uint32(REGTMP), uint32(p.To.Reg))
2353
2354 case 4:
2355 o1 = OP_12IRR(c.opirr(-p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2356 }
2357
2358 case 29:
2359 v := c.regoff(&p.To)
2360 r := int(p.To.Reg)
2361 if r == 0 {
2362 r = int(o.param)
2363 }
2364 switch o.size {
2365 case 12:
2366 o1 = OP_IR(c.opir(ALU12IW), uint32((v+1<<11)>>12), uint32(REGTMP))
2367 o2 = OP_RRR(c.oprrr(add), uint32(r), uint32(REGTMP), uint32(REGTMP))
2368 o3 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(REGTMP), uint32(p.From.Reg))
2369
2370 case 4:
2371 o1 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.From.Reg))
2372 }
2373
2374 case 30:
2375 a := c.specialFpMovInst(p.As, oclass(&p.From), oclass(&p.To))
2376 o1 = OP_RR(a, uint32(p.From.Reg), uint32(p.To.Reg))
2377
2378 case 31:
2379 v := c.regoff(&p.From)
2380 r := int(p.Reg)
2381 if r == 0 {
2382 r = int(p.To.Reg)
2383 }
2384 o1 = OP_5IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2385
2386 case 32:
2387 v := c.regoff(&p.From)
2388 r := int(p.Reg)
2389 if r == 0 {
2390 r = int(p.To.Reg)
2391 }
2392 o1 = OP_6IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2393
2394 case 33:
2395 ca := uint32(p.From.Reg)
2396 fk := uint32(p.Reg)
2397 fd := uint32(p.To.Reg)
2398 fj := fd
2399 if len(p.RestArgs) > 0 {
2400 fj = uint32(p.GetFrom3().Reg)
2401 }
2402 o1 = 0x340<<18 | (ca&0x7)<<15 | (fk&0x1F)<<10 | (fj&0x1F)<<5 | (fd & 0x1F)
2403
2404 case 34:
2405 v := c.regoff(&p.From)
2406 a := AADDU
2407 if v > 0 {
2408 a = AOR
2409 }
2410 a2 := c.specialFpMovInst(p.As, C_REG, oclass(&p.To))
2411 o1 = OP_12IRR(c.opirr(a), uint32(v), uint32(0), uint32(REGTMP))
2412 o2 = OP_RR(a2, uint32(REGTMP), uint32(p.To.Reg))
2413
2414 case 35:
2415 v := c.regoff(&p.To)
2416 r := int(p.To.Reg)
2417 if r == 0 {
2418 r = int(o.param)
2419 }
2420 o1 = OP_IR(c.opir(ALU12IW), uint32((v+1<<11)>>12), uint32(REGTMP))
2421 o2 = OP_RRR(c.oprrr(add), uint32(r), uint32(REGTMP), uint32(REGTMP))
2422 o3 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(REGTMP), uint32(p.From.Reg))
2423
2424 case 36:
2425 v := c.regoff(&p.From)
2426 r := int(p.From.Reg)
2427 if r == 0 {
2428 r = int(o.param)
2429 }
2430 o1 = OP_IR(c.opir(ALU12IW), uint32((v+1<<11)>>12), uint32(REGTMP))
2431 o2 = OP_RRR(c.oprrr(add), uint32(r), uint32(REGTMP), uint32(REGTMP))
2432 o3 = OP_12IRR(c.opirr(-p.As), uint32(v), uint32(REGTMP), uint32(p.To.Reg))
2433
2434 case 37:
2435 r := int(p.To.Reg)
2436 if len(p.RestArgs) > 0 {
2437 r = int(p.GetFrom3().Reg)
2438 }
2439 o1 = OP_RRRR(c.oprrrr(p.As), uint32(p.From.Reg), uint32(p.Reg), uint32(r), uint32(p.To.Reg))
2440
2441 case 38:
2442 o1 = uint32(c.regoff(&p.From))
2443
2444 case 39:
2445 v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
2446 if v == 0 {
2447 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2448 }
2449
2450 Rj := uint32(p.From.Reg & EXT_REG_MASK)
2451 Vd := uint32(p.To.Reg & EXT_REG_MASK)
2452 index := uint32(p.To.Index)
2453 c.checkindex(p, index, m)
2454 o1 = v | (index << 10) | (Rj << 5) | Vd
2455
2456 case 40:
2457 v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
2458 if v == 0 {
2459 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2460 }
2461
2462 Vj := uint32(p.From.Reg & EXT_REG_MASK)
2463 Rd := uint32(p.To.Reg & EXT_REG_MASK)
2464 index := uint32(p.From.Index)
2465 c.checkindex(p, index, m)
2466 o1 = v | (index << 10) | (Vj << 5) | Rd
2467
2468 case 41:
2469 v, _ := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
2470 if v == 0 {
2471 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2472 }
2473
2474 Rj := uint32(p.From.Reg & EXT_REG_MASK)
2475 Vd := uint32(p.To.Reg & EXT_REG_MASK)
2476 o1 = v | (Rj << 5) | Vd
2477
2478 case 42:
2479 v, _ := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
2480 if v == 0 {
2481 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2482 }
2483
2484 Xj := uint32(p.From.Reg & EXT_REG_MASK)
2485 Xd := uint32(p.To.Reg & EXT_REG_MASK)
2486 o1 = v | (Xj << 5) | Xd
2487
2488 case 43:
2489 v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
2490 if v == 0 {
2491 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2492 }
2493
2494 Xj := uint32(p.From.Reg & EXT_REG_MASK)
2495 Xd := uint32(p.To.Reg & EXT_REG_MASK)
2496 index := uint32(p.To.Index)
2497 c.checkindex(p, index, m)
2498 o1 = v | (index << 10) | (Xj << 5) | Xd
2499
2500 case 44:
2501 v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
2502 if v == 0 {
2503 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2504 }
2505
2506 Xj := uint32(p.From.Reg & EXT_REG_MASK)
2507 Xd := uint32(p.To.Reg & EXT_REG_MASK)
2508 index := uint32(p.From.Index)
2509 c.checkindex(p, index, m)
2510 o1 = v | (index << 10) | (Xj << 5) | Xd
2511
2512 case 45:
2513 v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
2514 if v == 0 {
2515 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2516 }
2517
2518 vj := uint32(p.From.Reg & EXT_REG_MASK)
2519 vd := uint32(p.To.Reg & EXT_REG_MASK)
2520 index := uint32(p.From.Index)
2521 c.checkindex(p, index, m)
2522 o1 = v | (index << 10) | (vj << 5) | vd
2523
2524 case 46:
2525 v, _ := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, true)
2526 if v == 0 {
2527 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2528 }
2529
2530 si := c.regoff(&p.From)
2531 Rj := uint32(p.From.Reg & EXT_REG_MASK)
2532 Vd := uint32(p.To.Reg & EXT_REG_MASK)
2533 o1 = v | uint32(si<<10) | (Rj << 5) | Vd
2534
2535 case 47:
2536 offs := c.regoff(&p.From)
2537 hint := p.GetFrom3().Offset
2538 o1 = OP_12IR_5I(c.opiir(p.As), uint32(offs), uint32(p.From.Reg), uint32(hint))
2539
2540 case 48:
2541 offs := c.regoff(&p.From)
2542 hint := p.RestArgs[1].Offset
2543 n := uint64(p.GetFrom3().Offset)
2544
2545 addrSeq := (n >> 0) & 0x1
2546 blkSize := (n >> 1) & 0x7ff
2547 blkNums := (n >> 12) & 0x1ff
2548 stride := (n >> 21) & 0xffff
2549
2550 if blkSize > 1024 {
2551 c.ctxt.Diag("%v: block_size amount out of range[16, 1024]: %v\n", p, blkSize)
2552 }
2553
2554 if blkNums > 256 {
2555 c.ctxt.Diag("%v: block_nums amount out of range[1, 256]: %v\n", p, blkSize)
2556 }
2557
2558 v := (uint64(offs) & 0xffff)
2559 v += addrSeq << 16
2560 v += ((blkSize / 16) - 1) << 20
2561 v += (blkNums - 1) << 32
2562 v += stride << 44
2563
2564 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
2565 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
2566 o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
2567 o4 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
2568 o5 = OP_5IRR(c.opirr(p.As), uint32(REGTMP), uint32(p.From.Reg), uint32(hint))
2569
2570 case 49:
2571 if p.As == ANOOP {
2572
2573 o1 = OP_12IRR(c.opirr(AAND), 0, 0, 0)
2574 } else {
2575
2576 o1 = OP_15I(c.opi(ABREAK), 0)
2577 }
2578
2579
2580 case 50:
2581 o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(REGTMP))
2582 c.cursym.AddRel(c.ctxt, obj.Reloc{
2583 Type: objabi.R_LOONG64_ADDR_HI,
2584 Off: int32(c.pc),
2585 Siz: 4,
2586 Sym: p.To.Sym,
2587 Add: p.To.Offset,
2588 })
2589 o2 = OP_12IRR(c.opirr(p.As), uint32(0), uint32(REGTMP), uint32(p.From.Reg))
2590 c.cursym.AddRel(c.ctxt, obj.Reloc{
2591 Type: objabi.R_LOONG64_ADDR_LO,
2592 Off: int32(c.pc + 4),
2593 Siz: 4,
2594 Sym: p.To.Sym,
2595 Add: p.To.Offset,
2596 })
2597
2598 case 51:
2599 o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(REGTMP))
2600 c.cursym.AddRel(c.ctxt, obj.Reloc{
2601 Type: objabi.R_LOONG64_ADDR_HI,
2602 Off: int32(c.pc),
2603 Siz: 4,
2604 Sym: p.From.Sym,
2605 Add: p.From.Offset,
2606 })
2607 o2 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(p.To.Reg))
2608 c.cursym.AddRel(c.ctxt, obj.Reloc{
2609 Type: objabi.R_LOONG64_ADDR_LO,
2610 Off: int32(c.pc + 4),
2611 Siz: 4,
2612 Sym: p.From.Sym,
2613 Add: p.From.Offset,
2614 })
2615
2616 case 52:
2617
2618
2619 o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(p.To.Reg))
2620 c.cursym.AddRel(c.ctxt, obj.Reloc{
2621 Type: objabi.R_LOONG64_ADDR_HI,
2622 Off: int32(c.pc),
2623 Siz: 4,
2624 Sym: p.From.Sym,
2625 Add: p.From.Offset,
2626 })
2627 o2 = OP_12IRR(c.opirr(add), uint32(0), uint32(p.To.Reg), uint32(p.To.Reg))
2628 c.cursym.AddRel(c.ctxt, obj.Reloc{
2629 Type: objabi.R_LOONG64_ADDR_LO,
2630 Off: int32(c.pc + 4),
2631 Siz: 4,
2632 Sym: p.From.Sym,
2633 Add: p.From.Offset,
2634 })
2635
2636 case 53:
2637
2638
2639 o1 = OP_IR(c.opir(ALU12IW), uint32(0), uint32(REGTMP))
2640 c.cursym.AddRel(c.ctxt, obj.Reloc{
2641 Type: objabi.R_LOONG64_TLS_LE_HI,
2642 Off: int32(c.pc),
2643 Siz: 4,
2644 Sym: p.To.Sym,
2645 Add: p.To.Offset,
2646 })
2647 o2 = OP_12IRR(c.opirr(AOR), uint32(0), uint32(REGTMP), uint32(REGTMP))
2648 c.cursym.AddRel(c.ctxt, obj.Reloc{
2649 Type: objabi.R_LOONG64_TLS_LE_LO,
2650 Off: int32(c.pc + 4),
2651 Siz: 4,
2652 Sym: p.To.Sym,
2653 Add: p.To.Offset,
2654 })
2655 o3 = OP_RRR(c.oprrr(AADDV), uint32(REG_R2), uint32(REGTMP), uint32(REGTMP))
2656 o4 = OP_12IRR(c.opirr(p.As), uint32(0), uint32(REGTMP), uint32(p.From.Reg))
2657
2658 case 54:
2659
2660
2661 o1 = OP_IR(c.opir(ALU12IW), uint32(0), uint32(REGTMP))
2662 c.cursym.AddRel(c.ctxt, obj.Reloc{
2663 Type: objabi.R_LOONG64_TLS_LE_HI,
2664 Off: int32(c.pc),
2665 Siz: 4,
2666 Sym: p.From.Sym,
2667 Add: p.From.Offset,
2668 })
2669 o2 = OP_12IRR(c.opirr(AOR), uint32(0), uint32(REGTMP), uint32(REGTMP))
2670 c.cursym.AddRel(c.ctxt, obj.Reloc{
2671 Type: objabi.R_LOONG64_TLS_LE_LO,
2672 Off: int32(c.pc + 4),
2673 Siz: 4,
2674 Sym: p.From.Sym,
2675 Add: p.From.Offset,
2676 })
2677 o3 = OP_RRR(c.oprrr(AADDV), uint32(REG_R2), uint32(REGTMP), uint32(REGTMP))
2678 o4 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(p.To.Reg))
2679
2680 case 56:
2681 o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(REGTMP))
2682 c.cursym.AddRel(c.ctxt, obj.Reloc{
2683 Type: objabi.R_LOONG64_TLS_IE_HI,
2684 Off: int32(c.pc),
2685 Siz: 4,
2686 Sym: p.To.Sym,
2687 })
2688 o2 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(REGTMP))
2689 c.cursym.AddRel(c.ctxt, obj.Reloc{
2690 Type: objabi.R_LOONG64_TLS_IE_LO,
2691 Off: int32(c.pc + 4),
2692 Siz: 4,
2693 Sym: p.To.Sym,
2694 })
2695 o3 = OP_RRR(c.oprrr(AADDVU), uint32(REGTMP), uint32(REG_R2), uint32(REGTMP))
2696 o4 = OP_12IRR(c.opirr(p.As), uint32(0), uint32(REGTMP), uint32(p.From.Reg))
2697
2698 case 57:
2699 o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(REGTMP))
2700 c.cursym.AddRel(c.ctxt, obj.Reloc{
2701 Type: objabi.R_LOONG64_TLS_IE_HI,
2702 Off: int32(c.pc),
2703 Siz: 4,
2704 Sym: p.From.Sym,
2705 })
2706 o2 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(REGTMP))
2707 c.cursym.AddRel(c.ctxt, obj.Reloc{
2708 Type: objabi.R_LOONG64_TLS_IE_LO,
2709 Off: int32(c.pc + 4),
2710 Siz: 4,
2711 Sym: p.From.Sym,
2712 })
2713 o3 = OP_RRR(c.oprrr(AADDVU), uint32(REGTMP), uint32(REG_R2), uint32(REGTMP))
2714 o4 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(p.To.Reg))
2715
2716 case 59:
2717
2718
2719 v := c.vregoff(&p.From)
2720 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
2721 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(p.To.Reg), uint32(p.To.Reg))
2722 o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
2723 o4 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
2724
2725 case 60:
2726 v := c.vregoff(&p.From)
2727 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
2728 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
2729 o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
2730 o4 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
2731 r := int(p.Reg)
2732 if r == 0 {
2733 r = int(p.To.Reg)
2734 }
2735 o5 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
2736
2737 case 61:
2738 o1 = uint32(c.vregoff(&p.From))
2739 o2 = uint32(c.vregoff(&p.From) >> 32)
2740
2741 case 62:
2742 o1 = OP_RR(c.oprr(p.As), uint32(p.To.Reg), uint32(p.RegTo2))
2743
2744 case 64:
2745 sa := p.From.Offset - 1
2746 if sa > 3 {
2747 c.ctxt.Diag("The shift amount is too large.")
2748 }
2749 r := p.GetFrom3().Reg
2750 o1 = OP_2IRRR(c.opirrr(p.As), uint32(sa), uint32(r), uint32(p.Reg), uint32(p.To.Reg))
2751
2752 case 65:
2753 o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(p.To.Reg))
2754 c.cursym.AddRel(c.ctxt, obj.Reloc{
2755 Type: objabi.R_LOONG64_GOT_HI,
2756 Off: int32(c.pc),
2757 Siz: 4,
2758 Sym: p.From.Sym,
2759 })
2760 o2 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(p.To.Reg), uint32(p.To.Reg))
2761 c.cursym.AddRel(c.ctxt, obj.Reloc{
2762 Type: objabi.R_LOONG64_GOT_LO,
2763 Off: int32(c.pc + 4),
2764 Siz: 4,
2765 Sym: p.From.Sym,
2766 })
2767
2768 case 66:
2769 rk := p.From.Reg
2770 rj := p.To.Reg
2771 rd := p.RegTo2
2772
2773
2774
2775 if rd == rj || rd == rk {
2776 c.ctxt.Diag("illegal register combination: %v\n", p)
2777 }
2778 o1 = OP_RRR(atomicInst[p.As], uint32(rk), uint32(rj), uint32(rd))
2779
2780 case 67:
2781 v := c.vregoff(&p.From)
2782 o1 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(0), uint32(p.To.Reg))
2783
2784 case 68:
2785 v := c.vregoff(&p.From)
2786 contype := c.aclass(&p.From)
2787 switch contype {
2788 default:
2789 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
2790 o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
2791 case C_DCON20S_20:
2792 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
2793 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
2794 case C_DCON12_12S:
2795 o1 = OP_12IRR(c.opirr(AADDV), uint32(v), uint32(0), uint32(p.To.Reg))
2796 o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
2797 case C_DCON20S_12S, C_DCON20S_0:
2798 o1 = OP_12IRR(c.opirr(AADD), uint32(v), uint32(0), uint32(p.To.Reg))
2799 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
2800 case C_DCON12_12U:
2801 o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(p.To.Reg))
2802 o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
2803 case C_DCON20S_12U:
2804 o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(p.To.Reg))
2805 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
2806 }
2807
2808 case 69:
2809 v := c.vregoff(&p.From)
2810 contype := c.aclass(&p.From)
2811 switch contype {
2812 default:
2813 o1 = OP_12IRR(c.opirr(AADD), uint32(v), uint32(0), uint32(p.To.Reg))
2814 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
2815 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
2816 case C_DCON32_20:
2817 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
2818 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
2819 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
2820 case C_DCON12_32S:
2821 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
2822 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(p.To.Reg), uint32(p.To.Reg))
2823 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
2824 case C_DCON20S_32:
2825 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
2826 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(p.To.Reg), uint32(p.To.Reg))
2827 o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
2828 case C_DCON32_12U:
2829 o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(p.To.Reg))
2830 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
2831 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
2832 }
2833
2834 case 70:
2835 v := c.vregoff(&p.From)
2836 r := int(p.Reg)
2837 if r == 0 {
2838 r = int(p.To.Reg)
2839 }
2840 o1 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(0), uint32(REGTMP))
2841 o2 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
2842
2843 case 71:
2844 v := c.vregoff(&p.From)
2845 r := int(p.Reg)
2846 if r == 0 {
2847 r = int(p.To.Reg)
2848 }
2849 contype := c.aclass(&p.From)
2850 switch contype {
2851 default:
2852 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
2853 o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
2854 case C_DCON20S_20:
2855 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
2856 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
2857 case C_DCON12_12S:
2858 o1 = OP_12IRR(c.opirr(AADDV), uint32(v), uint32(0), uint32(REGTMP))
2859 o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
2860 case C_DCON20S_12S, C_DCON20S_0:
2861 o1 = OP_12IRR(c.opirr(AADD), uint32(v), uint32(0), uint32(REGTMP))
2862 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
2863 case C_DCON12_12U:
2864 o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(REGTMP))
2865 o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
2866 case C_DCON20S_12U:
2867 o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(REGTMP))
2868 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
2869 }
2870 o3 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
2871
2872 case 72:
2873 v := c.vregoff(&p.From)
2874 r := int(p.Reg)
2875 if r == 0 {
2876 r = int(p.To.Reg)
2877 }
2878 contype := c.aclass(&p.From)
2879 switch contype {
2880 default:
2881 o1 = OP_12IRR(c.opirr(AADD), uint32(v), uint32(0), uint32(REGTMP))
2882 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
2883 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
2884 case C_DCON32_20:
2885 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
2886 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
2887 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
2888 case C_DCON12_32S:
2889 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
2890 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
2891 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
2892 case C_DCON20S_32:
2893 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
2894 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
2895 o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
2896 case C_DCON32_12U:
2897 o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(REGTMP))
2898 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
2899 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
2900 }
2901 o4 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
2902 }
2903
2904 out[0] = o1
2905 out[1] = o2
2906 out[2] = o3
2907 out[3] = o4
2908 out[4] = o5
2909 }
2910
2911
2912 func (c *ctxt0) checkoperand(p *obj.Prog, operand uint32, mask uint32) {
2913 if (operand & ^mask) != 0 {
2914 c.ctxt.Diag("operand out of range 0 to %d: %v", mask, p)
2915 }
2916 }
2917
2918
2919 func (c *ctxt0) checkindex(p *obj.Prog, index uint32, mask uint32) {
2920 if (index & ^mask) != 0 {
2921 c.ctxt.Diag("register element index out of range 0 to %d: %v", mask, p)
2922 }
2923 }
2924
2925 func (c *ctxt0) vregoff(a *obj.Addr) int64 {
2926 c.instoffset = 0
2927 c.aclass(a)
2928 return c.instoffset
2929 }
2930
2931 func (c *ctxt0) regoff(a *obj.Addr) int32 {
2932 return int32(c.vregoff(a))
2933 }
2934
2935 func (c *ctxt0) oprrrr(a obj.As) uint32 {
2936 switch a {
2937 case AFMADDF:
2938 return 0x81 << 20
2939 case AFMADDD:
2940 return 0x82 << 20
2941 case AFMSUBF:
2942 return 0x85 << 20
2943 case AFMSUBD:
2944 return 0x86 << 20
2945 case AFNMADDF:
2946 return 0x89 << 20
2947 case AFNMADDD:
2948 return 0x8a << 20
2949 case AFNMSUBF:
2950 return 0x8d << 20
2951 case AFNMSUBD:
2952 return 0x8e << 20
2953 }
2954
2955 c.ctxt.Diag("bad rrrr opcode %v", a)
2956 return 0
2957 }
2958
2959 func (c *ctxt0) oprrr(a obj.As) uint32 {
2960 switch a {
2961 case AADD:
2962 return 0x20 << 15
2963 case AADDU:
2964 return 0x20 << 15
2965 case ASGT:
2966 return 0x24 << 15
2967 case ASGTU:
2968 return 0x25 << 15
2969 case AMASKEQZ:
2970 return 0x26 << 15
2971 case AMASKNEZ:
2972 return 0x27 << 15
2973 case AAND:
2974 return 0x29 << 15
2975 case AOR:
2976 return 0x2a << 15
2977 case AXOR:
2978 return 0x2b << 15
2979 case AORN:
2980 return 0x2c << 15
2981 case AANDN:
2982 return 0x2d << 15
2983 case ASUB:
2984 return 0x22 << 15
2985 case ASUBU, ANEGW:
2986 return 0x22 << 15
2987 case ANOR:
2988 return 0x28 << 15
2989 case ASLL:
2990 return 0x2e << 15
2991 case ASRL:
2992 return 0x2f << 15
2993 case ASRA:
2994 return 0x30 << 15
2995 case AROTR:
2996 return 0x36 << 15
2997 case ASLLV:
2998 return 0x31 << 15
2999 case ASRLV:
3000 return 0x32 << 15
3001 case ASRAV:
3002 return 0x33 << 15
3003 case AROTRV:
3004 return 0x37 << 15
3005 case AADDV:
3006 return 0x21 << 15
3007 case AADDVU:
3008 return 0x21 << 15
3009 case ASUBV:
3010 return 0x23 << 15
3011 case ASUBVU, ANEGV:
3012 return 0x23 << 15
3013
3014 case AMUL:
3015 return 0x38 << 15
3016 case AMULU:
3017 return 0x38 << 15
3018 case AMULH:
3019 return 0x39 << 15
3020 case AMULHU:
3021 return 0x3a << 15
3022 case AMULV:
3023 return 0x3b << 15
3024 case AMULVU:
3025 return 0x3b << 15
3026 case AMULHV:
3027 return 0x3c << 15
3028 case AMULHVU:
3029 return 0x3d << 15
3030 case ADIV:
3031 return 0x40 << 15
3032 case ADIVU:
3033 return 0x42 << 15
3034 case ADIVV:
3035 return 0x44 << 15
3036 case ADIVVU:
3037 return 0x46 << 15
3038 case AREM:
3039 return 0x41 << 15
3040 case AREMU:
3041 return 0x43 << 15
3042 case AREMV:
3043 return 0x45 << 15
3044 case AREMVU:
3045 return 0x47 << 15
3046 case ACRCWBW:
3047 return 0x48 << 15
3048 case ACRCWHW:
3049 return 0x49 << 15
3050 case ACRCWWW:
3051 return 0x4a << 15
3052 case ACRCWVW:
3053 return 0x4b << 15
3054 case ACRCCWBW:
3055 return 0x4c << 15
3056 case ACRCCWHW:
3057 return 0x4d << 15
3058 case ACRCCWWW:
3059 return 0x4e << 15
3060 case ACRCCWVW:
3061 return 0x4f << 15
3062 case AJMP:
3063 return 0x13 << 26
3064 case AJAL:
3065 return (0x13 << 26) | 1
3066
3067 case ADIVF:
3068 return 0x20d << 15
3069 case ADIVD:
3070 return 0x20e << 15
3071 case AMULF:
3072 return 0x209 << 15
3073 case AMULD:
3074 return 0x20a << 15
3075 case ASUBF:
3076 return 0x205 << 15
3077 case ASUBD:
3078 return 0x206 << 15
3079 case AADDF:
3080 return 0x201 << 15
3081 case AADDD:
3082 return 0x202 << 15
3083 case ACMPEQF:
3084 return 0x0c1<<20 | 0x4<<15
3085 case ACMPEQD:
3086 return 0x0c2<<20 | 0x4<<15
3087 case ACMPGED:
3088 return 0x0c2<<20 | 0x7<<15
3089 case ACMPGEF:
3090 return 0x0c1<<20 | 0x7<<15
3091 case ACMPGTD:
3092 return 0x0c2<<20 | 0x3<<15
3093 case ACMPGTF:
3094 return 0x0c1<<20 | 0x3<<15
3095 case AFMINF:
3096 return 0x215 << 15
3097 case AFMIND:
3098 return 0x216 << 15
3099 case AFMAXF:
3100 return 0x211 << 15
3101 case AFMAXD:
3102 return 0x212 << 15
3103 case AFMAXAF:
3104 return 0x219 << 15
3105 case AFMAXAD:
3106 return 0x21a << 15
3107 case AFMINAF:
3108 return 0x21d << 15
3109 case AFMINAD:
3110 return 0x21e << 15
3111 case AFSCALEBF:
3112 return 0x221 << 15
3113 case AFSCALEBD:
3114 return 0x222 << 15
3115 case AFCOPYSGF:
3116 return 0x225 << 15
3117 case AFCOPYSGD:
3118 return 0x226 << 15
3119 case -AMOVB:
3120 return 0x07000 << 15
3121 case -AMOVH:
3122 return 0x07008 << 15
3123 case -AMOVW:
3124 return 0x07010 << 15
3125 case -AMOVV:
3126 return 0x07018 << 15
3127 case -AMOVBU:
3128 return 0x07040 << 15
3129 case -AMOVHU:
3130 return 0x07048 << 15
3131 case -AMOVWU:
3132 return 0x07050 << 15
3133 case AMOVB:
3134 return 0x07020 << 15
3135 case AMOVH:
3136 return 0x07028 << 15
3137 case AMOVW:
3138 return 0x07030 << 15
3139 case AMOVV:
3140 return 0x07038 << 15
3141 case -AMOVF:
3142 return 0x07060 << 15
3143 case -AMOVD:
3144 return 0x07068 << 15
3145 case AMOVF:
3146 return 0x07070 << 15
3147 case AMOVD:
3148 return 0x07078 << 15
3149 case -AVMOVQ:
3150 return 0x07080 << 15
3151 case -AXVMOVQ:
3152 return 0x07090 << 15
3153 case AVMOVQ:
3154 return 0x07088 << 15
3155 case AXVMOVQ:
3156 return 0x07098 << 15
3157 case AVSEQB:
3158 return 0x0e000 << 15
3159 case AXVSEQB:
3160 return 0x0e800 << 15
3161 case AVSEQH:
3162 return 0x0e001 << 15
3163 case AXVSEQH:
3164 return 0x0e801 << 15
3165 case AVSEQW:
3166 return 0x0e002 << 15
3167 case AXVSEQW:
3168 return 0x0e802 << 15
3169 case AVSEQV:
3170 return 0x0e003 << 15
3171 case AXVSEQV:
3172 return 0x0e803 << 15
3173 case AVANDV:
3174 return 0x0E24C << 15
3175 case AVORV:
3176 return 0x0E24D << 15
3177 case AVXORV:
3178 return 0x0E24E << 15
3179 case AVNORV:
3180 return 0x0E24F << 15
3181 case AVANDNV:
3182 return 0x0E250 << 15
3183 case AVORNV:
3184 return 0x0E251 << 15
3185 case AXVANDV:
3186 return 0x0EA4C << 15
3187 case AXVORV:
3188 return 0x0EA4D << 15
3189 case AXVXORV:
3190 return 0x0EA4E << 15
3191 case AXVNORV:
3192 return 0x0EA4F << 15
3193 case AXVANDNV:
3194 return 0x0EA50 << 15
3195 case AXVORNV:
3196 return 0x0EA51 << 15
3197 case AVDIVB:
3198 return 0xe1c0 << 15
3199 case AVDIVH:
3200 return 0xe1c1 << 15
3201 case AVDIVW:
3202 return 0xe1c2 << 15
3203 case AVDIVV:
3204 return 0xe1c3 << 15
3205 case AVMODB:
3206 return 0xe1c4 << 15
3207 case AVMODH:
3208 return 0xe1c5 << 15
3209 case AVMODW:
3210 return 0xe1c6 << 15
3211 case AVMODV:
3212 return 0xe1c7 << 15
3213 case AVDIVBU:
3214 return 0xe1c8 << 15
3215 case AVDIVHU:
3216 return 0xe1c9 << 15
3217 case AVDIVWU:
3218 return 0xe1ca << 15
3219 case AVDIVVU:
3220 return 0xe1cb << 15
3221 case AVMODBU:
3222 return 0xe1cc << 15
3223 case AVMODHU:
3224 return 0xe1cd << 15
3225 case AVMODWU:
3226 return 0xe1ce << 15
3227 case AVMODVU:
3228 return 0xe1cf << 15
3229 case AXVDIVB:
3230 return 0xe9c0 << 15
3231 case AXVDIVH:
3232 return 0xe9c1 << 15
3233 case AXVDIVW:
3234 return 0xe9c2 << 15
3235 case AXVDIVV:
3236 return 0xe9c3 << 15
3237 case AXVMODB:
3238 return 0xe9c4 << 15
3239 case AXVMODH:
3240 return 0xe9c5 << 15
3241 case AXVMODW:
3242 return 0xe9c6 << 15
3243 case AXVMODV:
3244 return 0xe9c7 << 15
3245 case AXVDIVBU:
3246 return 0xe9c8 << 15
3247 case AXVDIVHU:
3248 return 0xe9c9 << 15
3249 case AXVDIVWU:
3250 return 0xe9ca << 15
3251 case AXVDIVVU:
3252 return 0xe9cb << 15
3253 case AXVMODBU:
3254 return 0xe9cc << 15
3255 case AXVMODHU:
3256 return 0xe9cd << 15
3257 case AXVMODWU:
3258 return 0xe9ce << 15
3259 case AXVMODVU:
3260 return 0xe9cf << 15
3261 case AVMULWEVHB:
3262 return 0xe120 << 15
3263 case AVMULWEVWH:
3264 return 0xe121 << 15
3265 case AVMULWEVVW:
3266 return 0xe122 << 15
3267 case AVMULWEVQV:
3268 return 0xe123 << 15
3269 case AVMULWODHB:
3270 return 0xe124 << 15
3271 case AVMULWODWH:
3272 return 0xe125 << 15
3273 case AVMULWODVW:
3274 return 0xe126 << 15
3275 case AVMULWODQV:
3276 return 0xe127 << 15
3277 case AVMULWEVHBU:
3278 return 0xe130 << 15
3279 case AVMULWEVWHU:
3280 return 0xe131 << 15
3281 case AVMULWEVVWU:
3282 return 0xe132 << 15
3283 case AVMULWEVQVU:
3284 return 0xe133 << 15
3285 case AVMULWODHBU:
3286 return 0xe134 << 15
3287 case AVMULWODWHU:
3288 return 0xe135 << 15
3289 case AVMULWODVWU:
3290 return 0xe136 << 15
3291 case AVMULWODQVU:
3292 return 0xe137 << 15
3293 case AVMULWEVHBUB:
3294 return 0xe140 << 15
3295 case AVMULWEVWHUH:
3296 return 0xe141 << 15
3297 case AVMULWEVVWUW:
3298 return 0xe142 << 15
3299 case AVMULWEVQVUV:
3300 return 0xe143 << 15
3301 case AVMULWODHBUB:
3302 return 0xe144 << 15
3303 case AVMULWODWHUH:
3304 return 0xe145 << 15
3305 case AVMULWODVWUW:
3306 return 0xe146 << 15
3307 case AVMULWODQVUV:
3308 return 0xe147 << 15
3309 case AXVMULWEVHB:
3310 return 0xe920 << 15
3311 case AXVMULWEVWH:
3312 return 0xe921 << 15
3313 case AXVMULWEVVW:
3314 return 0xe922 << 15
3315 case AXVMULWEVQV:
3316 return 0xe923 << 15
3317 case AXVMULWODHB:
3318 return 0xe924 << 15
3319 case AXVMULWODWH:
3320 return 0xe925 << 15
3321 case AXVMULWODVW:
3322 return 0xe926 << 15
3323 case AXVMULWODQV:
3324 return 0xe927 << 15
3325 case AXVMULWEVHBU:
3326 return 0xe930 << 15
3327 case AXVMULWEVWHU:
3328 return 0xe931 << 15
3329 case AXVMULWEVVWU:
3330 return 0xe932 << 15
3331 case AXVMULWEVQVU:
3332 return 0xe933 << 15
3333 case AXVMULWODHBU:
3334 return 0xe934 << 15
3335 case AXVMULWODWHU:
3336 return 0xe935 << 15
3337 case AXVMULWODVWU:
3338 return 0xe936 << 15
3339 case AXVMULWODQVU:
3340 return 0xe937 << 15
3341 case AXVMULWEVHBUB:
3342 return 0xe940 << 15
3343 case AXVMULWEVWHUH:
3344 return 0xe941 << 15
3345 case AXVMULWEVVWUW:
3346 return 0xe942 << 15
3347 case AXVMULWEVQVUV:
3348 return 0xe943 << 15
3349 case AXVMULWODHBUB:
3350 return 0xe944 << 15
3351 case AXVMULWODWHUH:
3352 return 0xe945 << 15
3353 case AXVMULWODVWUW:
3354 return 0xe946 << 15
3355 case AXVMULWODQVUV:
3356 return 0xe947 << 15
3357 case AVSLLB:
3358 return 0xe1d0 << 15
3359 case AVSLLH:
3360 return 0xe1d1 << 15
3361 case AVSLLW:
3362 return 0xe1d2 << 15
3363 case AVSLLV:
3364 return 0xe1d3 << 15
3365 case AVSRLB:
3366 return 0xe1d4 << 15
3367 case AVSRLH:
3368 return 0xe1d5 << 15
3369 case AVSRLW:
3370 return 0xe1d6 << 15
3371 case AVSRLV:
3372 return 0xe1d7 << 15
3373 case AVSRAB:
3374 return 0xe1d8 << 15
3375 case AVSRAH:
3376 return 0xe1d9 << 15
3377 case AVSRAW:
3378 return 0xe1da << 15
3379 case AVSRAV:
3380 return 0xe1db << 15
3381 case AVROTRB:
3382 return 0xe1dc << 15
3383 case AVROTRH:
3384 return 0xe1dd << 15
3385 case AVROTRW:
3386 return 0xe1de << 15
3387 case AVROTRV:
3388 return 0xe1df << 15
3389 case AXVSLLB:
3390 return 0xe9d0 << 15
3391 case AXVSLLH:
3392 return 0xe9d1 << 15
3393 case AXVSLLW:
3394 return 0xe9d2 << 15
3395 case AXVSLLV:
3396 return 0xe9d3 << 15
3397 case AXVSRLB:
3398 return 0xe9d4 << 15
3399 case AXVSRLH:
3400 return 0xe9d5 << 15
3401 case AXVSRLW:
3402 return 0xe9d6 << 15
3403 case AXVSRLV:
3404 return 0xe9d7 << 15
3405 case AXVSRAB:
3406 return 0xe9d8 << 15
3407 case AXVSRAH:
3408 return 0xe9d9 << 15
3409 case AXVSRAW:
3410 return 0xe9da << 15
3411 case AXVSRAV:
3412 return 0xe9db << 15
3413 case AXVROTRB:
3414 return 0xe9dc << 15
3415 case AXVROTRH:
3416 return 0xe9dd << 15
3417 case AXVROTRW:
3418 return 0xe9de << 15
3419 case AXVROTRV:
3420 return 0xe9df << 15
3421 case AVADDB:
3422 return 0xe014 << 15
3423 case AVADDH:
3424 return 0xe015 << 15
3425 case AVADDW:
3426 return 0xe016 << 15
3427 case AVADDV:
3428 return 0xe017 << 15
3429 case AVADDQ:
3430 return 0xe25a << 15
3431 case AVSUBB:
3432 return 0xe018 << 15
3433 case AVSUBH:
3434 return 0xe019 << 15
3435 case AVSUBW:
3436 return 0xe01a << 15
3437 case AVSUBV:
3438 return 0xe01b << 15
3439 case AVSUBQ:
3440 return 0xe25b << 15
3441 case AXVADDB:
3442 return 0xe814 << 15
3443 case AXVADDH:
3444 return 0xe815 << 15
3445 case AXVADDW:
3446 return 0xe816 << 15
3447 case AXVADDV:
3448 return 0xe817 << 15
3449 case AXVADDQ:
3450 return 0xea5a << 15
3451 case AXVSUBB:
3452 return 0xe818 << 15
3453 case AXVSUBH:
3454 return 0xe819 << 15
3455 case AXVSUBW:
3456 return 0xe81a << 15
3457 case AXVSUBV:
3458 return 0xe81b << 15
3459 case AXVSUBQ:
3460 return 0xea5b << 15
3461 case AVILVLB:
3462 return 0xe234 << 15
3463 case AVILVLH:
3464 return 0xe235 << 15
3465 case AVILVLW:
3466 return 0xe236 << 15
3467 case AVILVLV:
3468 return 0xe237 << 15
3469 case AVILVHB:
3470 return 0xe238 << 15
3471 case AVILVHH:
3472 return 0xe239 << 15
3473 case AVILVHW:
3474 return 0xe23a << 15
3475 case AVILVHV:
3476 return 0xe23b << 15
3477 case AXVILVLB:
3478 return 0xea34 << 15
3479 case AXVILVLH:
3480 return 0xea35 << 15
3481 case AXVILVLW:
3482 return 0xea36 << 15
3483 case AXVILVLV:
3484 return 0xea37 << 15
3485 case AXVILVHB:
3486 return 0xea38 << 15
3487 case AXVILVHH:
3488 return 0xea39 << 15
3489 case AXVILVHW:
3490 return 0xea3a << 15
3491 case AXVILVHV:
3492 return 0xea3b << 15
3493 case AVMULB:
3494 return 0xe108 << 15
3495 case AVMULH:
3496 return 0xe109 << 15
3497 case AVMULW:
3498 return 0xe10a << 15
3499 case AVMULV:
3500 return 0xe10b << 15
3501 case AVMUHB:
3502 return 0xe10c << 15
3503 case AVMUHH:
3504 return 0xe10d << 15
3505 case AVMUHW:
3506 return 0xe10e << 15
3507 case AVMUHV:
3508 return 0xe10f << 15
3509 case AVMUHBU:
3510 return 0xe110 << 15
3511 case AVMUHHU:
3512 return 0xe111 << 15
3513 case AVMUHWU:
3514 return 0xe112 << 15
3515 case AVMUHVU:
3516 return 0xe113 << 15
3517 case AXVMULB:
3518 return 0xe908 << 15
3519 case AXVMULH:
3520 return 0xe909 << 15
3521 case AXVMULW:
3522 return 0xe90a << 15
3523 case AXVMULV:
3524 return 0xe90b << 15
3525 case AXVMUHB:
3526 return 0xe90c << 15
3527 case AXVMUHH:
3528 return 0xe90d << 15
3529 case AXVMUHW:
3530 return 0xe90e << 15
3531 case AXVMUHV:
3532 return 0xe90f << 15
3533 case AXVMUHBU:
3534 return 0xe910 << 15
3535 case AXVMUHHU:
3536 return 0xe911 << 15
3537 case AXVMUHWU:
3538 return 0xe912 << 15
3539 case AXVMUHVU:
3540 return 0xe913 << 15
3541 case AVADDF:
3542 return 0xe261 << 15
3543 case AVADDD:
3544 return 0xe262 << 15
3545 case AVSUBF:
3546 return 0xe265 << 15
3547 case AVSUBD:
3548 return 0xe266 << 15
3549 case AVMULF:
3550 return 0xe271 << 15
3551 case AVMULD:
3552 return 0xe272 << 15
3553 case AVDIVF:
3554 return 0xe275 << 15
3555 case AVDIVD:
3556 return 0xe276 << 15
3557 case AXVADDF:
3558 return 0xea61 << 15
3559 case AXVADDD:
3560 return 0xea62 << 15
3561 case AXVSUBF:
3562 return 0xea65 << 15
3563 case AXVSUBD:
3564 return 0xea66 << 15
3565 case AXVMULF:
3566 return 0xea71 << 15
3567 case AXVMULD:
3568 return 0xea72 << 15
3569 case AXVDIVF:
3570 return 0xea75 << 15
3571 case AXVDIVD:
3572 return 0xea76 << 15
3573 case AVBITCLRB:
3574 return 0xe218 << 15
3575 case AVBITCLRH:
3576 return 0xe219 << 15
3577 case AVBITCLRW:
3578 return 0xe21a << 15
3579 case AVBITCLRV:
3580 return 0xe21b << 15
3581 case AVBITSETB:
3582 return 0xe21c << 15
3583 case AVBITSETH:
3584 return 0xe21d << 15
3585 case AVBITSETW:
3586 return 0xe21e << 15
3587 case AVBITSETV:
3588 return 0xe21f << 15
3589 case AVBITREVB:
3590 return 0xe220 << 15
3591 case AVBITREVH:
3592 return 0xe221 << 15
3593 case AVBITREVW:
3594 return 0xe222 << 15
3595 case AVBITREVV:
3596 return 0xe223 << 15
3597 case AXVBITCLRB:
3598 return 0xea18 << 15
3599 case AXVBITCLRH:
3600 return 0xea19 << 15
3601 case AXVBITCLRW:
3602 return 0xea1a << 15
3603 case AXVBITCLRV:
3604 return 0xea1b << 15
3605 case AXVBITSETB:
3606 return 0xea1c << 15
3607 case AXVBITSETH:
3608 return 0xea1d << 15
3609 case AXVBITSETW:
3610 return 0xea1e << 15
3611 case AXVBITSETV:
3612 return 0xea1f << 15
3613 case AXVBITREVB:
3614 return 0xea20 << 15
3615 case AXVBITREVH:
3616 return 0xea21 << 15
3617 case AXVBITREVW:
3618 return 0xea22 << 15
3619 case AXVBITREVV:
3620 return 0xea23 << 15
3621 }
3622
3623 if a < 0 {
3624 c.ctxt.Diag("bad rrr opcode -%v", -a)
3625 } else {
3626 c.ctxt.Diag("bad rrr opcode %v", a)
3627 }
3628 return 0
3629 }
3630
3631 func (c *ctxt0) oprr(a obj.As) uint32 {
3632 switch a {
3633 case ACLOW:
3634 return 0x4 << 10
3635 case ACLZW:
3636 return 0x5 << 10
3637 case ACTOW:
3638 return 0x6 << 10
3639 case ACTZW:
3640 return 0x7 << 10
3641 case ACLOV:
3642 return 0x8 << 10
3643 case ACLZV:
3644 return 0x9 << 10
3645 case ACTOV:
3646 return 0xa << 10
3647 case ACTZV:
3648 return 0xb << 10
3649 case AREVB2H:
3650 return 0xc << 10
3651 case AREVB4H:
3652 return 0xd << 10
3653 case AREVB2W:
3654 return 0xe << 10
3655 case AREVBV:
3656 return 0xf << 10
3657 case AREVH2W:
3658 return 0x10 << 10
3659 case AREVHV:
3660 return 0x11 << 10
3661 case ABITREV4B:
3662 return 0x12 << 10
3663 case ABITREV8B:
3664 return 0x13 << 10
3665 case ABITREVW:
3666 return 0x14 << 10
3667 case ABITREVV:
3668 return 0x15 << 10
3669 case AEXTWH:
3670 return 0x16 << 10
3671 case AEXTWB:
3672 return 0x17 << 10
3673 case ACPUCFG:
3674 return 0x1b << 10
3675 case ARDTIMELW:
3676 return 0x18 << 10
3677 case ARDTIMEHW:
3678 return 0x19 << 10
3679 case ARDTIMED:
3680 return 0x1a << 10
3681 case ATRUNCFV:
3682 return 0x46a9 << 10
3683 case ATRUNCDV:
3684 return 0x46aa << 10
3685 case ATRUNCFW:
3686 return 0x46a1 << 10
3687 case ATRUNCDW:
3688 return 0x46a2 << 10
3689 case AMOVFV:
3690 return 0x46c9 << 10
3691 case AMOVDV:
3692 return 0x46ca << 10
3693 case AMOVVF:
3694 return 0x4746 << 10
3695 case AMOVVD:
3696 return 0x474a << 10
3697 case AMOVFW:
3698 return 0x46c1 << 10
3699 case AMOVDW:
3700 return 0x46c2 << 10
3701 case AMOVWF:
3702 return 0x4744 << 10
3703 case AMOVDF:
3704 return 0x4646 << 10
3705 case AMOVWD:
3706 return 0x4748 << 10
3707 case AMOVFD:
3708 return 0x4649 << 10
3709 case AABSF:
3710 return 0x4501 << 10
3711 case AABSD:
3712 return 0x4502 << 10
3713 case AMOVF:
3714 return 0x4525 << 10
3715 case AMOVD:
3716 return 0x4526 << 10
3717 case ANEGF:
3718 return 0x4505 << 10
3719 case ANEGD:
3720 return 0x4506 << 10
3721 case ASQRTF:
3722 return 0x4511 << 10
3723 case ASQRTD:
3724 return 0x4512 << 10
3725 case AFLOGBF:
3726 return 0x4509 << 10
3727 case AFLOGBD:
3728 return 0x450a << 10
3729 case AFCLASSF:
3730 return 0x450d << 10
3731 case AFCLASSD:
3732 return 0x450e << 10
3733 case AFFINTFW:
3734 return 0x4744 << 10
3735 case AFFINTFV:
3736 return 0x4746 << 10
3737 case AFFINTDW:
3738 return 0x4748 << 10
3739 case AFFINTDV:
3740 return 0x474a << 10
3741 case AFTINTWF:
3742 return 0x46c1 << 10
3743 case AFTINTWD:
3744 return 0x46c2 << 10
3745 case AFTINTVF:
3746 return 0x46c9 << 10
3747 case AFTINTVD:
3748 return 0x46ca << 10
3749 case AFTINTRMWF:
3750 return 0x4681 << 10
3751 case AFTINTRMWD:
3752 return 0x4682 << 10
3753 case AFTINTRMVF:
3754 return 0x4689 << 10
3755 case AFTINTRMVD:
3756 return 0x468a << 10
3757 case AFTINTRPWF:
3758 return 0x4691 << 10
3759 case AFTINTRPWD:
3760 return 0x4692 << 10
3761 case AFTINTRPVF:
3762 return 0x4699 << 10
3763 case AFTINTRPVD:
3764 return 0x469a << 10
3765 case AFTINTRZWF:
3766 return 0x46a1 << 10
3767 case AFTINTRZWD:
3768 return 0x46a2 << 10
3769 case AFTINTRZVF:
3770 return 0x46a9 << 10
3771 case AFTINTRZVD:
3772 return 0x46aa << 10
3773 case AFTINTRNEWF:
3774 return 0x46b1 << 10
3775 case AFTINTRNEWD:
3776 return 0x46b2 << 10
3777 case AFTINTRNEVF:
3778 return 0x46b9 << 10
3779 case AFTINTRNEVD:
3780 return 0x46ba << 10
3781 case AVPCNTB:
3782 return 0x1ca708 << 10
3783 case AVPCNTH:
3784 return 0x1ca709 << 10
3785 case AVPCNTW:
3786 return 0x1ca70a << 10
3787 case AVPCNTV:
3788 return 0x1ca70b << 10
3789 case AXVPCNTB:
3790 return 0x1da708 << 10
3791 case AXVPCNTH:
3792 return 0x1da709 << 10
3793 case AXVPCNTW:
3794 return 0x1da70a << 10
3795 case AXVPCNTV:
3796 return 0x1da70b << 10
3797 case AVFSQRTF:
3798 return 0x1ca739 << 10
3799 case AVFSQRTD:
3800 return 0x1ca73a << 10
3801 case AVFRECIPF:
3802 return 0x1ca73d << 10
3803 case AVFRECIPD:
3804 return 0x1ca73e << 10
3805 case AVFRSQRTF:
3806 return 0x1ca741 << 10
3807 case AVFRSQRTD:
3808 return 0x1ca742 << 10
3809 case AXVFSQRTF:
3810 return 0x1da739 << 10
3811 case AXVFSQRTD:
3812 return 0x1da73a << 10
3813 case AXVFRECIPF:
3814 return 0x1da73d << 10
3815 case AXVFRECIPD:
3816 return 0x1da73e << 10
3817 case AXVFRSQRTF:
3818 return 0x1da741 << 10
3819 case AXVFRSQRTD:
3820 return 0x1da742 << 10
3821 case AVNEGB:
3822 return 0x1ca70c << 10
3823 case AVNEGH:
3824 return 0x1ca70d << 10
3825 case AVNEGW:
3826 return 0x1ca70e << 10
3827 case AVNEGV:
3828 return 0x1ca70f << 10
3829 case AXVNEGB:
3830 return 0x1da70c << 10
3831 case AXVNEGH:
3832 return 0x1da70d << 10
3833 case AXVNEGW:
3834 return 0x1da70e << 10
3835 case AXVNEGV:
3836 return 0x1da70f << 10
3837 case AVFRINTRNEF:
3838 return 0x1ca75d << 10
3839 case AVFRINTRNED:
3840 return 0x1ca75e << 10
3841 case AVFRINTRZF:
3842 return 0x1ca759 << 10
3843 case AVFRINTRZD:
3844 return 0x1ca75a << 10
3845 case AVFRINTRPF:
3846 return 0x1ca755 << 10
3847 case AVFRINTRPD:
3848 return 0x1ca756 << 10
3849 case AVFRINTRMF:
3850 return 0x1ca751 << 10
3851 case AVFRINTRMD:
3852 return 0x1ca752 << 10
3853 case AVFRINTF:
3854 return 0x1ca74d << 10
3855 case AVFRINTD:
3856 return 0x1ca74e << 10
3857 case AXVFRINTRNEF:
3858 return 0x1da75d << 10
3859 case AXVFRINTRNED:
3860 return 0x1da75e << 10
3861 case AXVFRINTRZF:
3862 return 0x1da759 << 10
3863 case AXVFRINTRZD:
3864 return 0x1da75a << 10
3865 case AXVFRINTRPF:
3866 return 0x1da755 << 10
3867 case AXVFRINTRPD:
3868 return 0x1da756 << 10
3869 case AXVFRINTRMF:
3870 return 0x1da751 << 10
3871 case AXVFRINTRMD:
3872 return 0x1da752 << 10
3873 case AXVFRINTF:
3874 return 0x1da74d << 10
3875 case AXVFRINTD:
3876 return 0x1da74e << 10
3877 case AVFCLASSF:
3878 return 0x1ca735 << 10
3879 case AVFCLASSD:
3880 return 0x1ca736 << 10
3881 case AXVFCLASSF:
3882 return 0x1da735 << 10
3883 case AXVFCLASSD:
3884 return 0x1da736 << 10
3885 case AVSETEQV:
3886 return 0x1ca726<<10 | 0x0<<3
3887 case AVSETNEV:
3888 return 0x1ca727<<10 | 0x0<<3
3889 case AVSETANYEQB:
3890 return 0x1ca728<<10 | 0x0<<3
3891 case AVSETANYEQH:
3892 return 0x1ca729<<10 | 0x0<<3
3893 case AVSETANYEQW:
3894 return 0x1ca72a<<10 | 0x0<<3
3895 case AVSETANYEQV:
3896 return 0x1ca72b<<10 | 0x0<<3
3897 case AVSETALLNEB:
3898 return 0x1ca72c<<10 | 0x0<<3
3899 case AVSETALLNEH:
3900 return 0x1ca72d<<10 | 0x0<<3
3901 case AVSETALLNEW:
3902 return 0x1ca72e<<10 | 0x0<<3
3903 case AVSETALLNEV:
3904 return 0x1ca72f<<10 | 0x0<<3
3905 case AXVSETEQV:
3906 return 0x1da726<<10 | 0x0<<3
3907 case AXVSETNEV:
3908 return 0x1da727<<10 | 0x0<<3
3909 case AXVSETANYEQB:
3910 return 0x1da728<<10 | 0x0<<3
3911 case AXVSETANYEQH:
3912 return 0x1da729<<10 | 0x0<<3
3913 case AXVSETANYEQW:
3914 return 0x1da72a<<10 | 0x0<<3
3915 case AXVSETANYEQV:
3916 return 0x1da72b<<10 | 0x0<<3
3917 case AXVSETALLNEB:
3918 return 0x1da72c<<10 | 0x0<<3
3919 case AXVSETALLNEH:
3920 return 0x1da72d<<10 | 0x0<<3
3921 case AXVSETALLNEW:
3922 return 0x1da72e<<10 | 0x0<<3
3923 case AXVSETALLNEV:
3924 return 0x1da72f<<10 | 0x0<<3
3925 }
3926
3927 c.ctxt.Diag("bad rr opcode %v", a)
3928 return 0
3929 }
3930
3931 func (c *ctxt0) opi(a obj.As) uint32 {
3932 switch a {
3933 case ASYSCALL:
3934 return 0x56 << 15
3935 case ABREAK:
3936 return 0x54 << 15
3937 case ADBAR:
3938 return 0x70e4 << 15
3939 }
3940
3941 c.ctxt.Diag("bad ic opcode %v", a)
3942
3943 return 0
3944 }
3945
3946 func (c *ctxt0) opir(a obj.As) uint32 {
3947 switch a {
3948 case ALU12IW:
3949 return 0x0a << 25
3950 case ALU32ID:
3951 return 0x0b << 25
3952 case APCALAU12I:
3953 return 0x0d << 25
3954 case APCADDU12I:
3955 return 0x0e << 25
3956 }
3957 return 0
3958 }
3959
3960 func (c *ctxt0) opirr(a obj.As) uint32 {
3961 switch a {
3962 case AADD, AADDU:
3963 return 0x00a << 22
3964 case ASGT:
3965 return 0x008 << 22
3966 case ASGTU:
3967 return 0x009 << 22
3968 case AAND:
3969 return 0x00d << 22
3970 case AOR:
3971 return 0x00e << 22
3972 case ALU52ID:
3973 return 0x00c << 22
3974 case AXOR:
3975 return 0x00f << 22
3976 case ASLL:
3977 return 0x00081 << 15
3978 case ASRL:
3979 return 0x00089 << 15
3980 case ASRA:
3981 return 0x00091 << 15
3982 case AROTR:
3983 return 0x00099 << 15
3984 case AADDV:
3985 return 0x00b << 22
3986 case AADDVU:
3987 return 0x00b << 22
3988
3989 case AJMP:
3990 return 0x14 << 26
3991 case AJAL,
3992 obj.ADUFFZERO,
3993 obj.ADUFFCOPY:
3994 return 0x15 << 26
3995
3996 case AJIRL:
3997 return 0x13 << 26
3998 case ABLTU:
3999 return 0x1a << 26
4000 case ABLT, ABLTZ, ABGTZ:
4001 return 0x18 << 26
4002 case ABGEU:
4003 return 0x1b << 26
4004 case ABGE, ABGEZ, ABLEZ:
4005 return 0x19 << 26
4006 case -ABEQ:
4007 return 0x10 << 26
4008 case -ABNE:
4009 return 0x11 << 26
4010 case ABEQ:
4011 return 0x16 << 26
4012 case ABNE:
4013 return 0x17 << 26
4014 case ABFPT:
4015 return 0x12<<26 | 0x1<<8
4016 case ABFPF:
4017 return 0x12<<26 | 0x0<<8
4018 case APRELDX:
4019 return 0x07058 << 15
4020 case AMOVB,
4021 AMOVBU:
4022 return 0x0a4 << 22
4023 case AMOVH,
4024 AMOVHU:
4025 return 0x0a5 << 22
4026 case AMOVW,
4027 AMOVWU:
4028 return 0x0a6 << 22
4029 case AMOVV:
4030 return 0x0a7 << 22
4031 case AMOVF:
4032 return 0x0ad << 22
4033 case AMOVD:
4034 return 0x0af << 22
4035 case -AMOVB:
4036 return 0x0a0 << 22
4037 case -AMOVBU:
4038 return 0x0a8 << 22
4039 case -AMOVH:
4040 return 0x0a1 << 22
4041 case -AMOVHU:
4042 return 0x0a9 << 22
4043 case -AMOVW:
4044 return 0x0a2 << 22
4045 case -AMOVWU:
4046 return 0x0aa << 22
4047 case -AMOVV:
4048 return 0x0a3 << 22
4049 case -AMOVF:
4050 return 0x0ac << 22
4051 case -AMOVD:
4052 return 0x0ae << 22
4053 case -AVMOVQ:
4054 return 0x0b0 << 22
4055 case -AXVMOVQ:
4056 return 0x0b2 << 22
4057 case AVMOVQ:
4058 return 0x0b1 << 22
4059 case AXVMOVQ:
4060 return 0x0b3 << 22
4061 case ASLLV:
4062 return 0x0041 << 16
4063 case ASRLV:
4064 return 0x0045 << 16
4065 case ASRAV:
4066 return 0x0049 << 16
4067 case AROTRV:
4068 return 0x004d << 16
4069 case -ALL:
4070 return 0x020 << 24
4071 case -ALLV:
4072 return 0x022 << 24
4073 case ASC:
4074 return 0x021 << 24
4075 case ASCV:
4076 return 0x023 << 24
4077 case AVANDB:
4078 return 0x1CF4 << 18
4079 case AVORB:
4080 return 0x1CF5 << 18
4081 case AVXORB:
4082 return 0x1CF6 << 18
4083 case AVNORB:
4084 return 0x1CF7 << 18
4085 case AXVANDB:
4086 return 0x1DF4 << 18
4087 case AXVORB:
4088 return 0x1DF5 << 18
4089 case AXVXORB:
4090 return 0x1DF6 << 18
4091 case AXVNORB:
4092 return 0x1DF7 << 18
4093 case AVSEQB:
4094 return 0x0E500 << 15
4095 case AVSEQH:
4096 return 0x0E501 << 15
4097 case AVSEQW:
4098 return 0x0E502 << 15
4099 case AVSEQV:
4100 return 0x0E503 << 15
4101 case AXVSEQB:
4102 return 0x0ED00 << 15
4103 case AXVSEQH:
4104 return 0x0ED01 << 15
4105 case AXVSEQW:
4106 return 0x0ED02 << 15
4107 case AXVSEQV:
4108 return 0x0ED03 << 15
4109 case AVROTRB:
4110 return 0x1ca8<<18 | 0x1<<13
4111 case AVROTRH:
4112 return 0x1ca8<<18 | 0x1<<14
4113 case AVROTRW:
4114 return 0x1ca8<<18 | 0x1<<15
4115 case AVROTRV:
4116 return 0x1ca8<<18 | 0x1<<16
4117 case AXVROTRB:
4118 return 0x1da8<<18 | 0x1<<13
4119 case AXVROTRH:
4120 return 0x1da8<<18 | 0x1<<14
4121 case AXVROTRW:
4122 return 0x1da8<<18 | 0x1<<15
4123 case AXVROTRV:
4124 return 0x1da8<<18 | 0x1<<16
4125 case AVSLLB:
4126 return 0x1ccb<<18 | 0x1<<13
4127 case AVSLLH:
4128 return 0x1ccb<<18 | 0x1<<14
4129 case AVSLLW:
4130 return 0x1ccb<<18 | 0x1<<15
4131 case AVSLLV:
4132 return 0x1ccb<<18 | 0x1<<16
4133 case AVSRLB:
4134 return 0x1ccc<<18 | 0x1<<13
4135 case AVSRLH:
4136 return 0x1ccc<<18 | 0x1<<14
4137 case AVSRLW:
4138 return 0x1ccc<<18 | 0x1<<15
4139 case AVSRLV:
4140 return 0x1ccc<<18 | 0x1<<16
4141 case AVSRAB:
4142 return 0x1ccd<<18 | 0x1<<13
4143 case AVSRAH:
4144 return 0x1ccd<<18 | 0x1<<14
4145 case AVSRAW:
4146 return 0x1ccd<<18 | 0x1<<15
4147 case AVSRAV:
4148 return 0x1ccd<<18 | 0x1<<16
4149 case AXVSLLB:
4150 return 0x1dcb<<18 | 0x1<<13
4151 case AXVSLLH:
4152 return 0x1dcb<<18 | 0x1<<14
4153 case AXVSLLW:
4154 return 0x1dcb<<18 | 0x1<<15
4155 case AXVSLLV:
4156 return 0x1dcb<<18 | 0x1<<16
4157 case AXVSRLB:
4158 return 0x1dcc<<18 | 0x1<<13
4159 case AXVSRLH:
4160 return 0x1dcc<<18 | 0x1<<14
4161 case AXVSRLW:
4162 return 0x1dcc<<18 | 0x1<<15
4163 case AXVSRLV:
4164 return 0x1dcc<<18 | 0x1<<16
4165 case AXVSRAB:
4166 return 0x1dcd<<18 | 0x1<<13
4167 case AXVSRAH:
4168 return 0x1dcd<<18 | 0x1<<14
4169 case AXVSRAW:
4170 return 0x1dcd<<18 | 0x1<<15
4171 case AXVSRAV:
4172 return 0x1dcd<<18 | 0x1<<16
4173 case AVADDBU:
4174 return 0xe514 << 15
4175 case AVADDHU:
4176 return 0xe515 << 15
4177 case AVADDWU:
4178 return 0xe516 << 15
4179 case AVADDVU:
4180 return 0xe517 << 15
4181 case AVSUBBU:
4182 return 0xe518 << 15
4183 case AVSUBHU:
4184 return 0xe519 << 15
4185 case AVSUBWU:
4186 return 0xe51a << 15
4187 case AVSUBVU:
4188 return 0xe51b << 15
4189 case AXVADDBU:
4190 return 0xed14 << 15
4191 case AXVADDHU:
4192 return 0xed15 << 15
4193 case AXVADDWU:
4194 return 0xed16 << 15
4195 case AXVADDVU:
4196 return 0xed17 << 15
4197 case AXVSUBBU:
4198 return 0xed18 << 15
4199 case AXVSUBHU:
4200 return 0xed19 << 15
4201 case AXVSUBWU:
4202 return 0xed1a << 15
4203 case AXVSUBVU:
4204 return 0xed1b << 15
4205 case AVSHUF4IB:
4206 return 0x1ce4 << 18
4207 case AVSHUF4IH:
4208 return 0x1ce5 << 18
4209 case AVSHUF4IW:
4210 return 0x1ce6 << 18
4211 case AVSHUF4IV:
4212 return 0x1ce7 << 18
4213 case AXVSHUF4IB:
4214 return 0x1de4 << 18
4215 case AXVSHUF4IH:
4216 return 0x1de5 << 18
4217 case AXVSHUF4IW:
4218 return 0x1de6 << 18
4219 case AXVSHUF4IV:
4220 return 0x1de7 << 18
4221 case AVBITCLRB:
4222 return 0x1CC4<<18 | 0x1<<13
4223 case AVBITCLRH:
4224 return 0x1CC4<<18 | 0x1<<14
4225 case AVBITCLRW:
4226 return 0x1CC4<<18 | 0x1<<15
4227 case AVBITCLRV:
4228 return 0x1CC4<<18 | 0x1<<16
4229 case AVBITSETB:
4230 return 0x1CC5<<18 | 0x1<<13
4231 case AVBITSETH:
4232 return 0x1CC5<<18 | 0x1<<14
4233 case AVBITSETW:
4234 return 0x1CC5<<18 | 0x1<<15
4235 case AVBITSETV:
4236 return 0x1CC5<<18 | 0x1<<16
4237 case AVBITREVB:
4238 return 0x1CC6<<18 | 0x1<<13
4239 case AVBITREVH:
4240 return 0x1CC6<<18 | 0x1<<14
4241 case AVBITREVW:
4242 return 0x1CC6<<18 | 0x1<<15
4243 case AVBITREVV:
4244 return 0x1CC6<<18 | 0x1<<16
4245 case AXVBITCLRB:
4246 return 0x1DC4<<18 | 0x1<<13
4247 case AXVBITCLRH:
4248 return 0x1DC4<<18 | 0x1<<14
4249 case AXVBITCLRW:
4250 return 0x1DC4<<18 | 0x1<<15
4251 case AXVBITCLRV:
4252 return 0x1DC4<<18 | 0x1<<16
4253 case AXVBITSETB:
4254 return 0x1DC5<<18 | 0x1<<13
4255 case AXVBITSETH:
4256 return 0x1DC5<<18 | 0x1<<14
4257 case AXVBITSETW:
4258 return 0x1DC5<<18 | 0x1<<15
4259 case AXVBITSETV:
4260 return 0x1DC5<<18 | 0x1<<16
4261 case AXVBITREVB:
4262 return 0x1DC6<<18 | 0x1<<13
4263 case AXVBITREVH:
4264 return 0x1DC6<<18 | 0x1<<14
4265 case AXVBITREVW:
4266 return 0x1DC6<<18 | 0x1<<15
4267 case AXVBITREVV:
4268 return 0x1DC6<<18 | 0x1<<16
4269 }
4270
4271 if a < 0 {
4272 c.ctxt.Diag("bad irr opcode -%v", -a)
4273 } else {
4274 c.ctxt.Diag("bad irr opcode %v", a)
4275 }
4276 return 0
4277 }
4278
4279 func (c *ctxt0) opirrr(a obj.As) uint32 {
4280 switch a {
4281 case AALSLW:
4282 return 0x2 << 17
4283 case AALSLWU:
4284 return 0x3 << 17
4285 case AALSLV:
4286 return 0x16 << 17
4287 }
4288
4289 return 0
4290 }
4291
4292 func (c *ctxt0) opirir(a obj.As) uint32 {
4293 switch a {
4294 case ABSTRINSW:
4295 return 0x3<<21 | 0x0<<15
4296 case ABSTRINSV:
4297 return 0x2 << 22
4298 case ABSTRPICKW:
4299 return 0x3<<21 | 0x1<<15
4300 case ABSTRPICKV:
4301 return 0x3 << 22
4302 }
4303
4304 return 0
4305 }
4306
4307 func (c *ctxt0) opiir(a obj.As) uint32 {
4308 switch a {
4309 case APRELD:
4310 return 0x0AB << 22
4311 }
4312
4313 return 0
4314 }
4315
4316 func (c *ctxt0) specialFpMovInst(a obj.As, fclass int, tclass int) uint32 {
4317 switch a {
4318 case AMOVV:
4319 switch fclass {
4320 case C_REG:
4321 switch tclass {
4322 case C_FREG:
4323 return 0x452a << 10
4324 case C_FCCREG:
4325 return 0x4536 << 10
4326 case C_FCSRREG:
4327 return 0x4530 << 10
4328 }
4329 case C_FREG:
4330 switch tclass {
4331 case C_REG:
4332 return 0x452e << 10
4333 case C_FCCREG:
4334 return 0x4534 << 10
4335 }
4336 case C_FCCREG:
4337 switch tclass {
4338 case C_REG:
4339 return 0x4537 << 10
4340 case C_FREG:
4341 return 0x4535 << 10
4342 }
4343 case C_FCSRREG:
4344 switch tclass {
4345 case C_REG:
4346 return 0x4532 << 10
4347 }
4348 }
4349
4350 case AMOVW:
4351 switch fclass {
4352 case C_REG:
4353 switch tclass {
4354 case C_FREG:
4355 return 0x4529 << 10
4356 }
4357 case C_FREG:
4358 switch tclass {
4359 case C_REG:
4360 return 0x452d << 10
4361 }
4362 }
4363 }
4364
4365 c.ctxt.Diag("bad class combination: %s %s,%s\n", a, fclass, tclass)
4366
4367 return 0
4368 }
4369
4370 func (c *ctxt0) specialLsxMovInst(a obj.As, fReg, tReg int16, offset_flag bool) (op_code, index_mask uint32) {
4371 farng := (fReg >> EXT_TYPE_SHIFT) & EXT_TYPE_MASK
4372 tarng := (tReg >> EXT_TYPE_SHIFT) & EXT_TYPE_MASK
4373 fclass := c.rclass(fReg)
4374 tclass := c.rclass(tReg)
4375
4376 switch fclass | (tclass << 16) {
4377 case C_REG | (C_ELEM << 16):
4378
4379 switch a {
4380 case AVMOVQ:
4381 switch tarng {
4382 case ARNG_B:
4383 return (0x01CBAE << 14), 0xf
4384 case ARNG_H:
4385 return (0x03975E << 13), 0x7
4386 case ARNG_W:
4387 return (0x072EBE << 12), 0x3
4388 case ARNG_V:
4389 return (0x0E5D7E << 11), 0x1
4390 }
4391 case AXVMOVQ:
4392 switch tarng {
4393 case ARNG_W:
4394 return (0x03B75E << 13), 0x7
4395 case ARNG_V:
4396 return (0x076EBE << 12), 0x3
4397 }
4398 }
4399
4400 case C_ELEM | (C_REG << 16):
4401
4402 switch a {
4403 case AVMOVQ:
4404 switch farng {
4405 case ARNG_B:
4406 return (0x01CBBE << 14), 0xf
4407 case ARNG_H:
4408 return (0x03977E << 13), 0x7
4409 case ARNG_W:
4410 return (0x072EFE << 12), 0x3
4411 case ARNG_V:
4412 return (0x0E5DFE << 11), 0x1
4413 case ARNG_BU:
4414 return (0x01CBCE << 14), 0xf
4415 case ARNG_HU:
4416 return (0x03979E << 13), 0x7
4417 case ARNG_WU:
4418 return (0x072F3E << 12), 0x3
4419 case ARNG_VU:
4420 return (0x0E5E7E << 11), 0x1
4421 }
4422 case AXVMOVQ:
4423 switch farng {
4424 case ARNG_W:
4425 return (0x03B77E << 13), 0x7
4426 case ARNG_V:
4427 return (0x076EFE << 12), 0x3
4428 case ARNG_WU:
4429 return (0x03B79E << 13), 0x7
4430 case ARNG_VU:
4431 return (0x076F3E << 12), 0x3
4432 }
4433 }
4434
4435 case C_REG | (C_ARNG << 16):
4436 switch {
4437 case offset_flag:
4438
4439 switch a {
4440 case AVMOVQ:
4441 switch tarng {
4442 case ARNG_16B:
4443 return (0xC2 << 22), 0x0
4444 case ARNG_8H:
4445 return (0x182 << 21), 0x0
4446 case ARNG_4W:
4447 return (0x302 << 20), 0x0
4448 case ARNG_2V:
4449 return (0x602 << 19), 0x0
4450 }
4451 case AXVMOVQ:
4452 switch tarng {
4453 case ARNG_32B:
4454 return (0xCA << 22), 0x0
4455 case ARNG_16H:
4456 return (0x192 << 21), 0x0
4457 case ARNG_8W:
4458 return (0x322 << 20), 0x0
4459 case ARNG_4V:
4460 return (0x642 << 19), 0x0
4461 }
4462 }
4463 default:
4464
4465 switch a {
4466 case AVMOVQ:
4467 switch tarng {
4468 case ARNG_16B:
4469 return (0x1CA7C0 << 10), 0x0
4470 case ARNG_8H:
4471 return (0x1CA7C1 << 10), 0x0
4472 case ARNG_4W:
4473 return (0x1CA7C2 << 10), 0x0
4474 case ARNG_2V:
4475 return (0x1CA7C3 << 10), 0x0
4476 }
4477 case AXVMOVQ:
4478 switch tarng {
4479 case ARNG_32B:
4480 return (0x1DA7C0 << 10), 0x0
4481 case ARNG_16H:
4482 return (0x1DA7C1 << 10), 0x0
4483 case ARNG_8W:
4484 return (0x1DA7C2 << 10), 0x0
4485 case ARNG_4V:
4486 return (0x1DA7C3 << 10), 0x0
4487 }
4488 }
4489 }
4490
4491 case C_XREG | (C_ARNG << 16):
4492
4493 switch a {
4494 case AVMOVQ:
4495 return 0, 0
4496 case AXVMOVQ:
4497 switch tarng {
4498 case ARNG_32B:
4499 return (0x1DC1C0 << 10), 0x0
4500 case ARNG_16H:
4501 return (0x1DC1E0 << 10), 0x0
4502 case ARNG_8W:
4503 return (0x1DC1F0 << 10), 0x0
4504 case ARNG_4V:
4505 return (0x1DC1F8 << 10), 0x0
4506 case ARNG_2Q:
4507 return (0x1DC1FC << 10), 0x0
4508 }
4509 }
4510
4511 case C_XREG | (C_ELEM << 16):
4512
4513 switch a {
4514 case AVMOVQ:
4515 return 0, 0
4516 case AXVMOVQ:
4517 switch tarng {
4518 case ARNG_W:
4519 return (0x03B7FE << 13), 0x7
4520 case ARNG_V:
4521 return (0x076FFE << 12), 0x3
4522 }
4523 }
4524
4525 case C_ELEM | (C_XREG << 16):
4526
4527 switch a {
4528 case AVMOVQ:
4529 return 0, 0
4530 case AXVMOVQ:
4531 switch farng {
4532 case ARNG_W:
4533 return (0x03B81E << 13), 0x7
4534 case ARNG_V:
4535 return (0x07703E << 12), 0x3
4536 }
4537 }
4538
4539 case C_ELEM | (C_ARNG << 16):
4540
4541 switch a {
4542 case AVMOVQ:
4543 switch int32(farng) | (int32(tarng) << 16) {
4544 case int32(ARNG_B) | (int32(ARNG_16B) << 16):
4545 return (0x01CBDE << 14), 0xf
4546 case int32(ARNG_H) | (int32(ARNG_8H) << 16):
4547 return (0x0397BE << 13), 0x7
4548 case int32(ARNG_W) | (int32(ARNG_4W) << 16):
4549 return (0x072F7E << 12), 0x3
4550 case int32(ARNG_V) | (int32(ARNG_2V) << 16):
4551 return (0x0E5EFE << 11), 0x1
4552 }
4553 case AXVMOVQ:
4554 return 0, 0
4555 }
4556 }
4557
4558 return 0, 0
4559 }
4560
4561 func vshift(a obj.As) bool {
4562 switch a {
4563 case ASLLV,
4564 ASRLV,
4565 ASRAV,
4566 AROTRV:
4567 return true
4568 }
4569 return false
4570 }
4571
View as plain text