a.out.go

     1  // Copyright 2022 The Go Authors. All rights reserved.
     2  // Use of this source code is governed by a BSD-style
     3  // license that can be found in the LICENSE file.
     4  
     5  package loong64
     6  
     7  import (
     8  	"cmd/internal/obj"
     9  )
    10  
    11  //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p loong64
    12  
    13  const (
    14  	NSNAME = 8
    15  	NSYM   = 50
    16  	NREG   = 32 // number of general registers
    17  	NFREG  = 32 // number of floating point registers
    18  	NVREG  = 32 // number of LSX registers
    19  	NXREG  = 32 // number of LASX registers
    20  )
    21  
    22  const (
    23  	REG_R0 = obj.RBaseLOONG64 + iota // must be a multiple of 32
    24  	REG_R1
    25  	REG_R2
    26  	REG_R3
    27  	REG_R4
    28  	REG_R5
    29  	REG_R6
    30  	REG_R7
    31  	REG_R8
    32  	REG_R9
    33  	REG_R10
    34  	REG_R11
    35  	REG_R12
    36  	REG_R13
    37  	REG_R14
    38  	REG_R15
    39  	REG_R16
    40  	REG_R17
    41  	REG_R18
    42  	REG_R19
    43  	REG_R20
    44  	REG_R21
    45  	REG_R22
    46  	REG_R23
    47  	REG_R24
    48  	REG_R25
    49  	REG_R26
    50  	REG_R27
    51  	REG_R28
    52  	REG_R29
    53  	REG_R30
    54  	REG_R31
    55  
    56  	REG_F0 // must be a multiple of 32
    57  	REG_F1
    58  	REG_F2
    59  	REG_F3
    60  	REG_F4
    61  	REG_F5
    62  	REG_F6
    63  	REG_F7
    64  	REG_F8
    65  	REG_F9
    66  	REG_F10
    67  	REG_F11
    68  	REG_F12
    69  	REG_F13
    70  	REG_F14
    71  	REG_F15
    72  	REG_F16
    73  	REG_F17
    74  	REG_F18
    75  	REG_F19
    76  	REG_F20
    77  	REG_F21
    78  	REG_F22
    79  	REG_F23
    80  	REG_F24
    81  	REG_F25
    82  	REG_F26
    83  	REG_F27
    84  	REG_F28
    85  	REG_F29
    86  	REG_F30
    87  	REG_F31
    88  
    89  	REG_FCSR0 // must be a multiple of 32
    90  	REG_FCSR1
    91  	REG_FCSR2
    92  	REG_FCSR3 // only four registers are needed
    93  	REG_FCSR4
    94  	REG_FCSR5
    95  	REG_FCSR6
    96  	REG_FCSR7
    97  	REG_FCSR8
    98  	REG_FCSR9
    99  	REG_FCSR10
   100  	REG_FCSR11
   101  	REG_FCSR12
   102  	REG_FCSR13
   103  	REG_FCSR14
   104  	REG_FCSR15
   105  	REG_FCSR16
   106  	REG_FCSR17
   107  	REG_FCSR18
   108  	REG_FCSR19
   109  	REG_FCSR20
   110  	REG_FCSR21
   111  	REG_FCSR22
   112  	REG_FCSR23
   113  	REG_FCSR24
   114  	REG_FCSR25
   115  	REG_FCSR26
   116  	REG_FCSR27
   117  	REG_FCSR28
   118  	REG_FCSR29
   119  	REG_FCSR30
   120  	REG_FCSR31
   121  
   122  	REG_FCC0 // must be a multiple of 32
   123  	REG_FCC1
   124  	REG_FCC2
   125  	REG_FCC3
   126  	REG_FCC4
   127  	REG_FCC5
   128  	REG_FCC6
   129  	REG_FCC7 // only eight registers are needed
   130  	REG_FCC8
   131  	REG_FCC9
   132  	REG_FCC10
   133  	REG_FCC11
   134  	REG_FCC12
   135  	REG_FCC13
   136  	REG_FCC14
   137  	REG_FCC15
   138  	REG_FCC16
   139  	REG_FCC17
   140  	REG_FCC18
   141  	REG_FCC19
   142  	REG_FCC20
   143  	REG_FCC21
   144  	REG_FCC22
   145  	REG_FCC23
   146  	REG_FCC24
   147  	REG_FCC25
   148  	REG_FCC26
   149  	REG_FCC27
   150  	REG_FCC28
   151  	REG_FCC29
   152  	REG_FCC30
   153  	REG_FCC31
   154  
   155  	// LSX: 128-bit vector register
   156  	REG_V0
   157  	REG_V1
   158  	REG_V2
   159  	REG_V3
   160  	REG_V4
   161  	REG_V5
   162  	REG_V6
   163  	REG_V7
   164  	REG_V8
   165  	REG_V9
   166  	REG_V10
   167  	REG_V11
   168  	REG_V12
   169  	REG_V13
   170  	REG_V14
   171  	REG_V15
   172  	REG_V16
   173  	REG_V17
   174  	REG_V18
   175  	REG_V19
   176  	REG_V20
   177  	REG_V21
   178  	REG_V22
   179  	REG_V23
   180  	REG_V24
   181  	REG_V25
   182  	REG_V26
   183  	REG_V27
   184  	REG_V28
   185  	REG_V29
   186  	REG_V30
   187  	REG_V31
   188  
   189  	// LASX: 256-bit vector register
   190  	REG_X0
   191  	REG_X1
   192  	REG_X2
   193  	REG_X3
   194  	REG_X4
   195  	REG_X5
   196  	REG_X6
   197  	REG_X7
   198  	REG_X8
   199  	REG_X9
   200  	REG_X10
   201  	REG_X11
   202  	REG_X12
   203  	REG_X13
   204  	REG_X14
   205  	REG_X15
   206  	REG_X16
   207  	REG_X17
   208  	REG_X18
   209  	REG_X19
   210  	REG_X20
   211  	REG_X21
   212  	REG_X22
   213  	REG_X23
   214  	REG_X24
   215  	REG_X25
   216  	REG_X26
   217  	REG_X27
   218  	REG_X28
   219  	REG_X29
   220  	REG_X30
   221  	REG_X31
   222  
   223  	REG_SPECIAL = REG_FCSR0
   224  
   225  	REGZERO = REG_R0 // set to zero
   226  	REGLINK = REG_R1
   227  	REGSP   = REG_R3
   228  	REGRT1  = REG_R20 // reserved for runtime, duffzero and duffcopy
   229  	REGRT2  = REG_R21 // reserved for runtime, duffcopy
   230  	REGCTXT = REG_R29 // context for closures
   231  	REGG    = REG_R22 // G in loong64
   232  	REGTMP  = REG_R30 // used by the assembler
   233  	FREGRET = REG_F0  // not use
   234  )
   235  
   236  var LOONG64DWARFRegisters = map[int16]int16{}
   237  
   238  func init() {
   239  	// f assigns dwarfregisters[from:to] = (base):(to-from+base)
   240  	f := func(from, to, base int16) {
   241  		for r := int16(from); r <= to; r++ {
   242  			LOONG64DWARFRegisters[r] = (r - from) + base
   243  		}
   244  	}
   245  	f(REG_R0, REG_R31, 0)
   246  	f(REG_F0, REG_F31, 32)
   247  
   248  	// The lower bits of V and X registers are alias to F registers
   249  	f(REG_V0, REG_V31, 32)
   250  	f(REG_X0, REG_X31, 32)
   251  }
   252  
   253  const (
   254  	BIG = 2046
   255  )
   256  
   257  const (
   258  	// mark flags
   259  	LABEL  = 1 << 0
   260  	LEAF   = 1 << 1
   261  	SYNC   = 1 << 2
   262  	BRANCH = 1 << 3
   263  )
   264  
   265  // Arrangement for Loong64 SIMD instructions
   266  const (
   267  	// arrangement types
   268  	ARNG_32B int16 = iota
   269  	ARNG_16H
   270  	ARNG_8W
   271  	ARNG_4V
   272  	ARNG_2Q
   273  	ARNG_16B
   274  	ARNG_8H
   275  	ARNG_4W
   276  	ARNG_2V
   277  	ARNG_B
   278  	ARNG_H
   279  	ARNG_W
   280  	ARNG_V
   281  	ARNG_BU
   282  	ARNG_HU
   283  	ARNG_WU
   284  	ARNG_VU
   285  )
   286  
   287  // LoongArch64 SIMD extension type
   288  const (
   289  	LSX int16 = iota
   290  	LASX
   291  )
   292  
   293  // bits 0-4 indicates register: Vn or Xn
   294  // bits 5-9 indicates arrangement: <T>
   295  // bits 10 indicates SMID type: 0: LSX, 1: LASX
   296  const (
   297  	REG_ARNG = obj.RBaseLOONG64 + (1 << 10) + (iota << 11) // Vn.<T>
   298  	REG_ELEM                                               // Vn.<T>[index]
   299  	REG_ELEM_END
   300  )
   301  
   302  const (
   303  	EXT_REG_SHIFT = 0
   304  	EXT_REG_MASK  = 0x1f
   305  
   306  	EXT_TYPE_SHIFT = 5
   307  	EXT_TYPE_MASK  = 0x1f
   308  
   309  	EXT_SIMDTYPE_SHIFT = 10
   310  	EXT_SIMDTYPE_MASK  = 0x1
   311  )
   312  
   313  const (
   314  	REG_LAST = REG_ELEM_END // the last defined register
   315  )
   316  
   317  //go:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
   318  const (
   319  	C_NONE = iota
   320  	C_REG
   321  	C_FREG
   322  	C_FCSRREG
   323  	C_FCCREG
   324  	C_VREG
   325  	C_XREG
   326  	C_ARNG // Vn.<T>
   327  	C_ELEM // Vn.<T>[index]
   328  
   329  	C_ZCON
   330  	C_U1CON      // 1 bit unsigned constant
   331  	C_U2CON      // 2 bit unsigned constant
   332  	C_U3CON      // 3 bit unsigned constant
   333  	C_U4CON      // 4 bit unsigned constant
   334  	C_U5CON      // 5 bit unsigned constant
   335  	C_U6CON      // 6 bit unsigned constant
   336  	C_U7CON      // 7 bit unsigned constant
   337  	C_U8CON      // 8 bit unsigned constant
   338  	C_S5CON      // 5 bit signed constant
   339  	C_US12CON    // same as C_S12CON, increase the priority of C_S12CON in special cases.
   340  	C_UU12CON    // same as C_U12CON, increase the priority of C_U12CON in special cases.
   341  	C_S12CON     // 12 bit signed constant, -0x800 < v <= 0x7ff
   342  	C_U12CON     // 12 bit unsigned constant, 0 < v <= 0xfff
   343  	C_12CON      // 12 bit signed constant, or 12 bit unsigned constant
   344  	C_S13CON20_0 // 13 bit signed constant, low 12 bits 0
   345  	C_S13CON     // 13 bit signed constant
   346  	C_U13CON20_0 // 13 bit unsigned constant, low 12 bits 0
   347  	C_U13CON     // 13 bit unsigned constant
   348  	C_13CON      // 13 bit signed constant, or 13 bit unsigned constant
   349  	C_U15CON     // 15 bit unsigned constant
   350  	C_U15CON20_0 // 15 bit unsigned constant, low 12 bits 0
   351  	C_32CON20_0  // 32 bit signed, low 12 bits 0
   352  	C_32CON      // other 32 bit signed
   353  
   354  	// 64 bit signed, lo32 bits 0, hi20 bits are not 0, hi12 bits can
   355  	// be obtained by sign extension of the hi20 bits.
   356  	C_DCON20S_0
   357  	// 64 bit signed, lo52 bits 0, hi12 bits are not 0.
   358  	C_DCON12_0
   359  	// 64 bit signed, lo32 bits 0, hi32 bits are not 0.
   360  	C_DCON32_0
   361  	// 64 bit signed, lo12 bits 0, lo20 bits are not 0, hi20 bits can be
   362  	// obtained by sign extension of the lo20 bits, other bits are not 0.
   363  	C_DCON12_20S
   364  	// 64 bit signed, lo12 bits 0, hi20 bits are not 0, hi12 bits can be
   365  	// obtained by sign extension of the hi20 bits, other bits are not 0.
   366  	C_DCON20S_20
   367  	// 64 bit signed, lo12 bits 0, other bits are not 0.
   368  	C_DCON32_20
   369  	// 64 bit signed, lo12 bits are not 0, 12~51 bits can be obtained
   370  	// by sign extension of the lo12 bits, other bits are not 0.
   371  	C_DCON12_12S
   372  	// 64 bit signed, hi20 bits and lo12 bits are not 0, hi12 bits can
   373  	// be obtained by sign extension of the hi20 bits, lo20 bits can
   374  	// be obtained by sign extension of the lo12 bits.
   375  	C_DCON20S_12S
   376  	// 64 bit signed, lo12 bits are not 0, lo20 bits can be obtained by sign
   377  	// extension of the lo12 bits, other bits are not 0.
   378  	C_DCON32_12S
   379  	// 64 bit signed, lo20 and lo12 bits are not 0, hi20 bits can be obtained by sign
   380  	// extension of the lo20 bits. other bits are not 0.
   381  	C_DCON12_32S
   382  	// 64 bit signed, hi20 bits are not 0, hi12 bits can be obtained by sign
   383  	// extension of the hi20 bits, lo32 bits are not 0.
   384  	C_DCON20S_32
   385  	// 64 bit signed, 12~51 bits 0, other bits are not 0.
   386  	C_DCON12_12U
   387  	// 64 bit signed, lo20 bits 0, hi20 bits are not 0, hi12 bits can be
   388  	// obtained by sign extension of the hi20 bits, lo12 bits are not 0.
   389  	C_DCON20S_12U
   390  	// 64 bit signed, lo20 bits 0, other bits are not 0.
   391  	C_DCON32_12U
   392  	// other 64
   393  	C_DCON
   394  
   395  	C_SACON   // $n(REG) where n <= int12
   396  	C_LACON   // $n(REG) where int12 < n <= int32
   397  	C_DACON   // $n(REG) where int32 < n
   398  	C_EXTADDR // external symbol address
   399  	C_BRAN
   400  	C_SAUTO
   401  	C_LAUTO
   402  	C_ZOREG
   403  	C_SOREG
   404  	C_LOREG
   405  	C_ROFF // register offset
   406  	C_ADDR
   407  	C_TLS_LE
   408  	C_TLS_IE
   409  	C_GOTADDR
   410  	C_TEXTSIZE
   411  
   412  	C_GOK
   413  	C_NCLASS // must be the last
   414  )
   415  
   416  const (
   417  	AABSD = obj.ABaseLoong64 + obj.A_ARCHSPECIFIC + iota
   418  	AABSF
   419  	AADD
   420  	AADDD
   421  	AADDF
   422  	AADDU
   423  
   424  	AADDW
   425  	AAND
   426  	ABEQ
   427  	ABGEZ
   428  	ABLEZ
   429  	ABGTZ
   430  	ABLTZ
   431  	ABFPF
   432  	ABFPT
   433  
   434  	ABNE
   435  	ABREAK
   436  
   437  	ACMPEQD
   438  	ACMPEQF
   439  
   440  	ACMPGED // ACMPGED -> fcmp.sle.d
   441  	ACMPGEF // ACMPGEF -> fcmp.sle.s
   442  	ACMPGTD // ACMPGTD -> fcmp.slt.d
   443  	ACMPGTF // ACMPGTF -> fcmp.slt.s
   444  
   445  	ALU12IW
   446  	ALU32ID
   447  	ALU52ID
   448  	APCALAU12I
   449  	APCADDU12I
   450  	AJIRL
   451  	ABGE
   452  	ABLT
   453  	ABLTU
   454  	ABGEU
   455  
   456  	ADIV
   457  	ADIVD
   458  	ADIVF
   459  	ADIVU
   460  	ADIVW
   461  
   462  	ALL
   463  	ALLV
   464  
   465  	ALUI
   466  
   467  	AMOVB
   468  	AMOVBU
   469  
   470  	AMOVD
   471  	AMOVDF
   472  	AMOVDW
   473  	AMOVF
   474  	AMOVFD
   475  	AMOVFW
   476  
   477  	AMOVH
   478  	AMOVHU
   479  	AMOVW
   480  
   481  	AMOVWD
   482  	AMOVWF
   483  
   484  	AMUL
   485  	AMULD
   486  	AMULF
   487  	AMULU
   488  	AMULH
   489  	AMULHU
   490  	AMULW
   491  	ANEGD
   492  	ANEGF
   493  
   494  	ANEGW
   495  	ANEGV
   496  
   497  	ANOOP // hardware nop
   498  	ANOR
   499  	AOR
   500  	AREM
   501  	AREMU
   502  
   503  	ARFE
   504  
   505  	ASC
   506  	ASCV
   507  
   508  	ASGT
   509  	ASGTU
   510  
   511  	ASLL
   512  	ASQRTD
   513  	ASQRTF
   514  	ASRA
   515  	ASRL
   516  	AROTR
   517  	ASUB
   518  	ASUBD
   519  	ASUBF
   520  
   521  	ASUBU
   522  	ASUBW
   523  	ADBAR
   524  	ASYSCALL
   525  
   526  	ATEQ
   527  	ATNE
   528  
   529  	AWORD
   530  
   531  	AXOR
   532  
   533  	AMASKEQZ
   534  	AMASKNEZ
   535  
   536  	// 64-bit
   537  	AMOVV
   538  
   539  	ASLLV
   540  	ASRAV
   541  	ASRLV
   542  	AROTRV
   543  	ADIVV
   544  	ADIVVU
   545  
   546  	AREMV
   547  	AREMVU
   548  
   549  	AMULV
   550  	AMULVU
   551  	AMULHV
   552  	AMULHVU
   553  	AADDV
   554  	AADDVU
   555  	ASUBV
   556  	ASUBVU
   557  
   558  	// 64-bit FP
   559  	ATRUNCFV
   560  	ATRUNCDV
   561  	ATRUNCFW
   562  	ATRUNCDW
   563  
   564  	AMOVWU
   565  	AMOVFV
   566  	AMOVDV
   567  	AMOVVF
   568  	AMOVVD
   569  
   570  	// 2.2.1.3
   571  	AALSLW
   572  	AALSLWU
   573  	AALSLV
   574  
   575  	// 2.2.1.8
   576  	AORN
   577  	AANDN
   578  
   579  	// 2.2.7. Atomic Memory Access Instructions
   580  	AAMSWAPB
   581  	AAMSWAPH
   582  	AAMSWAPW
   583  	AAMSWAPV
   584  	AAMCASB
   585  	AAMCASH
   586  	AAMCASW
   587  	AAMCASV
   588  	AAMADDW
   589  	AAMADDV
   590  	AAMANDW
   591  	AAMANDV
   592  	AAMORW
   593  	AAMORV
   594  	AAMXORW
   595  	AAMXORV
   596  	AAMMAXW
   597  	AAMMAXV
   598  	AAMMINW
   599  	AAMMINV
   600  	AAMMAXWU
   601  	AAMMAXVU
   602  	AAMMINWU
   603  	AAMMINVU
   604  	AAMSWAPDBB
   605  	AAMSWAPDBH
   606  	AAMSWAPDBW
   607  	AAMSWAPDBV
   608  	AAMCASDBB
   609  	AAMCASDBH
   610  	AAMCASDBW
   611  	AAMCASDBV
   612  	AAMADDDBW
   613  	AAMADDDBV
   614  	AAMANDDBW
   615  	AAMANDDBV
   616  	AAMORDBW
   617  	AAMORDBV
   618  	AAMXORDBW
   619  	AAMXORDBV
   620  	AAMMAXDBW
   621  	AAMMAXDBV
   622  	AAMMINDBW
   623  	AAMMINDBV
   624  	AAMMAXDBWU
   625  	AAMMAXDBVU
   626  	AAMMINDBWU
   627  	AAMMINDBVU
   628  
   629  	// 2.2.3.1
   630  	AEXTWB
   631  	AEXTWH
   632  
   633  	// 2.2.3.2
   634  	ACLOW
   635  	ACLOV
   636  	ACLZW
   637  	ACLZV
   638  	ACTOW
   639  	ACTOV
   640  	ACTZW
   641  	ACTZV
   642  
   643  	// 2.2.3.4
   644  	AREVBV
   645  	AREVB2W
   646  	AREVB4H
   647  	AREVB2H
   648  
   649  	// 2.2.3.5
   650  	AREVH2W
   651  	AREVHV
   652  
   653  	// 2.2.3.6
   654  	ABITREV4B
   655  	ABITREV8B
   656  
   657  	// 2.2.3.7
   658  	ABITREVW
   659  	ABITREVV
   660  
   661  	// 2.2.3.8
   662  	ABSTRINSW
   663  	ABSTRINSV
   664  
   665  	// 2.2.3.9
   666  	ABSTRPICKW
   667  	ABSTRPICKV
   668  
   669  	// 2.2.5.4. Prefetch Instructions
   670  	APRELD
   671  	APRELDX
   672  
   673  	// 2.2.9. CRC Check Instructions
   674  	ACRCWBW
   675  	ACRCWHW
   676  	ACRCWWW
   677  	ACRCWVW
   678  	ACRCCWBW
   679  	ACRCCWHW
   680  	ACRCCWWW
   681  	ACRCCWVW
   682  
   683  	// 2.2.10. Other Miscellaneous Instructions
   684  	ARDTIMELW
   685  	ARDTIMEHW
   686  	ARDTIMED
   687  	ACPUCFG
   688  
   689  	// 3.2.1.2
   690  	AFMADDF
   691  	AFMADDD
   692  	AFMSUBF
   693  	AFMSUBD
   694  	AFNMADDF
   695  	AFNMADDD
   696  	AFNMSUBF
   697  	AFNMSUBD
   698  
   699  	// 3.2.1.3
   700  	AFMINF
   701  	AFMIND
   702  	AFMAXF
   703  	AFMAXD
   704  
   705  	// 3.2.1.4
   706  	AFMAXAF
   707  	AFMAXAD
   708  	AFMINAF
   709  	AFMINAD
   710  
   711  	// 3.2.1.7
   712  	AFCOPYSGF
   713  	AFCOPYSGD
   714  	AFSCALEBF
   715  	AFSCALEBD
   716  	AFLOGBF
   717  	AFLOGBD
   718  
   719  	// 3.2.1.8
   720  	AFCLASSF
   721  	AFCLASSD
   722  
   723  	// 3.2.3.2
   724  	AFFINTFW
   725  	AFFINTFV
   726  	AFFINTDW
   727  	AFFINTDV
   728  	AFTINTWF
   729  	AFTINTWD
   730  	AFTINTVF
   731  	AFTINTVD
   732  
   733  	// 3.2.3.3
   734  	AFTINTRPWF
   735  	AFTINTRPWD
   736  	AFTINTRPVF
   737  	AFTINTRPVD
   738  	AFTINTRMWF
   739  	AFTINTRMWD
   740  	AFTINTRMVF
   741  	AFTINTRMVD
   742  	AFTINTRZWF
   743  	AFTINTRZWD
   744  	AFTINTRZVF
   745  	AFTINTRZVD
   746  	AFTINTRNEWF
   747  	AFTINTRNEWD
   748  	AFTINTRNEVF
   749  	AFTINTRNEVD
   750  
   751  	// 3.2.4.2
   752  	AFSEL
   753  
   754  	// LSX and LASX memory access instructions
   755  	AVMOVQ
   756  	AXVMOVQ
   757  
   758  	// LSX and LASX arithmetic instructions
   759  	AVADDB
   760  	AVADDH
   761  	AVADDW
   762  	AVADDV
   763  	AVADDQ
   764  	AXVADDB
   765  	AXVADDH
   766  	AXVADDW
   767  	AXVADDV
   768  	AXVADDQ
   769  	AVSUBB
   770  	AVSUBH
   771  	AVSUBW
   772  	AVSUBV
   773  	AVSUBQ
   774  	AXVSUBB
   775  	AXVSUBH
   776  	AXVSUBW
   777  	AXVSUBV
   778  	AXVSUBQ
   779  	AVADDBU
   780  	AVADDHU
   781  	AVADDWU
   782  	AVADDVU
   783  	AVSUBBU
   784  	AVSUBHU
   785  	AVSUBWU
   786  	AVSUBVU
   787  	AXVADDBU
   788  	AXVADDHU
   789  	AXVADDWU
   790  	AXVADDVU
   791  	AXVSUBBU
   792  	AXVSUBHU
   793  	AXVSUBWU
   794  	AXVSUBVU
   795  
   796  	// LSX and LASX Bit-manipulation Instructions
   797  	AVANDB
   798  	AVORB
   799  	AVXORB
   800  	AVNORB
   801  	AXVANDB
   802  	AXVORB
   803  	AXVXORB
   804  	AXVNORB
   805  	AVANDV
   806  	AVORV
   807  	AVXORV
   808  	AVNORV
   809  	AVANDNV
   810  	AVORNV
   811  	AXVANDV
   812  	AXVORV
   813  	AXVXORV
   814  	AXVNORV
   815  	AXVANDNV
   816  	AXVORNV
   817  
   818  	AVPCNTB
   819  	AVPCNTH
   820  	AVPCNTW
   821  	AVPCNTV
   822  	AXVPCNTB
   823  	AXVPCNTH
   824  	AXVPCNTW
   825  	AXVPCNTV
   826  
   827  	AVBITCLRB
   828  	AVBITCLRH
   829  	AVBITCLRW
   830  	AVBITCLRV
   831  	AVBITSETB
   832  	AVBITSETH
   833  	AVBITSETW
   834  	AVBITSETV
   835  	AVBITREVB
   836  	AVBITREVH
   837  	AVBITREVW
   838  	AVBITREVV
   839  	AXVBITCLRB
   840  	AXVBITCLRH
   841  	AXVBITCLRW
   842  	AXVBITCLRV
   843  	AXVBITSETB
   844  	AXVBITSETH
   845  	AXVBITSETW
   846  	AXVBITSETV
   847  	AXVBITREVB
   848  	AXVBITREVH
   849  	AXVBITREVW
   850  	AXVBITREVV
   851  
   852  	// LSX and LASX integer comparison instruction
   853  	AVSEQB
   854  	AXVSEQB
   855  	AVSEQH
   856  	AXVSEQH
   857  	AVSEQW
   858  	AXVSEQW
   859  	AVSEQV
   860  	AXVSEQV
   861  
   862  	// LSX and LASX integer div and mod instructions
   863  	AVDIVB
   864  	AVDIVH
   865  	AVDIVW
   866  	AVDIVV
   867  	AVDIVBU
   868  	AVDIVHU
   869  	AVDIVWU
   870  	AVDIVVU
   871  	AVMODB
   872  	AVMODH
   873  	AVMODW
   874  	AVMODV
   875  	AVMODBU
   876  	AVMODHU
   877  	AVMODWU
   878  	AVMODVU
   879  	AXVDIVB
   880  	AXVDIVH
   881  	AXVDIVW
   882  	AXVDIVV
   883  	AXVDIVBU
   884  	AXVDIVHU
   885  	AXVDIVWU
   886  	AXVDIVVU
   887  	AXVMODB
   888  	AXVMODH
   889  	AXVMODW
   890  	AXVMODV
   891  	AXVMODBU
   892  	AXVMODHU
   893  	AXVMODWU
   894  	AXVMODVU
   895  
   896  	// LSX and LASX shift operation instructions
   897  	AVSLLB
   898  	AVSLLH
   899  	AVSLLW
   900  	AVSLLV
   901  	AVSRLB
   902  	AVSRLH
   903  	AVSRLW
   904  	AVSRLV
   905  	AVSRAB
   906  	AVSRAH
   907  	AVSRAW
   908  	AVSRAV
   909  	AVROTRB
   910  	AVROTRH
   911  	AVROTRW
   912  	AVROTRV
   913  	AXVSLLB
   914  	AXVSLLH
   915  	AXVSLLW
   916  	AXVSLLV
   917  	AXVSRLB
   918  	AXVSRLH
   919  	AXVSRLW
   920  	AXVSRLV
   921  	AXVSRAB
   922  	AXVSRAH
   923  	AXVSRAW
   924  	AXVSRAV
   925  	AXVROTRB
   926  	AXVROTRH
   927  	AXVROTRW
   928  	AXVROTRV
   929  
   930  	// LSX and LASX move and shuffle instructions
   931  	AVILVLB
   932  	AVILVLH
   933  	AVILVLW
   934  	AVILVLV
   935  	AVILVHB
   936  	AVILVHH
   937  	AVILVHW
   938  	AVILVHV
   939  	AXVILVLB
   940  	AXVILVLH
   941  	AXVILVLW
   942  	AXVILVLV
   943  	AXVILVHB
   944  	AXVILVHH
   945  	AXVILVHW
   946  	AXVILVHV
   947  
   948  	// LSX and LASX integer mul instructions
   949  	AVMULB
   950  	AVMULH
   951  	AVMULW
   952  	AVMULV
   953  	AVMUHB
   954  	AVMUHH
   955  	AVMUHW
   956  	AVMUHV
   957  	AVMUHBU
   958  	AVMUHHU
   959  	AVMUHWU
   960  	AVMUHVU
   961  	AXVMULB
   962  	AXVMULH
   963  	AXVMULW
   964  	AXVMULV
   965  	AXVMUHB
   966  	AXVMUHH
   967  	AXVMUHW
   968  	AXVMUHV
   969  	AXVMUHBU
   970  	AXVMUHHU
   971  	AXVMUHWU
   972  	AXVMUHVU
   973  
   974  	// LSX and LASX floating point instructions
   975  	AVFSQRTF
   976  	AVFSQRTD
   977  	AVFRECIPF
   978  	AVFRECIPD
   979  	AVFRSQRTF
   980  	AVFRSQRTD
   981  	AXVFSQRTF
   982  	AXVFSQRTD
   983  	AXVFRECIPF
   984  	AXVFRECIPD
   985  	AXVFRSQRTF
   986  	AXVFRSQRTD
   987  
   988  	AVADDF
   989  	AVADDD
   990  	AVSUBF
   991  	AVSUBD
   992  	AVMULF
   993  	AVMULD
   994  	AVDIVF
   995  	AVDIVD
   996  	AXVADDF
   997  	AXVADDD
   998  	AXVSUBF
   999  	AXVSUBD
  1000  	AXVMULF
  1001  	AXVMULD
  1002  	AXVDIVF
  1003  	AXVDIVD
  1004  
  1005  	AVFCLASSF
  1006  	AVFCLASSD
  1007  	AXVFCLASSF
  1008  	AXVFCLASSD
  1009  
  1010  	// LSX and LASX floating point conversion instructions
  1011  	AVFRINTRNEF
  1012  	AVFRINTRNED
  1013  	AVFRINTRZF
  1014  	AVFRINTRZD
  1015  	AVFRINTRPF
  1016  	AVFRINTRPD
  1017  	AVFRINTRMF
  1018  	AVFRINTRMD
  1019  	AVFRINTF
  1020  	AVFRINTD
  1021  	AXVFRINTRNEF
  1022  	AXVFRINTRNED
  1023  	AXVFRINTRZF
  1024  	AXVFRINTRZD
  1025  	AXVFRINTRPF
  1026  	AXVFRINTRPD
  1027  	AXVFRINTRMF
  1028  	AXVFRINTRMD
  1029  	AXVFRINTF
  1030  	AXVFRINTD
  1031  
  1032  	// LSX and LASX integer neg instructions
  1033  	AVNEGB
  1034  	AVNEGH
  1035  	AVNEGW
  1036  	AVNEGV
  1037  	AXVNEGB
  1038  	AXVNEGH
  1039  	AXVNEGW
  1040  	AXVNEGV
  1041  
  1042  	// LSX and LASX mul instructions that operate on even or odd positions
  1043  	AVMULWEVHB
  1044  	AVMULWEVWH
  1045  	AVMULWEVVW
  1046  	AVMULWEVQV
  1047  	AVMULWODHB
  1048  	AVMULWODWH
  1049  	AVMULWODVW
  1050  	AVMULWODQV
  1051  	AVMULWEVHBU
  1052  	AVMULWEVWHU
  1053  	AVMULWEVVWU
  1054  	AVMULWEVQVU
  1055  	AVMULWODHBU
  1056  	AVMULWODWHU
  1057  	AVMULWODVWU
  1058  	AVMULWODQVU
  1059  	AXVMULWEVHB
  1060  	AXVMULWEVWH
  1061  	AXVMULWEVVW
  1062  	AXVMULWEVQV
  1063  	AXVMULWODHB
  1064  	AXVMULWODWH
  1065  	AXVMULWODVW
  1066  	AXVMULWODQV
  1067  	AXVMULWEVHBU
  1068  	AXVMULWEVWHU
  1069  	AXVMULWEVVWU
  1070  	AXVMULWEVQVU
  1071  	AXVMULWODHBU
  1072  	AXVMULWODWHU
  1073  	AXVMULWODVWU
  1074  	AXVMULWODQVU
  1075  	AVMULWEVHBUB
  1076  	AVMULWEVWHUH
  1077  	AVMULWEVVWUW
  1078  	AVMULWEVQVUV
  1079  	AVMULWODHBUB
  1080  	AVMULWODWHUH
  1081  	AVMULWODVWUW
  1082  	AVMULWODQVUV
  1083  	AXVMULWEVHBUB
  1084  	AXVMULWEVWHUH
  1085  	AXVMULWEVVWUW
  1086  	AXVMULWEVQVUV
  1087  	AXVMULWODHBUB
  1088  	AXVMULWODWHUH
  1089  	AXVMULWODVWUW
  1090  	AXVMULWODQVUV
  1091  
  1092  	AVSHUF4IB
  1093  	AVSHUF4IH
  1094  	AVSHUF4IW
  1095  	AVSHUF4IV
  1096  	AXVSHUF4IB
  1097  	AXVSHUF4IH
  1098  	AXVSHUF4IW
  1099  	AXVSHUF4IV
  1100  
  1101  	AVSETEQV
  1102  	AVSETNEV
  1103  	AVSETANYEQB
  1104  	AVSETANYEQH
  1105  	AVSETANYEQW
  1106  	AVSETANYEQV
  1107  	AVSETALLNEB
  1108  	AVSETALLNEH
  1109  	AVSETALLNEW
  1110  	AVSETALLNEV
  1111  	AXVSETEQV
  1112  	AXVSETNEV
  1113  	AXVSETANYEQB
  1114  	AXVSETANYEQH
  1115  	AXVSETANYEQW
  1116  	AXVSETANYEQV
  1117  	AXVSETALLNEB
  1118  	AXVSETALLNEH
  1119  	AXVSETALLNEW
  1120  	AXVSETALLNEV
  1121  
  1122  	ALAST
  1123  
  1124  	// aliases
  1125  	AJMP = obj.AJMP
  1126  	AJAL = obj.ACALL
  1127  	ARET = obj.ARET
  1128  )
  1129  
  1130  func init() {
  1131  	// The asm encoder generally assumes that the lowest 5 bits of the
  1132  	// REG_XX constants match the machine instruction encoding, i.e.
  1133  	// the lowest 5 bits is the register number.
  1134  	// Check this here.
  1135  	if REG_R0%32 != 0 {
  1136  		panic("REG_R0 is not a multiple of 32")
  1137  	}
  1138  	if REG_F0%32 != 0 {
  1139  		panic("REG_F0 is not a multiple of 32")
  1140  	}
  1141  	if REG_FCSR0%32 != 0 {
  1142  		panic("REG_FCSR0 is not a multiple of 32")
  1143  	}
  1144  	if REG_FCC0%32 != 0 {
  1145  		panic("REG_FCC0 is not a multiple of 32")
  1146  	}
  1147  	if REG_V0%32 != 0 {
  1148  		panic("REG_V0 is not a multiple of 32")
  1149  	}
  1150  	if REG_X0%32 != 0 {
  1151  		panic("REG_X0 is not a multiple of 32")
  1152  	}
  1153  }
  1154
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